Design Of Parallel Architectures Research Articles

Design of an efficient routing algorithm on the WK-recursive network

The WK-recursive network proposed by Vecchia and Sanges[1] is widely used in the design and implementation of local area networks and parallel processing architectures. It provides a high degree of regularity and scalability, which conform well to a design and realization of distributed systems involving a large number of computing elements. In this paper, the routing of a message is investigated on the WK-recursive network, which is key to the performance of this network. We present an efficient shortest path algorithm on the WK-recursive network, which is simpler than Chen and Duh[2] in terms of design complexity.

Parallel Hardware Implementation of Walsh Hadamard Transform

The Walsh Hadamard Transform is a powerful notion in digital signal processing. This paper explains the construction of parallel hardware architecture using the mathematical concept of Kronecker product based approach to Walsh Hadamard Transform and its simulation using Verilog. This architecture is simulated here using Field Programmable Gate Array (FPGA) technology in Verilog Spartan 3e platform. Furthermore, this paper illustrates the fast algorithm and parallel computational result of both one-dimensional and two-dimensional transforms using the Kronecker product.This algorithm can be used to implement a systolic array based dedicated hardware for computation of the transform. Our proposed hardware design for the Walsh Hadamard Transform will be used in various digital signal processing applications. The systematic derivation of parallel architecture design using the concept of Kronecker product and stride permutation would depict the real time processing rather than conventional way and reducing time complexity using minimal resources is a challenging task.

Multi-core parallel architecture design and experiment for deep learning model training

Multi-core parallel architecture design and experiment for deep learning model training

Research on parallel architecture design of radar real-time signal processing based on CPU-GPU heterogeneous platform

Research on parallel architecture design of radar real-time signal processing based on CPU-GPU heterogeneous platform

Design for parallel computation of model-based signal processing in Thomson scattering diagnostic

The Thomson Scattering (TS) diagnostic system calculates electron temperature and density profiles of tokamak plasma. The diagnostic is enabled by measuring and analyzing pulse signals of scattered laser light in the tokamak plasma. In order to improve accuracy of the diagnostic, it is necessary to reduce noise level of the pulse signals. In KSTAR, a fast digitizer with 5 GS/s has been adopted for obtaining the pulse shape information, and a research of model-based signal processing for the pulse signals has been conducted. In this paper, we present a new approach for the model-based signal processing and its parallel computation architecture design to improve its computation speed. As our approach, we conduct a nonlinear least square method in frequency domain by taking Fourier Transformation (FT) of the TS pulse model containing a convolution operator. Then, we can obtain algebraic functions for the transformed model and its Jacobian, which can reduce amount of computation and can be computed in parallel respect to frequency component. We implement the parallel computation of the algorithm in Graphical Processing Unit (GPU) and evaluate its effectiveness in terms of computation performance, convergence analysis, and variation of the model parameters.

Architecture Design for Feature Extraction and Template Matching in a Real-Time Iris Recognition System

Real-time support for an iris recognition algorithm is a considerable challenge for a portable system that is commonly used in the field. In this paper, an efficient parallel and pipeline architecture design for the feature extraction and template matching processes in the Ridge Energy Direction (RED) algorithm for iris recognition is presented. Several techniques used in the proposed architecture design to reduce the computational complexity while supporting a high performance capability include (i) a circle approximation method for the iris unwrapping process, (ii) a parallel design with an on-chip buffer for 2D convolution in the feature extraction process, and (iii) an approximation method for log2 and inverse-log2 conversion in the template matching process. Performance analysis shows that the proposed architecture achieves a speedup of 881 times compared to the conventional method. The proposed design can be integrated with an embedded microprocessor to realize a complete system-on-chip solution for a portable iris recognition system.

Hitting Times for Random Walks on Sierpiński Graphs and Hierarchical Graphs

AbstractThe Sierpiński graphs and hierarchical graphs are two much studied self-similar networks, both of which are iteratively constructed and have the same number of vertices and edges at any iteration, but display entirely different topological properties. Both graphs have a large variety of applications: Sierpiński graphs have a close connection with WK-recursive networks that are employed extensively in the design and implementation of local area networks and parallel processing architectures, while hierarchical graphs can be used to model complex networks. In this paper, we study hitting times for several absorbing random walks in Sierpiński graphs and hierarchical graphs. For all considered random walks, we determine exact solutions to hitting times for both graphs. The obtained explicit expressions indicate that the hitting times in both graphs behave quite differently. We show that the structural difference of the graphs is responsible for the disparate behaviors of their hitting times.

The parallelism motifs of genomic data analysis.

Genomic datasets are growing dramatically as the cost of sequencing continues to decline and small sequencing devices become available. Enormous community databases store and share these data with the research community, but some of these genomic data analysis problems require large-scale computational platforms to meet both the memory and computational requirements. These applications differ from scientific simulations that dominate the workload on high-end parallel systems today and place different requirements on programming support, software libraries and parallel architectural design. For example, they involve irregular communication patterns such as asynchronous updates to shared data structures. We consider several problems in high-performance genomics analysis, including alignment, profiling, clustering and assembly for both single genomes and metagenomes. We identify some of the common computational patterns or ‘motifs’ that help inform parallelization strategies and compare our motifs to some of the established lists, arguing that at least two key patterns, sorting and hashing, are missing.This article is part of a discussion meeting issue ‘Numerical algorithms for high-performance computational science’.

A Method for Large-Scale Parallel Simulation of Reactor Structural Mechanics

The structural mechanics simulation in reactor is an extremely complicated problem, which includes statics, fluid-induced vibration and wear. Because the entire structural mechanics simulation require dividing into 10 billion mesh elements, and then a large number of equations are generated to solve, the demand for high performance computing is urgent. Therefore, we conduct researches on E-class supercomputers, including reactor core geometric modeling, tens of billions of meshing, addition of physical parameters, regional decomposition, and solution of ultra-large sparse matrix equations. Furthermore, we propose a parallel workflow design, function design and architecture design scheme for large-scale parallel simulation of Generation IV reactors structural mechanics based on E-class supercomputer. By combining and optimizing of existing meshing tools and matrix equation solving methods, and finally verified its feasibility and correctness through calculation examples. In addition, the efficiency of the large-scale parallelism has also been significantly improved.

BLASTP-ACC: Parallel Architecture and Hardware Accelerator Design for BLAST-Based Protein Sequence Alignment.

In this study, we design a hardware accelerator for a widely used sequence alignment algorithm, the basic local alignment search tool for proteins (BLASTP). The architecture of the proposed accelerator consists of five stages: a new systolic-array-based one-hit finding stage, a novel RAM-REG-based two-hit finding stage, a refined ungapped extension stage, a faster gapped extension stage, and a highly efficient parallel sorter. The system is implemented on an Altera Stratix V FPGA with a processing speed of more than 500 giga cell updates per second (GCUPS). It can receive a query sequence, compare it with the sequences in the database, and generate a list sorted in descending order of the similarity scores between the query sequence and the subject sequences. Moreover, it is capable of processing both query and subject protein sequences comprising as many as 8192 amino acid residues in a single pass. Using data from the National Center for Biotechnology Information (NCBI) database, we show that a speed-up of more than 3X can be achieved with our hardware compared to the runtime required by BLASTP software on an 8-thread Intel Xeon CPU with 144GB DRAM.

Spectral Properties of Extended Sierpiński Graphs and Their Applications

The eigenvalues of a graph present a wide range of applications in structural and dynamical aspects of the graph. Determining and analyzing spectra of a graph has been an important and exciting research topic in recent years. In this paper, we study the spectra and their applications for extended Sierpinski graphs, which are closely related to WK-recursive networks that are widely used in the design and implementation of local area networks and parallel processing architectures. Moreover, a particular case of extended Sierpinski graphs is the dual of Apollonian network, which displays the prominent scale-free small-world characteristics as observed in various real networks. We derive recursive relations of the characteristic polynomials for extended Sierpinski graphs at two successive iterations, based on which we determine all the eigenvalues, their corresponding multiplicities and properties. We then use the obtained eigenvalues to evaluate the number of spanning trees, Kirchhoff index of extended Sierpinski graphs, as well as mean hitting time and cover time for random walks on the graphs.

A Configurable High Speed Crossbar Network on FPGA

The MPSoC platform plays a vital role in the design of parallel processor architectures. However, it poses a great challenge to design a configurable high-speed network regarding as the processors growing isomerization and reconfigurable. This paper proposes a configurable crossbar on-chip interconnection method based on FPGA, which can provide high speed high speed through Xilinx Fast Simplex Link (FSL) for processing elements include processors and hardware IP. We built a prototype system on FPGA to evaluate the transfer time and hardware costs of the crossbar network architectures. The experimental results show that each word can be reduced by 10 cycles, and the entire transmission delay only accounts for 6% of the total system operation time.

Foreword to the special issue of the workshop on high performance computing systems (XVIII Simpósio em Sistemas Computacionais de Alto Desempenho, WSCAD 2017)

Foreword to the special issue of the workshop on high performance computing systems (XVIII Simpósio em Sistemas Computacionais de Alto Desempenho, WSCAD 2017)

A new parallel simulation method for massive crowd

With the advent of multi-core and even many-core processors, massively parallel computing processing has presented a trend of low cost and popularity. It provides new technical means and feasible solutions for the rapid simulation calculation of large-scale group movements and the simulable problem of super-large group movements. In the process of parallel computing, the design of parallel architecture and parallel algorithm is closely related to the group motion simulation algorithm itself due to the original task needs to be decomposed. A parallel simulation algorithm for the continuum crowds has been proposed in this paper. We use the transition block-based scene segmentation algorithm on the management node to divide the simulated scene after initializing the virtual scene, and assign each block to a different computing node for processing. Then, the compute node gets information about the individual it is responsible for. Based on the method, a parallel simulation prototype system was developed on the Sugon high-performance computing platform. Experimental results show that our parallel simulation algorithm can increase the efficiency of scene-rendering and solve the bottleneck in group scale.

A resource-efficient parallel architecture for infrared image stripe noise removal based on the most stable window

Stripe noise is a common phenomenon arises in the multi-detectors infrared imaging equipment, which not only generally destroys the quality of the image, but also seriously affects the subsequent processing of the image. We exploit the stripe noise features of infrared image, and find that the adjacent noise difference can be well described by the difference of the mean values of adjacent rows in infrared images with the mean compensation and the two-point correction principle. Based on this, a novel stripe noise removal algorithm based on stable window is designed, it is not only effective to remove stripe noise in infrared image without causing undesired blurring effects and artifacts, but also efficient in terms of storage and computing resource utilization for real-time processing. In addition, in order to meet the demands of image real-time processing on satellites, we also design a low-latency, low-energy and highly-paralleled architecture for the de-noising algorithm, and implement it on a field programmable gate array (FPGA) processor. Experimental results show that the proposed algorithm outperforms the other current methods, and it can not only has a better performance in visualeffect and objective quality than otherstate-of-the-art de-noising methods, but also has obvious advantages in the consumption of storage resources due to the design of resource-efficient parallel architecture. For instance, in the consumption of Block RAM storage, compared with the TPC method, this proposed algorithm reduces 80% memory, and gets a significant improvement of the processing speed.

English

English

Application of the Hamiltonian circuit Latin square to a Parallel Routing Algorithm on Generalized Recursive Circulant Networks

A generalized recursive circulant network(GR) is widely used in the design and implementation of local area networks and parallel processing architectures. In this paper, we investigate the routing of a message on this network, that is a key to the performance of this network. We would like to transmit maximum number of packets from a source node to a destination node simultaneously along paths on this network, where the i th packet traverses along the i th path. In order for all packets to arrive at the destination node securely, the i th path must be node-disjoint from all other paths. For construction of these paths, employing the Hamiltonian Circuit Latin Square(HCLS), a special class of (n x n) matrices, we present O(n 2 ) parallel routing algorithm on generalized recursive circulant networks.

Customizable hardware design of fuzzy controllers applied to autonomous car driving

Nowadays, final products often encompass a certain intelligence therein to deal with variation or lack of precision in the sensing input data. This intelligence is usually acquired via the utilization of existing soft techniques, such as artificial neural networks, genetic algorithms and fuzzy control, among others. Thus, it is profitable to have on-the-shelf shell scalable and adaptive hardware designs that implement these soft techniques. This availability allows for an immediate embedding of any of those designs onto final products. This usually entails a reduced time-to-market of the product. Process control is one of the many applications that took advantage of the fuzzy paradigm. In general, controllers are embedded into the controlled device. This paper presents a novel design of a reconfigurable efficient parallel architecture to implement fuzzy controllers on hardware with almost no design effort for final users. The proposed architecture is herein proven suitable for embedding. It is customizable, so it allows the setup and configuration of the controller parameters, and hence its use for any problem application. Two fuzzy controllers that model autonomous car driving are implemented and their cost and performance evaluated.

Design and implementation of parallel video combiner architecture for multi-user video conferencing at ultra-high definition resolution

In software driven multi-user video conferencing systems, consumer progression towards ultra-high definition (i.e., 8 k) resolution introduces new challenges to the video combination process in sustaining smooth combined video playback at high frame rates. As such, this paper analyzes the underlying architecture of a conventional video combiner to identify the performance impact of combined video frame rates at ultra-high definition resolutions. Then, two straightforward parallel video combination architectures using software application threads, namely PVC-1 and PVC-2, are studied as a benchmark. In PVC-1, the number of application threads tallies with the number of client videos to be combined, which improves playback performance at the expense of inconsistencies in inset client frame rates within a combined video. PVC-2 includes a synchronizer to address these inconsistencies, but exhibits marginal performance gains. To address the aforementioned problems, a balanced workload parallel video combiner architecture is proposed, namely PVC-3. In this architecture, a balanced workload management algorithm stitches client videos into an ultra-high definition combined frame, based on the number of available logical processors on a multi-core processor. This method improves frame rate performance and sustains consistent client frame rates within a combined video. Experimental results suggest that PVC-3 is superior over PVC-2 and achieves a frame rate performance gain of 27 % against a conventional video combiner for a combined video of 16 clients (each at a resolution of 720p) and zero standard deviation in combined frame rate consistency.

Design of a set of One-to-Many Node-Disjoint and Nearly Shortest Paths on Recursive Circulant Networks

The recursive circulant network G(N,d) can be widely used in the design and implementation of parallel processing architectures. It consists of N identical nodes, each node is connected through bidirectional, point-to-point communication channels to different neighbors by jumping d i, where 0≤i≤?logd N??1. In this paper, we investigate the routing of a message on G(2 m ,4), a special kind of RCN, that is key to the performance of this network. On G(2 m ,4) we would like to transmit k packets from a source node to k destination nodes simultaneously along paths on this network, the i th packet will be transmitted along the i th path, where 1≤k≤m?1, 0≤i m ,4) for generating a set of one-to-many node-disjoint and nearly shortest paths, where each path is either shortest or nearly shortest and the total length of these paths is nearly minimum since the path is mainly determined by employing the Hungarian method.