Parallel Adder Research Articles

Quantum realization of the bilinear interpolation method for NEQR

In recent years, quantum image processing is one of the most active fields in quantum computation and quantum information. Image scaling as a kind of image geometric transformation has been widely studied and applied in the classical image processing, however, the quantum version of which does not exist. This paper is concerned with the feasibility of the classical bilinear interpolation based on novel enhanced quantum image representation (NEQR). Firstly, the feasibility of the bilinear interpolation for NEQR is proven. Then the concrete quantum circuits of the bilinear interpolation including scaling up and scaling down for NEQR are given by using the multiply Control-Not operation, special adding one operation, the reverse parallel adder, parallel subtractor, multiplier and division operations. Finally, the complexity analysis of the quantum network circuit based on the basic quantum gates is deduced. Simulation result shows that the scaled-up image using bilinear interpolation is clearer and less distorted than nearest interpolation.

An enhanced high-speed multi-digit BCD adder using quantum-dot cellular automata

The advent of development of high-performance, low-power digital circuits is achieved by a suitable emerging nanodevice called quantum-dot cellular automata (QCA). Even though many efficient arithmetic circuits were designed using QCA, there is still a challenge to implement high-speed circuits in an optimized manner. Among these circuits, one of the essential structures is a parallel multi-digit decimal adder unit with significant speed which is very attractive for future environments. To achieve high speed, a new correction logic formulation method is proposed for single and multi-digit BCD adder. The proposed enhanced single-digit BCD adder (ESDBA) is 26% faster than the carry flow adder (CFA)-based BCD adder. The multi-digit operations are also performed using the proposed ESDBA, which is cascaded innovatively. The enhanced multi-digit BCD adder (EMDBA) performs two 4-digit and two 8-digit BCD addition 50% faster than the CFA-based BCD adder with the nominal overhead of the area. The EMDBA performs two 4-digit BCD addition 24% faster with 23% decrease in the area, similarly for 8-digit operation the EMDBA achieves 36% increase in speed with 21% less area compared to the existing carry look ahead (CLA)-based BCD adder design. The proposed multi-digit adder produces significantly less delay of (N –1) + 3.5 clock cycles compared to the N* One digit BCD adder delay required by the conventional BCD adder method. It is observed that as per our knowledge this is the first innovative proposal for multi-digit BCD addition using QCA.

Recursive Formulation Based Parallel Self Timed Adder Design Based Architectural Design and CMOS Implementation Approach

Recursive Formulation Based Parallel Self Timed Adder Design Based Architectural Design and CMOS Implementation Approach

Summation of binary codes without carry

The paper considers the operation of summation of binary codes in the scheme of a multi digit parallel adder without carry. The process of the operation of summation uses a pairing algorithm that provides for a logarithmic complexity to the algorithm of the calculation in the adder’s scheme. Since the codes for the operation of summation, known in the literature, such as Galois field codes, the XAND codes, are defined by the systems of recurrent codes that contain one of the initial codes of complete combinatorial system with repetition, then the given codes are a particular case of the class of combinatorial systems of binary codes with a ring structure and initial code of complete combinatorial system with repetition. Therefore, the only basis of the mentioned systems of binary codes indicates the usefulness of their classification generalization, within the framework of the operation of summation, on the basis of a single criterion – an object of binary codes. Thus, the generalization of the classification of binary codes simplifies the structure of the subject area, increases the variety of systems of binary codes, in particular, for their application in arithmetic operations with binary numbers. It was established that the properties of the recurrent method of the synthesis of binary codes allow focusing the principle of building codes in the range of complete combinatorial system with repetition, which ensures reduction of the thesaurus of the parallel adder of binary codes without carry. The results of this study may be a component of the technology of designing electronic computing systems because: – they expand the apparatus of obtaining recurrent binary codes for their application in the information technology; – they provide a possibility to control the selection of the code at the stage of designing a computing device; – they help predict the impact of the implementation of the selected code for the solution of problems of the information systems.. – they minimize hardware costs associated with the selection of the system of binary code for the calculation.

Minimization of Area and Power in Digital System Design for Digital Combinational Circuits

This paper proposes enhanced parallel adder architectures with low power and reduced area. It includes, design of three different parallel adders such as Ripple Carry Adder (RCA), Carry Look ahead Adder (CLA) and Carry Select Adder (CSA). All three adders are designed in Gate Diffusion Interface (GDI) technique as well as traditional CMOS method. Adder is a basic common combinational digital circuit. Adders are important components in signal processing, image and video processing applications. So it is essential to have compact, low power adder design for these application fields. GDI based digital system design offers reduction in power consumption and area over head. When compared to traditional CMOS based design, GDI uses very less transistor to implement a function. The GDI and CMOS methods are taken in to account for the comparison of design parameters such as design layout, node to node delay, total power dissipation and speed of operation. All three parallel adders are designed in traditional CMOS as well as GDI method. The simulations are done using Microwind2 and DSCH2 analysis software tools and the results between those two types are listed below. This proposed adder circuits can be used in all high speed multipliers and filter designs where low power and reduced area is a major concern.

Low Power High Speed based Various Adder Architectures using SPST

Adder is a circuit that is combinational andcalculates the sum of three (full adder) or two (half adder) inputs. Full adder can be cascaded to produce n-stages of adder. This cascaded adder structure is called as parallel adder. The sum and carry outputs of any stage cannot be calculated until the input carry occurs, this leads to a delay in the addition process. In order to overcome the delay, carry look ahead adder is proposed which is said to be a fast adder. To improve the speed of vary look ahead adder, Spurious Power Suppression Technique (SPST) is used. This paper discusses 8-bit adder consisting of three architectures parallel adder, normal carry look ahead adder and SPST carry look ahead adder. The results were simulated using Xilinx tools and as shown, the power has decreased for both the SPST carry look ahead adder and the SPST ripple carry adder. The code was written in Verilog HDL and tested on a Xilinx FPGA test board as a part of a velocity measurement circuit for an Electromagnetic Projectile Launcher.

Design of a compact reversible fault tolerant division circuit

In this paper, we propose an n-bit reversible fault tolerant binary division circuit, where n is the number of bits of dividend and divisor. We present a new algorithm for division operation with the optimum time complexity in the design of dividers. The proposed division method consists of four steps: Firstly, it considers floating-point data and rounding. Secondly, it performs correctly rounded division. Thirdly, it performs correct rounding from one sided approximations. Finally, it calculates the result of the division operation. The proposed design of the divider circuit shows that it is composed of reversible fault tolerant multiplexers, parallel-in–parallel out (PIPO) left shift registers, D-Latch, rounding and normalization registers and parallel adder. The proposed divisor register and the parallel adder have the minimum quantum cost with respect to the existing ones. Fredkin gates and Feynman double gates are also used to form the divider circuit. Finally, we present an algorithm to construct a compact n-bit reversible fault tolerant binary division circuit. In this paper, a new algorithm has also been proposed to reduce the number of steps required for performing division operation. Our circuit performs better than the existing approaches considering all the efficiency parameters of reversible logic design which includes number of gates, constant inputs, garbage outputs, quantum cost and delay of the circuit, e.g., for a 256-bit binary division circuit, the proposed reversible fault tolerant binary division circuit improves 27.75% on the number of gates, 0.03% on garbage outputs, 11.04% on quantum cost, 8.94% on constant inputs and 23.50% on delay with respect to the best known existing divider circuit. We also simulate the proposed n-bit reversible fault tolerant binary division circuit using Microwind DSCH 3 which shows the correctness of the circuit.

Optical Arithmetic Operation Using Optical Demultiplexer

Using Terahertz Optical Asymmetric Demultiplexer (TOAD) based switch we have designed all-optical parallel half adder and full adder. The approach to design this all-optical arithmetic circuit not only enhances the computational speed but also is capable of synthesizing light as input to produce desire output. The main advantage of parallel circuit is synchronization of input which is not required. All the circuits are designed theoretically and verified through numerical simulations.

ERSFQ 8-Bit Parallel Adders as a Process Benchmark

We have designed and demonstrated two versions of an ERSFQ 8-bit parallel adder. ERSFQ is a resistor-free approach to dc biasing of Single Flux Quantum circuits that dissipates orders of magnitude less power than a traditional RSFQ logic while operating and has zero dissipation in inactive mode. The adders were designed for and fabricated with various fabrication processes, including HYPRES's 1.0-μm 4-layer 4.5 kA/cm 2 process, HYPRES's 0.25-μm 4-layer 4.5 kA/cm 2 process, HYPRES's 0.25-μm 6-layer 4.5 kA/cm 2 planarized process, and MIT Lincoln Lab's 0.25-μm 4-layer 10 kA/cm 2 process. These circuits serve as a good LSI fabrication process benchmark. We describe design and report on test results of all versions of the adder.

Transmission Gate base Programmable Binary Incrementer Decrementer

We can use a high-speed parallel adder in incrementer / decrementer to improve the operating speed which can count up or count down from the loaded value by one step in one clock cycle. For this, design of a faster and highly reliable adder is of major importance. Thus, much effort has been invested in the research that has led to faster and more efficient ways to perform this operation. To prove the efficiency of the proposed method, the circuit is simulated in pass transistor CMOS 50nm technology and some simulation parameters are calcultes in the layout of the circuit. The binary decrementer reduces the stored binary data in memopry or register by ‘1’. This can be done by using 2’s complement method by using XOR gates which convert binary data in 1’s complement and then by addition of binary ‘1’ it can be converted to 2’s complement form. It is made by cascading ‘n’ full adders for ‘n’ number of bits i.e. the storage capacity of the register to be decremented. Hence, a 4-bit binary decrementer requires 4 cascaded half adder circuits. This paper presents the eight bit CMOS base incrementer and decrementer logic design using eight bit adder and subtractor. The parametric simulation is done on MICROWIND layout editor tool. The any conventional static CMOS adder with pullup and pulldown logic requires 32 MOSFET whereas our design adder requires 30 MOSFETs. Our design methodology is based on static CMOS logic and transmission gate logic to achieve smaller delays, reduce power dissipation and optimized area.

Recursive Approach to the Design of a Parallel Self-Timed Adder

This brief presents a parallel single-rail self-timed adder. It is based on a recursive formulation for performing multibit binary addition. The operation is parallel for those bits that do not need any carry chain propagation. Thus, the design attains logarithmic performance over random operand conditions without any special speedup circuitry or look-ahead schema. A practical implementation is provided along with a completion detection unit. The implementation is regular and does not have any practical limitations of high fanouts. A high fan-in gate is required though but this is unavoidable for asynchronous logic and is managed by connecting the transistors in parallel. Simulations have been performed using an industry standard toolkit that verify the practicality and superiority of the proposed approach over existing asynchronous adders.

Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count

A multiplier-less architecture based on algebraic integer representation for computing the Daubechies 6-tap wavelet transform for 1-D/2-D signal processing is proposed. This architecture improves on previous designs in a sense that it minimizes the number of parallel 2-input adder circuits. The algorithm was achieved using brute-force numerical optimization of the algebraic integer representation. The proposed architecture furnishes exact computation up to the final reconstruction step, which is the operation that maps the exactly computed filtered results from algebraic integer representation to fixed-point. Compared to our recent work, this architecture shows a reduction of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$27\cdot n-16$</tex></formula> adder circuits, where <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$n$</tex> </formula> is the number of wavelet decomposition levels. The design is physically implemented for a 4-level 1-D/2-D decomposition using a Xilinx Virtex-6 vcx240t-1ff1156 field programmable gate array (FPGA) device operating at up to a maximum clock frequency of 344/ 168 MHz. The FPGA implementation of 1-D/2-D are tested using hardware co-simulation using an ML605 board with clock of 100 MHz. A 45 nm CMOS synthesis of 2-D designs show improved clock frequency of better than 306 MHz for a supply voltage of 1.1 V.

FPGA Implementation of Area Efficient and Delay Optimized 32-Bit SQRT CSLA with First Addition Logic

Binary addition is a fundamental operation in most digital circuits. There are a variety of adders, each has certain performance. Parallel adders are used for fast binary addition which plays a crucial impersonation in majority of digital circuit designs including digital signal processors (DSP) and microprocessor data path unit. In this project we implement the parallel adder 32-bit SQRT CSLA(square root carry select adder) with BEC logic and compare them to the simple ripple carry adder(RCA),carry look ahead adder(CLA) & carry select adder(CSLA). To reduce the area and delay of n-bit CSLA, n-bit SQRT CSLA with BEC-1 logic was designed. Since CSLA is area consuming because it consists of dual RCA in structure. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. So as to achieve the same an efficient gate-level modification would be implemented to vitally reduce the delay of the CSLA. 32bit SQRT CSLA with BEC-1logic is already designed which reduces the area of corresponding CSLA. But while performing area reduction and power reduction it is found that there is an increase in the delay. So in this project we put forward the structure of square root CSLA (SQRT CSLA) using “first addition logic circuit(FAL)” for 32-bit instead of BEC-1 logic circuit. The performance in terms of area, delay and utilization of power are calculated for SQRT CSLA with FAL and are compared with existing CSLA, SQRT CSLA and SQRT CSLA with BEC-1 logic.

Hardware implementation of 32-bit high-speed direct digital frequency synthesizer.

The design and implementation of a high-speed direct digital frequency synthesizer are presented. A modified Brent-Kung parallel adder is combined with pipelining technique to improve the speed of the system. A gated clock technique is proposed to reduce the number of registers in the phase accumulator design. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The ROM lookup table (LUT) is partitioned into three 4-bit sub-ROMs based on angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2 : 1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz. These techniques make the direct digital frequency synthesizer an attractive candidate for wireless communication applications.

Constructing DNA-based Parallel Adder with Basic Logic Operations in the Adleman-Liption Model

It is shown first by Adleman that deoxyribonucleic acid (DNA) strands could be employed towards calculating solution to an instance of The NP-complete Hamiltonian Path Problem (HPP). Lipton also demonstrated that Adleman's techniques could be used to solve the satisfiability (SAT) problem. In this paper, it is demonstrated how the DNA operations presented by Adleman and Lipton can be used to construct bio-molecular parallel adder with basic logic operations in the Adleman-Lipton model.

Multioperand Redundant Adders on FPGAs

Although redundant addition is widely used to design parallel multioperand adders for ASIC implementations, the use of redundant adders on Field Programmable Gate Arrays (FPGAs) has generally been avoided. The main reasons are the efficient implementation of carry propagate adders (CPAs) on these devices (due to their specialized carry-chain resources) as well as the area overhead of the redundant adders when they are implemented on FPGAs. This paper presents different approaches to the efficient implementation of generic carry-save compressor trees on FPGAs. They present a fast critical path, independent of bit width, with practically no area overhead compared to CPA trees. Along with the classic carry-save compressor tree, we present a novel linear array structure, which efficiently uses the fast carry-chain resources. This approach is defined in a parameterizable HDL code based on CPAs, which makes it compatible with any FPGA family or vendor. A detailed study is provided for a wide range of bit widths and large number of operands. Compared to binary and ternary CPA trees, speedups of up to 2.29 and 2.14 are achieved for 16-bit width and up to 3.81 and 3.11 for 64-bit width.

A Novel Design of Reversible Multiplier Circuit

Adders and multipliers are two main parts of arithmetic units of computer hardware and play important role in reversible computations. This paper introduces a novel reversible 4×4 multiplier circuit that is based on an advanced “Partial Product Generation Circuits” (PPGC) with Peres gates only without duplicating gates. Again, an optimized Peres full adder reversible gate is used in “Reversible Parallel Adder” (RPA) part with accompaniment with the carry save adder technique. Comparison of the proposed design with previous ones shows that the proposed reversible multiplier improves the quantum parameters. The proposed design shows lower quantum cost and depth with the help of a novel design in PPGC. The circuit cost of the proposed design is a little higher than the best compared design, but the proposed design shows the lowest total cost which is defined as sum of quantum cost and circuit cost. Moreover, the number of gates, garbage input and output has no change regarding to the best compared design. The proposed multiplier can be generalized as an n×n bit multiplication.

8-channel acquisition system for time-correlated single-photon counting

Nowadays, an increasing number of applications require high-performance analytical instruments capable to detect the temporal trend of weak and fast light signals with picosecond time resolution. The Time-Correlated Single-Photon Counting (TCSPC) technique is currently one of the preferable solutions when such critical optical signals have to be analyzed and it is fully exploited in biomedical and chemical research fields, as well as in security and space applications. Recent progress in the field of single-photon detector arrays is pushing research towards the development of high performance multichannel TCSPC systems, opening the way to modern time-resolved multi-dimensional optical analysis. In this paper we describe a new 8-channel high-performance TCSPC acquisition system, designed to be compact and versatile, to be used in modern TCSPC measurement setups. We designed a novel integrated circuit including a multichannel Time-to-Amplitude Converter with variable full-scale range, a D∕A converter, and a parallel adder stage. The latter is used to adapt each converter output to the input dynamic range of a commercial 8-channel Analog-to-Digital Converter, while the integrated DAC implements the dithering technique with as small as possible area occupation. The use of this monolithic circuit made the design of a scalable system of very small dimensions (95 × 40 mm) and low power consumption (6 W) possible. Data acquired from the TCSPC measurement are digitally processed and stored inside an FPGA (Field-Programmable Gate Array), while a USB transceiver allows real-time transmission of up to eight TCSPC histograms to a remote PC. Eventually, the experimental results demonstrate that the acquisition system performs TCSPC measurements with high conversion rate (up to 5 MHz/channel), extremely low differential nonlinearity (<0.04 peak-to-peak of the time bin width), high time resolution (down to 20 ps Full-Width Half-Maximum), and very low crosstalk between channels.

FPGA Based Systolic Array for Modular Multiplication Using Precomputed Addition Value

본 논문에서는 몽고메리 알고리듬을 기반으로 하여 고속 모듈러 곱셈을 위한 새로운 시스톨릭 VLSI 알고리듬을 제안하고, 미리 계산된 덧셈 값을 이용한 FPGA에 기반한 시스톨릭 어레이를 하드웨어로 구현한다. 제안한 알고리듬에서 이 덧셈 값은 CLA 방식의 직렬 체인으로 구성된 n-bit 병렬 가산기를 사용하여 얻게 된다. 모듈러 곱셈의 계산 속도를 증가시키기 위해서 두 개의 기본 셀 (PE_X와 PE_Y)을 설계하여 시스톨릭 어레이를 구현한다. 구현 결과를 통하여 제안한 셀 PE_Y와 시스톨릭 어레이에 대한 기존의 방법과의 비교에서 셀 수는 각각 약 43%와 5% 정도 감소하였고, 임계 경로도 각각 11%와 12% 정도 감소함을 보였다.

Design and implementation of Parallel Prefix Adders using FPGAs

Adders are known to have the frequently used in VLSI designs. In digital design we have half adder and full adder, main adders by using these adders we can implement ripple carry adders. RCA use to perform any number of addition. In this RCA is serial adder and it has commutation delay problem. If increase the ha&fa simultaneously delay also increase. That's why we go for parallel adders(parallel prefix adders). IN the parallel prefix adder are ks adder(kogge-stone),sks adder(sparse kogge-stone),spaning tree and brentkung adder. These adders are designd and implemented on FPGA sparton3E kit. Simulated and synthesis by model sim6.4b, Xilinx ise10.1.