PAM-4 Data Research Articles

Evaluating PAM-4 Data Transmission Quality Using Multi-Dimensional Mapping of Received Symbols

Evaluating PAM-4 Data Transmission Quality Using Multi-Dimensional Mapping of Received Symbols

Local oscillators-free chip-enabled W-band wireless IM-DD PAM-4 data transmission with simultaneous dual-laser modulation and envelope detection.

Wireless data traffic is expected to exponentially increase in the future, and meeting this demand will require high data rate photonic-wireless links operating in the W-band (75-110 GHz). For this purpose, pulse-amplitude-modulation with four levels (PAM-4)-based intensity modulation and direct detection (IM-DD) photonic-wireless systems are preferred due to their simplified configuration. In this Letter, we present an experimental demonstration of an IM-DD PAM-4 photonic-wireless link in the W-band, leveraging a monolithic dual-laser photonic chip to enhance integration. Through injection-locking by an optical comb, the chip generates a W-band wireless signal via photo-mixing with a photodiode. This comb injection approach facilitates the phase correlation of the chip's two modes, resulting in a stabilized beat note. Additionally, the on-chip integration of the dual lasers enables the modulation of the two modes with a single modulator, improving the signal-to-noise ratio (SNR) while eliminating the need for extra splitters or combiners. Meanwhile, the envelope detector (ED) plays a crucial role in the simplified configuration, contributing to the overall decrease in size, weight, power, and complexity of the system. The integration of the chip-based phase-locked light source and the utilization of the ED thus signify noteworthy features of our experimental setup, which functions without the necessity of both optical and electrical local oscillators. PAM-4 signal modulation is simultaneously applied to the two coherent optical carriers. Our experiments have effectively transmitted 5 and 10 Gbaud PAM-4 W-band wireless signals in a cost-effective, lightweight, and straightforward configuration, achieving a line data rate of up to 20 Gbit/s economically. These experimental results demonstrate the practical potential of implementing fully integrated photonic-wireless transmitters.

High-speed data transmission over a microresonator frequency comb with dispersion compensation for augmented data rates and reach.

Microresonator frequency comb-based high-speed data transmission provides a pathway towards augmented data capacity without increasing the number of laser sources. Their use with intensity-modulated direct detection modulation (IMDD) formats is especially pertinent in data center communications where minimizing cost, latency and complexity is paramount. This however implies that the same extent of digital signal processing techniques commonly used in coherent detection for the management of fiber impairments including chromatic dispersion are not available. With the proliferation of silicon photonics technologies in data center transceivers integrated dispersion compensation which can overcome fiber impairments would be of great merit. We demonstrate low power generation of the primary comb state in a silicon nitride microresonator and transmission of 25 Gb/s NRZ and 50 Gb/s PAM4 data over 20 km of single mode fiber. This represents the longest fiber reach demonstrated to date for the transmission of IMDD data using an integrated, microresonator frequency comb. An integrated, tunable grating device for dispersion compensation that reduces dispersion impairments after several fiber lengths generates significant improvements in the eye diagram, six orders of magnitude improvement in the bit-error rate and 14 dB improvement in the transmitter and dispersion eye closure quaternary values. Concurrently, doubling data transmission is demonstrated via polarization multiplexing a comb line and successful dispersion compensation of up to 20 km.

Si Mach-Zehnder Modulator for PAM-4, QAM-OFDM, and DMT Transmission at C-Band

A silicon (Si) Mach-Zehnder modulator (MZM) is demonstrated for 10-km SMF Link at C-band (1550 nm), which allows the pre-emphasized 4-level pulse amplitude modulation (PAM-4) data transmission at 50 GBaud (100 Gbit/s) per channel. By employing the pre-emphasis to the PAM-4 data over different links, the channel dispersion-induced power fading can be compensated. The PAM-4 data with improved spectral usage efficiency in limited bandwidth is employed to encode the Si MZM, and the maximal transmission capacities of 50 GBaud for back-to-back (BtB), 50 GBaud for 2-km SMF, and 26 GBaud for 10-km DSF under KP4-FEC criterion are respectively obtained for providing 100/100/52 Gbit/s data transmission with qualified bit error ratios of 1.5×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> /2×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> /1.4×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> . The penalties on the sensitivity of the receiving power are 0.32 dB for 50-GBaud PAM-4 data after 2-km-SMF link and 0.64 dB for 26-GBaud PAM-4 data over 10-km DSF as compared to the BtB case. Such a scheme takes advantages including the lower power consumption with less circuit complexity than traditional push-pull driven operation, which certifies the 50-GBaud PAM-4 data capability per channel for inter-data-center applications. In addition, this Si MZM device can also modulate the pre-emphasized 16-QAM OFDM data at 140 Gbit/s and the bit-loaded DMT data at 153 Gbit/s.

A Low-Latency, Low-Jitter Retimer Circuit for PCIe 6.0

As the PCIe 6.0 specification places higher requirements on signal integrity and transmission latency, it becomes especially important to improve signal transmission performance at the physical layer of the transceiver interface. Retimer circuits are a key component of high-speed serial interfaces, and their delay and jitter size directly affect the overall performance of PCIe. For the typical retimer circuit with large-latency and low-jitter performance, this paper proposes a low-latency and low-jitter Retimer circuit based on CDR + PLL architecture for PCIe 6.0, using a jitter-canceling filter circuit to eliminate the frequency difference between the retiming clock and data, reduce the retiming clock jitter, and improve the quality of Retimer output data. The data are sampled using the retiming clock and then output, avoiding the problem of large penetration latency of typical retimer circuits. The circuit is designed using the CMOS 28 nm process. Simulation results show that when 112 Gbps PAM4 data are input to the retimer circuit, the Retimer penetration latency is 27.3 ps, which is 83.5% lower than the typical Retimer structure; the output jitter data are 741 fs, a 31.4% reduction compared to the typical retimer structure.

Ultra-compact silicon photonics highly dispersive elements for low-latency signal processing.

On-chip optical group-velocity dispersion (GVD) is highly desired for a wide range of signal processing applications, including low-latency and low-power-consumption dispersion compensation of telecommunication data signals. However, present technologies, such as linearly chirped waveguide Bragg gratings (LCWBGs), employ spectral phase accumulation along the frequency spectrum. To achieve the needed specifications in most applications, this strategy requires device lengths that are not compatible with on-chip integration while incurring in relatively long processing latencies. Here, we demonstrate a novel design strategy that utilizes a discretized and bounded spectral phase filtering process to emulate the continuous spectral phase variation of a target GVD line. This leads to a significant reduction of the resulting device length, enabling on-chip integration and ultra-low latencies. In experiments, we show GVD compensation of both NRZ and PAM4 data signals with baud rates up to 24 GBd over a 31.12-km fibre-optic link using a 4.1-mm WBG-based on-chip phase filter in a silicon-on-insulator (SOI) platform, at least 5× shorter compared to an equivalent LCWBG, reducing the processing latency down to ∼ 100 ps. The bandwidth of the mm-long device can be further extended to the THz range by employing a simple and highly efficient phase-only sampling of the grating profile. The proposed solution provides a promising route toward a true on-chip realization of a host of GVD-based all-optical analog signal processing functionalities.

50 Gbit/s PAM4 Data Transmission Over 500-m Single-Mode Fiber Using an 880-nm Single Mode VCSEL

Error-free 50 Gbit/s PAM4 data transmission over 500-m single mode fiber was successfully realized using our oxide-confined 880-nm single-mode high-speed VCSELs. This transmission was accomplished because of the flat frequency response of the VCSEL across a wide bias span. Static characteristics and high-speed modulation properties at room temperature and high operation temperature were studied in detail. Data transmission experiments for the 880-nm VCSEL with 4- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> oxide-aperture diameter was performed. A 50-Gbps PAM4 module was packaged for data transmission. Error-free 50 Gbit/s PAM4 data transmission over 500-m single mode fiber was successfully realized. The proposed VCSEL is fit for the 400G DR8 module because of its 500-m single-channel 50 Gbit/s error-free transmission. Compared with commonly used DML, VCSELs are evidently advantageous in cost and power consumption.

Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector

This article presents design techniques for a PAM-4 baud-rate digital clock and data recovery (CDR) circuit utilizing a stochastic phase detector (SPD). The proposed baud-rate phase detector (PD) is designed in an inductive and stochastic way, so there is a clear difference from the existing deductive and logical method used in sign-sign Mueller–Müller PD (SS-MMPD), a representative baud-rate PD. By collecting the histograms of the sequential PAM-4 patterns under EARLY and LATE sampling phases and calculating optimal weights, the SPD exhibits optimized phase-locking characteristic that maximizes the PAM-4 vertical eye opening (VEO) compared with the conventional logical approaches. In addition, unlike SS-MMPD, which may suffer from a severe multiple-locking problem, the SPD tracks a unique and optimal sampling phase even with an adaptive decision-feedback equalizer (DFE). For verification, a prototype PAM-4 receiver is fabricated in 40-nm CMOS technology and occupies 0.24 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Tested with PRBS-7 patterns, it achieves a bit error rate (BER) of less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-11}$ </tex-math></inline-formula> and energy efficiency of 2.4 pJ/b at 48 Gb/s.

A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing

This brief presents a 32-Gb/s PAM4-Binary bridge for the next-generation memory testing. The bridge incorporates all the required functions to evaluate a high-speed PAM4 memory using a low-speed NRZ tester. The low-speed data transmitted from the NRZ tester to the bridge are converted into high-speed PAM4 data through half-rate clock control and forwarded to the memory, and vice-versa. The ground-terminated PAM4 driver provides the single-ended output by controlling the output current with a 2-tap feed-forward equalizer, achieving a ratio level mismatch (RLM) of 0.95. To minimize the offset at the PAM4 receiver, the offset cancellation circuit with an offset of 2.76mV consisting of a CTLE and sampling latches is employed, and the horizontal margin of the received PAM4 signal is 50% for BER <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${ &lt; } 10^{-9}$ </tex-math></inline-formula> . An all-digital PLL integrated in the bridge doubles the 4-GHz WCK used as forwarded clock for the graphic memory. The count-based PAM4 eye-opening monitor is also proposed to find the optimal codes for the maximum eye opening using the PRBS7 data sequence. The bridge fabricated in the 40-nm CMOS technology occupies an active area of 1.6mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and dissipates 132mW.

Experimental investigation of VCSEL-based optical heterodyning with PAM 4 and envelop detection for 5G fronthaul systems

Vertical cavity surface-emitting lasers (VCSELs) are power-efficient optical sources for application in passive optical networks. Despite these sources having the potential of generating coherent high-frequency radio frequency signal, their application for high-order amplitude modulation formats is yet to be demonstrated experimentally. In this work, for the first time, we experimentally demonstrate a four-level pulse amplitude modulation (4-PAM) format on a photonically generated RF carrier signal using optical heterodyning of two independent VCSELs. Two low-power VCSELs were combined at an optical coupler and allowed to beat a PIN photodiode to generate a 10-GHz RF carrier. In the first demonstration, an 8.5 Gbps data signal was modulated on the photonically generated 10 GHz RF carrier. In the second demonstration, a 17-Gbps PAM-4 data signal was externally modulated onto the same VCSEL carrier, ultimately doubling the network bit rate. A simple digital signal processing (DSP) receiver was used as an alternative to costly receiver hardware to decode the transmitted PAM-4 data signal. A 24-km fiber transmission penalty of 7-dB was recorded when PAM-4 signal was photonically generated and transmitted. The penalty introduced by moving from binary transmission to PM-4 transmission was recorded to be 3-dB.

Error-free PAM-4 transmission by a high-speed plastic optical fiber without forward error correction.

This Letter reports, to the best of our knowledge, the first study in which error-free four-level pulse-amplitude modulation (PAM-4) transmission has been achieved using a graded-index plastic optical fiber (GI POF) without the use of forward error correction (FEC) techniques, at a high data rate (>50Gb/s), for short-reach applications (10 m). The GI POF that is developed has the characteristic microscopic heterogeneities in the fiber core material, which provide distinct mode coupling and significantly stabilize PAM-4 data transmission. The results of the study in this Letter indicate that the GI POF achieves highly stable PAM-4 transmission without the need for the current FEC techniques, which seriously increase the communication delay and power consumption of the transmission systems. Our GI POF material is paving the way for "material changes the system" approaches for achieving unprecedented optical interconnects in real time at a high speed and with low power consumption.

Self restorable intra data center interconnect based on multimode fiber and free-space optics

We demonstrate a high data rate and low-cost OM4 multimode fiber (MMF) and free-space optics (FSO)-based self-restorable 2 × 100 Gbps per wavelength intra data center interconnect between two pairs of servers. This transmission system is based on two vertical cavity surface-emitting lasers that are directly modulated with PAM-4 data at the rate of 100 Gbps and multiplexed using mode division multiplexing of two linearly polarized modes. In case a fault occurs in the MMF-based primary path, the traffic is shifted to FSO-based protection path through a specially designed triggering and switching mechanism. Offline digital signal processing is used at the receiver to process the received PAM-4 signal for compensating the effects of channel impairments. The performance of the proposed architecture is evaluated at link lengths of 35 and 70 m under normal and faulty scenarios. The effect of varying the refractive index structure parameter of the log-normal channel model and the effect of mode coupling between linearly polarized (LP) modes on the bit-error-rate performance is also analyzed under different conditions. We observe that the performance of the FSO-based protection path is better than the OM4-based primary path at a forward error correction limit of 3.8 × 10 − 3 bit-error-rate.

Tunable optical single-sideband generation for OOK and PAM4 data channels using an optical frequency comb and nonlinear wave-mixing.

We experimentally demonstrate tunable optical single-sideband (SSB) generation using a tapped-delay-line (TDL) optical filter for 10 and 20 Gbit/s on/off-keying (OOK) signals and a 20 Gbit/s four-level pulse-amplitude-modulated (PAM4) signal. The optical SSB filter is realized by using an optical frequency comb, wavelength-dependent delay, and nonlinear wave-mixing to achieve the TDL function. Moreover, SSB tunability is achieved by adjusting the amplitude, phase, frequency spacing, and number of selected optical frequency comb lines. We show that the one-sideband suppression of a double-sideband (DSB) channel can be enhanced as the number of taps is increased; however, we do measure a ∼1.5% error-vector-magnitude penalty. Furthermore, we demonstrate that the chromatic-dispersion-induced penalty after 80 km standard-single-mode-fiber transmission of a 10 Gbit/s SSB OOK signal without chromatic dispersion compensation has been reduced by >3dB when compared to DSB.

Low-chirp push-pull dual-ring modulator with 144 Gb/s PAM-4 data transmission.

We experimentally demonstrate a low-chirp high-speed push-pull dual-ring modulator. The device is formed by two parallel cascaded add-drop ring modulators which has a Fabry-Perot resonance spectrally similar as electromagnetically induced transparency (EIT) effect. Differential drive signals are applied to the two rings to shift the individual resonances towards opposite directions, creating intensity modulation with suppressed frequency chirp. We present static and dynamic characterization of the device, including chirp parameter. We also demonstrate 144 Gb/s PAM-4 data transmission with 1-km standard single-mode fiber (SSMF) with BER below hard-decision forward error correction (HD-FEC) threshold with 7% overhead.

23-dB average isolation using a silicon photonic Mach-Zehnder modulator.

We demonstrate an optical time-gate isolator entirely fabricated on the silicon-on-insulator (SOI) platform based on a conventional traveling-wave Mach-Zehnder modulator (TW-MZM) design. The device achieves 18.2 dB (22.7 dB) time-averaged isolation when driven with 2.0-Vpp (7.1-Vpp) differential clock signals at 6.8 GHz and biased at null. Under these conditions, the isolator blocks backward light at all time regardless of driver amplitude, but produces periodic modulation in the forward direction. Moreover, we embed our isolator in a digital communication link and measure a signal-to-noise ratio (SNR) penalty of only 0.5 dB due to the isolator at 13.6 Gbaud PAM-4 data rate. Our device can be integrated in larger circuits to protect laser sources or mitigate interference.

Silicon-organic hybrid (SOH) Mach-Zehnder modulators for 100 GBd PAM4 signaling with sub-1 dB phase-shifter loss.

We report on compact and efficient silicon-organic hybrid (SOH) Mach-Zehnder modulators (MZM) with low phase-shifter insertion loss of 0.7 dB. The 280 µm-long phase shifters feature a π-voltage-length product of 0.41 Vmm and a loss-efficiency product as small as aUπL = 1.0 VdB. The device performance is demonstrated in a data transmission experiment, where we generate on-off-keying (OOK) and four-level pulse-amplitude modulation (PAM4) signals at symbol rates of 100 GBd, resulting in line rates of up to 200 Gbit/s. Bit error ratios are below the threshold for hard-decision forward error correction (HD-FEC) with 7% coding overhead, leading to net data rates of 187 Gbit/s. This is the highest PAM4 data rate ever achieved for a sub-1 mm silicon photonic MZM.

150-GHz CMOS TX/RX With Digitally Predistorted PAM-4 Modulation for Terahertz Contactless/Plastic Waveguide Communications

In this article, 150-GHz CMOS transmitter (TX) and receiver (RX) are presented for contactless and plastic waveguide communications. The implemented system employs a four-level pulse-amplitude modulation (PAM-4) and noncoherent detection. The direct upconversion TX and self-mixing RX suffer amplitude nonlinearity and distort the carrier-modulated multilevel signals. A current-mode digital predistortion is integrated in the PAM-4 modulator to correct the nonlinearity for the carrier-modulated multilevel signaling. Coupling antennas are designed on FR4-HR substrates. The same antenna launches electromagnetic energy into plastic waveguides to extend the communication distance. A plastic printed circuit board (PCB) is introduced by inserting plastic waveguides into copper-coated slots on PCBs to realize terahertz PCB communications. The TX and RX are fabricated in the 28-nm standard bulk CMOS process. The system consumes 60.2 mW under 1.2/1.5 V supply while transferring 30 Gb/s PAM-4 data, achieving 2.01 pJ/bit energy efficiency.

Comparison of High-Speed PAM4 and QAM-OFDM Data Transmission Using Single-Mode VCSEL in OM5 and OM4 MMF Links

To realize the superiority of data transmission with reduced modal dispersion in OM4- and OM5-mulitmode fiber (MMF), a single transverse mode (SM) vertical cavity surface emitting laser (VCSEL), directly encoded with large-capacity data formats for transmissions in OM5-MMF and OM4-MMF, are compared. The SM-VCSEL contains a 12-μm mesa formed by double-oxidized AlGaAs layers, which confines a current-flow area within an aperture of 3 μm. The SM-VCSEL is lasing with a carrier-to-noise ratio of 34.4 dB and a linewidth of 0.05 nm. The SM-VCSEL is biased at 10Ith to provide a modulation bandwidth of 21.4 GHz and a relative intensity noise of -138 dBc/Hz. By encoding the SM-VCSEL with four-level pulse amplitude modulation (PAM-4) at 64 Gbit/s, the bit error ratio (BER) of 32-GBaud PAM-4 data is improved from 7.9 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> to 4.9 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> under a KP4-FEC criterion by replacing OM4-MMF with OM5-MMF. After OM5-MMF transmission, a bathtub BER plot shows bottom-eye, middle-eye, and top-eye jitter tolerances of 9.3, 10.6, and 7.1 ps, which are much wider than 6.9, 10.1, and 6.5 ps for OM4-MMF, respectively. When encoding the 16-QAM OFDM at 100 Gbit/s, OM5-MMF allows data transmission at 96-Gbit/s with a corresponding error vector magnitude, signal-to-noise ratio, and BER of 16.7%, 15.4 dB, and 3.6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> under preleveling at a slope of 0.3 dB/GHz. Because of the high effective modal bandwidth and low modal dispersion of the OM5-MMF, a relatively low receiving power penalty of 0.1 dB between 100-m and back-to-back (BtB) transmissions is obtained with either the pre-emphasized PAM-4 or the preleveled QAM-OFDM data format. By contrast, the receiving power penalty is 1.04 dB between 100 m and BtB cases during OM4-MMF transmission.

A 50-Gb/s PAM4 Si-Photonic Transmitter With Digital-Assisted Distributed Driver and Integrated CDR in 40-nm CMOS

A 50-Gb/s four-level pulse-amplitude modulation (PAM4) silicon photonic transmitter is presented, which is composed of a 40-nm bulk CMOS driver hybrid integrated with a 180-nm silicon-on-insulator (SOI) CMOS Mach–Zehnder modulator (MZM). To recover and demodulate 50-Gb/s PAM4 data into dual-25-Gb/s nonreturn to zero (NRZ) streams for the co-designed MZM digital-analog converter (DAC), a reference-less clock and data recovery (CDR) is integrated, and to achieve high swing and high speed, the driver is made in a distributed amplifier (DA), employing push–pull cells that are grouped in three segments. A digital-assisted distributed driver (DADD) that replaces the input T-line by segmented 2:1 multiplexers and buffers is, thus, proposed. Precise time gating in each segment allows for velocity match in both the DA and optical DAC, as well as the in-segment pre-emphasis without power-hungry analog delay stages. Measurement results show that the driver and CDR achieve 4-VPP differential swing, 1.19-ps rms jitter, and 1.34-W power consumption at 50 Gb/s. An optical transmitter is demonstrated by wire-bonding the driver to the MZM DAC, achieving 50-Gb/s PAM4 output with 6.35-ps rms jitter and improved linearity.

A Circuit-Level Implementation of Voltage-Tuning Scheme for Realizing Optical PAM-4 Using Three-Segment Microring Modulator

Silicon Photonics, as one of the solutions to satisfy ever-increasing data bandwidth growth, becomes more challenging due to the latest technologies such as Internet of Things (IoT). Higher order pulse amplitude modulation (PAM) schemes is one of the answers to push towards higher data transmission in the presence of bandwidth limited optical devices. In this paper, we have implemented a circuit-level PAM-4 transmitter design based on the voltage-tuning scheme for realizing optical PAM-4 using a three-segment microring modulator. Simulation results based on the extracted layout using TSMC 65nm LP technology and IMEC-ePIXfab SiPhotonics ISIPP50G technology show that our proposed circuit-level transmitter structure is able to achieve PAM-4 data rate of 25-Gb/s with extinction ratio of 9dB and PAM-4 energy efficiency of 0.5pJ/bit. The results also verify that the scheme is able to achieve high tuning flexibility, but the proposed transmitter will consume more power as a result.