Pair Of Processors Research Articles

Reliability Evaluation of Braided Networks Using A Recursive Method

The global reliability of a connected network reflects the probability of having a connected path between every pair of processors. Given any network, there are several ways of finding this reliability measure such as path set and cut set methods. These methods are computation extensive for large networks and do not utilize the symmetry of the networks. In this paper, we present a generalization of a special class of networks called Braided-Line networks and derive the reliability expressions for these networks using recursive techniques. These recursive techniques utilize the symmetry of the networks thus reducing the computation time of the global reliability substantially.

Allocating task interaction graphs to processors in heterogeneous networks

The problem of allocating task interaction graphs (TIGs) to heterogeneous computing systems to minimize job completion time is investigated. The only restriction is that the interprocessor communication cost is the same for any pair of processors. This is suitable for local area network based systems, such as Ethernet, as well as fully interconnected multiprocessor systems. An optimal polynomial solution exists if sufficient homogeneous processors and communication capacity are available. This solution is generalized to obtain two faster heuristics, one for the case of homogeneous processors and the other for heterogeneous processors. The heuristics were tested extensively with 60,900 systematically generated random TIGs and shown to be stable independent of the size of the TIG. A performance model is also proposed to predict the performance of the heuristic algorithms, and it is successful in explaining the experimental results qualitatively.

Justifying reliability claims for a fault-detecting parallel architecture

This paper describes ‘Goal Structuring Notation’ (GSN), a graphical notation that can be used to structure and present an argument justifying some aspect of system performance. The design of a fault-detecting processor pair is examined to determine the extent to which it is indeed ‘fault-detecting’. It is argued that for complex systems, difficulties with assessment arise not so much from a lack of analysis techniques, but from the need to integrate the results from many diverse analyses into a coherent and compelling argument. It is suggested that GSN provides a framework in which such an argument can be made.

Digital signal processing circuit board having use for voice processing system

A digital voice processing circuit board having use in a voice processing system wherein voice processing functions are run in software. This application of software allows a modular structure since the application software resides in boards that are coupled to a host computer. With this structure, the software can be updated as required and the capacity of the system can be expanded readily to meet increased needs. The digital voice processing board has an interface chip to which random access memories are connected for temporary storage of data and storage of the operating code for the voice processing card. The interface is in communication with an application processor which runs the application programming and database management. The application processor is in communication with and controls a pair of signal processors which are in communication with a time division multiplexer chip which in turn is in communication with the bus. The signal processors perform digital signal processing such as decoding control information, telephone processing, compression and decompression, and tone generation.

An Optimal Algorithm for Scheduling Interval Ordered Tasks with Communication on N Processors

The problem of scheduling task graphs on multiprocessor systems have received considerable attention in recent years. This problem is known to be NP-hard in its general form as well as many restricted cases. Few polynomial algorithms have been developed for solving special cases of the scheduling problem when the communication cost is not considered. For example, Papadimitriou and Yannakakis showed that unit execution time tasks in interval orders can be scheduled in linear time on N processors when communication cost is assumed to be zero. They have also shown that the generalization of this problem to arbitrary execution times is NP-complete. The complexity of the problem arises even more when communication among tasks is considered. Papadimitriou and Yannakakis also showed that the problem of optimally scheduling unit-time task graphs with communication on an unlimited number of processors is NP-complete. They provided a simple way to approximate the optimal schedule length within a factor of two. In this paper, we study the problem of scheduling task graphs with communication on a given number of processors when the task graph is an interval order. We introduce an optimal algorithm for solving the scheduling problem when the execution cost of the system tasks is identical and equal to the communication cost between any pair of processors.

Performance of Work-Optimal PRAM Simulation Algorithms on Coated Meshes

We study the effect of varying the multithreading level of processors in work-optimal PRAM simulation algorithms on coated meshes. A coated mesh consists of a mesh connected routing machinery and P processor & memory pairs that form a coat on the routing machinery. The algorithms studied are based on greedy routing, sorting, improved virtual leveled network technique, combining queues method, and synchronization wave. Our results show that increasing the multithreading level considerably improves the simulation cost. The cost can be decreased below 5 routing steps per P simulated PRAM processors. In case of one algorithm, even costs 1.1...2 are achieved.

A dynamically reconfigurable parallel processing system

A parallel processing system is described based on a number of microprocessor nodes interconnected by means of reconfigurable, reallocatable blocks of memory. The ideas presented address what the authors perceive as the drawbacks of current parallel microprocessor architectures such as transputer based systems. The concepts presented are applicable to a broad range of microprocessors and application areas. The system offers minimal communications latency between any arbitrary pair of processors in the system. Communicating processors are connected via a communications path on a point to point basis. The interconnection network is inherently reconfigurable. Reconfiguration occurs with no apparent overhead to the processor nodes. Communication paths between the processor nodes are implemented by shared memory blocks which, combined with dynamic reconfiguration and reallocation, overcome the bus bandwidth problem normally associated with shared memory architectures. Strategies for scaling the architecture are discussed. A working prototype of the system based on widely available, low-cost, off-the-shelf components demonstrates the feasibility of the architecture. Some preliminary performance figures are presented.

Optoelectronic wavelet processors based on Smartt interferometry

Optoelectronic wavelet-processor implementations based on Smartt interferometry are described for both one-dimensional (1-D) and two-dimensional (2-D) wavelet transforms. The 1-D processor study focuses on the processor's capability to perform the wavelet transform when the wavelets are defined in the time domain. The experimental results indicate that the system preserves all the phase information of the selected mother wavelets and thus delivers the true wavelet transform. The 2-D version of the processor is designed for the implementation of the complex wavelet transform. This processor will be valuable for applications, such as image coding-decoding, for which the preservation of phase information is necessary. A pair of prototype processors that incorporates.the 1-D and the 2-D systems has been built and tested to mechanical vibrations. High-quality reconstructed images were also obtained from the experimental data. The proposed systems have great potential for many practical applications.

RSM — a restricted shared memory architecture for high speed interprocessor communication

A restricted shared memory (RSM) architecture is presented which employs dual-port memory blocks for high speed interprocessor communication. The dual-port memory blocks are connected to processor buses in a triangular matrix for full processor connectivity. Multiple pairs of processors can communicate concurrently as a dedicated dual-port memory block connects each processor pair. The prototype RSM is developed for a cluster of five transputers' which provides a contention-free medium for message passing and data sharing. Several data transfer protocols including general, overlapped and broadcast, are implemented and their performance is evaluated. A message can be broadcast to all or selected processors in a single step. The RSM architecture is also fault tolerant in terms of fault containment and isolation of faulty units.

THE TIME COMPLEXITY OF SCHEDULING INTERVAL ORDERS WITH COMMUNICATION IS POLYNOMIAL

Papadimitrjou and Yannakakis showed that unit execution time tasks in interval orders can be scheduled in linear time on N processors when communication cost is ignored. The objective function was to minimize the schedule length. They have also shown that the generalization of this problem to arbitrary execution times is NP- complete . In this paper, we study the problem of scheduling task graphs with communication on N processors when the task graph is an interval order. We prove that this scheduling problem can be solved in polynomial time when the execution cost of the system tasks is identical and equal to the communication cost between any pair of processors. We introduce an algorithm of O(Ne) to minimize the schedule length, where e is the number of arcs in the interval order.

A distributed recovery block approach to fault-tolerant execution of application tasks in hypercubes

An approach to fault-tolerant execution of real-time application tasks in hypercubes is proposed. The approach is based on the distributed recovery block (DRB) scheme and does not require special hardware mechanisms in support of fault tolerance. Each task is assigned to a pair of processors forming a DRB computing station for execution in a dual-redundant and self-checking mode. Assignment of all tasks in an application in such a form is called the full DRB mapping. The DRB scheme was developed as an approach to uniform treatment of hardware and software faults with the effect of fast forward recovery. However, if the system developer is concerned with hardware fault possibilities only, then forming DRB stations becomes a mechanical process not burdening the application software designer in any way. A procedure for converting an efficient nonredundant task-to-processor mapping into an efficient full DRB mapping is presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Conservative parallel simulation of continuous time Markov chains using uniformization

The authors describe parallel algorithms for simulating certain continuous time Markov chains, such as those arising in queueing network models of distributed computing systems or communications systems. The algorithms are based on the technique of uniformization. Two variations of a conservative parallel simulation algorithm are presented. In each algorithm, a relatively short presimulation is performed to identify those times, and only those times, at which the simulation algorithm requires processor pairs to synchronize. Speedup studies of the algorithms, performed on a 16-node Intel iPSC/2 hypercube, are presented and discussed. >

Design machines: Algebraically well described interconnection networks

We present a method constructing efficient multiprocessor networks based on combinatorial designs and group theory. The principal idea is to combine 1-factorizations of complete graphs on each block of certain 2-designs, to obtain efficient networks with a short maximum distance between any pair of processors. Using a smart multiplexing technique derived from the 1-factorization of complete graphs we can circumvent the restrictive Moore bound for (Δ, d)-graphs.

A programmable digital filter IC employing multiple processors on a single chip

A programmable general-purpose digital filter IC that employs multiple processing units on a single chip is described. The processors operate in parallel and communicate through on-chip dual-access storage register blocks. The processors are arranged as a ring with the locally shared register blocks between each adjacent pair of processors. It is shown that this ring of processors is capable of realizing a rich variety of filter structures operating at the maximum possible instruction execution rate. Fast real-time processing at video rates is obtained by using a fast hardware multiplier in each processor and by employing a design that permits each processor to simultaneously execute multiplication and addition operations in a single instruction cycle. An advantage of the design is the free passing of data between adjacent processors due to each register block's dual port. A ring of five such processors can be implemented in 2- mu m CMOS technology on a single 7.9 mm*9.2 mm chip operating at data rates up to 40 MHz. >

Routing with Polynomial Communication-Space Trade-Off

This paper presents a family of memory-balanced routing schemes that use relatively short paths while storing relatively little routing information. The quality of the routes provided by a scheme is measured in terms of their stretch, namely, the maximum ratio between the length of a route connecting some pair of processors and their distance. The hierarchical schemes$\mathcal{H}_k $ (for every integer $k\geqq 1$) presented in this paper guarantee a stretch factor of $O( k^2 )$ on the length of the routes and require storing at most $O( k \cdot n^{1/k} \cdot \log n\log D )$ bits of routing information per vertex in an n-processor network with diameter D. The schemes are name independent and applicable to general networks with arbitrary edge weights. This improves on previous designs whose stretch bound was exponential in k. The proposed schemes are based on a new efficient solution to a certain graph-theoretic problem concerning sparse graph covers. The new cover technique has already found several other applications in the area of distributed computing.

Identifying migrated objects using multicast addresses

All objects in a distributed system must be associated with some form of identifier if they are to communicate with other objects. Should an object migrate between a pair of processors, it then becomes necessary to institute measures to ensure that communication can continue. Seven object identification techniques are examined here, and their application to object migration and communication is considered. The use of multicast addresses to identify objects is then proposed. Data from an experimental Ethernet illustrates the benefits of using multicast addresses, including a reduction in identifier management overheads, lower transmission times, and less network traffic.

Optimal communication algorithms for hypercubes

We consider the following basic communication problems in a hypercube network of processors: the problem of a single processor sending a different packet to each of the other processors, the problem of simultaneous broadcast of the same packet from every processor to all other processors, and the problem of simultaneous exchange of different packets between every pair of processors. The algorithms proposed for these problems are optimal in terms of execution time and communication resource requirements; that is, they require the minimum possible number of time steps and packet transmissions. In contrast, algorithms in the literature are optimal only within an additive or multiplicative factor.

A fail-safe interlocking system for railways

A new approach to the design of microprocessor-based failsafe systems for railways that was used to design the FIRM architecture is described. The approach involves assigning appropriate levels of safety to system functions, depending on how critical they are, instead of using the same safety standard for all functions. The FIRM (short for failsafe interlocking system for railways using microprocessors) architecture uses a pair of processors that operate in a see-saw mode, with one or more pairs kept on standby. The installation and testing of an engineering prototype of the architecture that was fabricated for Indian Railways are discussed. >

Scheduling independent two processor tasks on a uniform duo-processor system

The problem to be addressed is one of scheduling multiprocessor tasks, some of which require more than one processor at a time. We extend this model by introducing uniform duo-processor systems consisting of pairs of processors having the same speeds. A low order polynomial-time algorithm for preemptive scheduling of uni- and two-processor tasks is proposed, when schedule length is the performance measure.

Constructing disjoint paths on expander graphs

In a typical parallel or distributed computation model processors are connected by a spars interconnection network. To establish open-line communication between pairs of processors that wish to communicate interactively, a set of disjoint paths has to be constructed on the network. Since communication needs vary in time, paths have to be dynamically constructed and destroyed. We study the complexity of constructing disjoint paths between given pairs of vertices on expander interconnection graphs. These graphs have been shown before to possess desirable properties for other communication tasks. We present a sufficient condition for the existence ofK≦n Q edge-disjoint paths connecting any set ofK pairs of vertices on an expander graph, wheren is the number of vertices andϱ<1 is some constant. We then show that the computational problem of constructing these paths lies in the classes Deterministic-P and Random-P C. Furthermore, we show that the set of paths can be constructed in probabilistic polylog time in the parallel-distributed model of computation, in which then participating processors reside in the nodes of the communication graph and all communication is done through edges of the graph. Thus, the disjoint paths are constructed in the very computation model that uses them. Finally, we show how to apply variants of our parallel algorithms to find sets ofvertex-disjoint paths when certain conditions are satisfied.