Pair Of Wafers Research Articles

Fatigue Damage Diagnostics–Prognostics Framework for Remaining Life Estimation in Adhesive Joints

This work presents an integrated damage diagnostics–prognostics framework for remaining useful life (RUL) estimation in the adhesively bonded joints under fatigue loading. A matching pursuit algorithm is proposed as the diagnostics technique for estimating the damage extent followed by the fatigue damage growth (FDG) simulator as the predictive model for simulating fatigue degradation. The framework calibrates the FDG simulator by quantifying uncertainties in fatigue model parameters using the damage extent data. Bayesian inference via the Markov chain Monte Carlo method is used to quantify uncertainties and estimate the probabilistic RUL from the quantified uncertainties. The FDG simulator encompasses a physics-based fatigue damage degradation model with an artificial neural network-based hybrid machine-learning model for tracing the damage progression. In the diagnostic technique, ultrasonic guided waves are excited into the structure using a pair of piezoelectric wafers, and the damage extent is quantified by reconstructing the reflected signal from the bond region. The proposed diagnostic technique is verified using the ultrasonic signal obtained from the finite element simulations. The damage prognostics part of the integrated framework is verified by estimating RUL in a mixed-mode failure joint specimen using the experimental fatigue damage progression data. In addition, the integrated framework is then verified by estimating RUL in two adhesively bonded joints: a single lap joint and a tapered single lap joint using Gaussian noise added synthetic data and diagnostic damage extent data.

Surface Density Gradient Engineering Precedes Enhanced Diffusion; Drives CMOS In-Line Process Flow Compatible Cu–Cu Thermocompression Bonding at 75 °C

Diffusion is one of the most critical and key factor for achieving low temperature and low pressure thermocompression bonding. In this work, we propose a novel concept of modifying density conditions within the Cu films. The density of film was varied by varying the DC bias applied for the sputter deposition. While two samples of different densities are brought in contact with each other, Cu atoms from the thin film having higher density of atoms tends to interdiffuse into the thin film having lower density. Optimal dc biasing conditions for pair of wafers were figured out based on the pre-bonding characterizations and it yielded an excellent bonding at Sub 100 °C. No observable bond interface X-TEM images and bond strength of 164 MPa confirmed the quality of bonding. Furthermore, bonded structure undergone various reliability tests include multiple current stressing test, temperature cycling test and relative humidity test confirms Cu-Cu bonding using surface density gradient engineering is stable and promising candidate for future 3D IC integration applications.

Improved Copper Damascene Wires Using Direct Plate on Cobalt Process

We preset an electrochemical damascene fill process for copper which is capable of direct nucleation and fill on a cobalt substrate. This process preserves the benefits of a cobalt liner while simultaneously reducing problems inherent in the use of a PVD copper seed on small interconnect features. The process depends upon the use of an additive which enhances the action of traditional damascene suppressors. This enables improved nucleation on the Co substrate without sacrificing the ability of the bath to produce the bottom-up fill typical of damascene Cu plating. We demonstrate good fill across a wafer on a thin, resistive cobalt substrate, producing lines with better electrical properties than a control created using PVD seed followed by a traditional damascene process. As integrated circuit features get smaller, the use of electrochemical copper metallization for interconnects has become more challenging. A major reason for this is the requirement for a PVD copper seed layer on top of a cobalt liner to enable traditional damascene plating. In very small features, the seed layer takes up a substantial portion of the feature volume. This produces a serious risk of voids as either the PVD itself or subsequent electrodeposition can close off the feature top before it has been filled with metal. One way to extend the manufacturability of copper interconnects is to eliminate the PVD copper deposition step entirely and instead plate directly on the cobalt liner. Direct plating of copper onto cobalt is a challenging problem. Cobalt dissolves readily in acidic solutions used for damascene Cu plating. Further, the reduction potential of Cu(II) is such that it will galvanically corrode Co substrates exposed to it. Copper has been successfully plated on cobalt, but previous attempts use heavily complexed alkaline baths to preserve the cobalt substrate. Unfortunately, both high pH and heavily complexed copper inhibit the ability of traditional damascene additives to produce good bottom up fill. Our approach to this problem has been to use an additive which improves the nucleation of Cu on Co not by complexing the Cu in the bulk solution, but by improving the ability of damascene suppressor molecules to quickly and effectively inhibit Cu plating on newly created Cu surfaces. This fast inhibition makes it more favorable for Cu nuclei to expand across the Co surface rather than growing in a more perpendicular direction. The faster passivation of the surface with Cu in turn dramatically reduces Co corrosion loss to the bath. Because this behavior is produced using traditional damascene additives, bottom up fill can be established after nucleation occurs if plating conditions are properly chosen. Good nucleation and fill on a 36nm pitch structure can be seen in the benchtop scale fill progression tests shown in Figure 1. Nucleation is slightly rougher than is observed when plating on a Cu substrate, but fill ability is sufficient to compensate. A Sabre electrodeposition tool from Lam Research was used to scale this process up to 300mm wafer plating. In Figure 2 electrical data statistics from these wafers are compared with similar results form a pair of control wafers plated using traditional damascene process on a PVD Cu substrate. A portion of this work was performed by the Research Alliance Teams at various IBM Research and Development facilities. Figure 1

Deep reactive ion etched anti-reflection coatings for sub-millimeter silicon optics.

Refractive optical elements are widely used in millimeter and sub-millimeter (sub-mm) astronomical telescopes. High-resistivity silicon is an excellent material for dielectric lenses given its low loss tangent, high thermal conductivity, and high index of refraction. The high index of refraction of silicon causes a large Fresnel reflectance at the vacuum-silicon interface (up to 30%), which can be reduced with an anti-reflection (AR) coating. In this work, we report techniques for efficiently AR coating silicon at sub-mm wavelengths using deep reactive ion etching (DRIE) and bonding the coated silicon to another silicon optic. Silicon wafers of 100 mm diameter (1 mm thick) were coated and bonded using the silicon direct bonding technique at high temperature (1100°C). No glue is used in this process. Optical tests using a Fourier transform spectrometer show sub-percent reflections for a single-layer DRIE AR coating designed for use at 320 μm on a single wafer. Cryogenic (10 K) measurements of a bonded pair of AR-coated wafers also reached sub-percent reflections. A prototype two-layer DRIE AR coating to reduce reflections and increase bandwidth is presented, and plans for extending this approach are discussed.

Enhancement of Bonding Strength for Low Temperature Si3N4/Si3N4 Direct Wafer Bonding by Nitrogen-Plasma Activation and Hydrofluoric Pre-dip

Prior to exposing to plasma for surface activation, dipping the silicon nitride (Si3N4) surfaces on one pair of silicon wafers in diluted hydrofluoric (HF) solution is for the sake of low temperature wafer bonding. We found the bonding strength (2,500 mJ/m2) reaches the level of silicon fracture through a 200°C annealing less than 24 hours compared with 400 hours done by HF-dip merely. We suggest the bonding mechanism as following: the HF-dip treatment passivated the Si dangling Si bonds on the broken Si-N network of the Si3N4 surface to form sufficient high density of Si-H bonds. And then the application of N2 plasma treatment can increase the density of Si-H-N bonds for forming hydrogen bonds between the two mating surfaces to bridge the two bonding surfaces resulting in high bonding strength after annealing.

Enhancement of Bonding Strength for Low Temperature Si3N4/Si3N4 Direct Wafer Bonding by Nitrogen-Plasma Activation and Hydrofluoric Pre-dip

Applying the hydrofluoric (HF) pre-dip treatment on the surfaces of one pair of bare silicon wafers before performing plasma-activation wafer bonding approach, the annealing temperature for achieving silicon fracture bonding strength can be drastically reduced as low as 75°C. In comparison, the annealing temperature is 700°C or higher in the case of a conventional HF-dip hydrophobic wafer bonding or 300-400°C through the assistance of hydrogen trapping defective surface layer caused by boron ion implantation.Applying the same bonding approach to the Si3N4/Si3N4 wafer bonding, we found the bonding strength reaches the level of silicon fracture through a 200°C annealing less than 24 hours compared with 400 hours done by HF-dip only. The bonding mechanism is proposed as following: the HF-dip treatment passivated the Si dangling bonds on the Si surface or the broken Si-N network of the Si3N4 surface to form sufficient high density of Si-H bonds. And then the application of N2 plasma treatment increases the density of Si-H-N bonds for forming hydrogen bonds which bridges the two bonding surfaces resulting in high bonding strength after annealing.

Low temperature Cu [sbnd]Cu thermo-compression bonding with temporary passivation of self-assembled monolayer and its bond strength enhancement

Self-assembled monolayer (SAM) of alkane-thiol is formed on copper (Cu) thin layer coated on silicon (Si) wafer with the aim to protect the surface against excessive oxidation during storage in the room ambient. After 3 days of storage, the temporary SAM layer is desorbed with in situ anneal in inert ambient to uncover the clean Cu surface. A pair of wafers is bonded at 250 °C. Clear evidences of in-plane and out-of-plane Cu grain growth are observed resulting in a wiggling bonding interface. This gives rise to enhancement in shear strength in the bonded Cu Cu layer.

열가압 접합 공정으로 제조된 Cu-Cu 접합의 계면 접합 특성 평가

3 차원 패키징을 위해 열가압 공정으로 제조된 Cu-Cu 접합 계면의 접합 특성을 평가하기 위해 4 점 굽힘 실험을 수행하였다. Cu 가 코팅된 Si 웨이퍼 2 장을 350 ℃ 에서 1 시간 동안 15kN 의 하중으로 접합시킨후, 동일한 온도에서 1 시간동안 어닐닝을 수행하였다. 접합된 웨이퍼를 30 ㎜ × 3 ㎜ 크기로 잘라 시험편을 준비하였다. 시험편의 중심에 깊이 400 ㎛ 의 노치를 가공하였다. 시험기에 광학계를 부착하여 노치에서의 크랙 발생과 계면에서의 크랙 진전을 관찰하였다. 일정한 테스트 속도로 실험을 수행하여, 이에 상응하는 하중을 측정하였다. Cu-Cu 접합 계면 에너지는 10.36 J/㎡ 으로 측정되었으며, 파괴된 계면을 분석하였다.표면 분석 결과, SiO₂ 와 Ti 의 계면에서 파괴가 일어났음을 확인하였다.

Void Density Reduction at the Cu–Cu Bonding Interface by Means of Prebonding Surface Passivation with Self-Assembled Monolayer

A self-assembled monolayer (SAM) of 1-hexanethiol is formed on a copper (Cu) thin layer coated on silicon (Si) wafers with the aim to protect the surface against contamination during storage in room ambient. After 3 days of storage, the SAM is desorbed with an in situ annealing step in inert N 2 ambient to provide a clean Cu surface and a pair of wafers is bonded at 250°C. It is observed with scanning acoustic microscopy that there is a clear reduction in the interfacial void density in the bonded pair compared with the control sample without SAM passivation.

Correlation of electrical and luminescence properties of a dislocation network with its microscopic structure

AbstractThe direct bonding of Si wafers reproducibly forms dislocation networks (DN) with a microscopic structure defined by the mutual crystallographic orientation between the pair of wafers used for the bonding procedure. This allows studying the electrical and optical properties of specific dislocations. In the present work three different DN structures were investigated using transmission electron microscopy (TEM), photoluminescence (PL) and deep level transient spectroscopy (DLTS). The results show close correlation between the structural, electrical and optical properties of dislocations and opens a possibility to identify structural peculiarities of the dislocations responsible for the high intensity of photoluminescence. Namely, the obtained results suggest that PL at ∼0.8 eV is related to screw dislocations in DN. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Cohesive zone model for direct silicon wafer bonding

Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

Development of a Silicon Based Air-Breathing Micro Direct Methanol Fuel Cell

As one part of the efforts to break the bottleneck of power sources in development of integrated micro systems, a silicon based air-breathing micro direct methanol fuel cell (μDMFC) was developed in this work. By using micro-machining technologies compatible with that in processing of the other MEMS devices, the anode and cathode micro flow-field plates had been successfully fabricated on a pair of 2-inch silicon wafers. The silicon μDMFC was evaluated under ambient conditions using aqueous methanol solution with different concentrations. Results show that open circuit potential (OCP) of the μDMFC was above to 0.6 V, and by using 3mol/L methanol, the peak current density and power density of the silicon μDMFC could reach 28mA/cm2 and 8mW/cm2, respectively.

Energy-rate consideration in wafer bonding

In the present study, we consider the bonding process of a pair of wafers with rough surfaces via an energy-rate concept in which “rate” refers to “area rate”. A finite element numerical simulation for a rough surface with periodical distributed asperities bonded onto a rigid half-space is carried out for demonstrating the energy-rate concept. The simulation reveals various phenomena in the wafer bonding, such as self-activated bonding, asperity shape effect and plastic deformation effect in the bonding process.

Conductivity Enhancement in Thin Silicon-on-Insulator Layer Embedding Artificial Dislocation Network

AbstractA nanometer-scale dislocation network is artificially formed in thin top Si layer of silicon-on-insulator (SOI) structure, and effect of the dislocation network on the transport property is examined from the viewpoint of nanodevice applications. The artificial network of screw dislocations was formed in the Si layer using a wafer bonding of a pair of (001) SOI wafers with a slight misalignment of the in-plane crystalline directions to cause a lattice mismatch. The transmission electron microscopy clearly revealed the formation of dislocation network at the bonding interface with the period less than ∼20 nm. The dislocation network was found to enhance the conductivity in the Si bicrystal layer more than one order of magnitude in comparison with that in the monocrystal layer free from the dislocations. The enhanced conductivity is probably derived from an increased concentration of electrons around the dislocations due to the formation of donor-like gap states.

In situ measurement of wafer temperatures in a low pressure chemical vapor deposition furnace

Axial and radial temperature profiles within the wafer load of a multiwafer LPCVD furnace were measured in situ using a pair of instrumented wafers. The measurements confirm that the wafer load is not in thermal equilibrium with the furnace tube, as has been widely assumed in many modeling studies. The measurements confirm temperature variations predicted previously from a study of polysilicon film thickness profiles. Temperature variations were small for wafers near the center of the 150-wafer load. However, axial variations of up to 25 degrees C and radial variations of up to 5 degrees C were measured at the extremes of the wafer load. For a representative polysilicon deposition data set, axial and radial thin-film thickness variations were found to correlate closely with measured temperature variations. The temperature profile was found to be insensitive to gas composition and flowrate, establishing radiation as the dominant mode of heat transfer. A pair of polysilicon coated quartz radiation shields was shown to improve polysilicon film thickness uniformity both down the load (along the furnace axis) and across each wafer.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Pulse-Field-Assisted Wafer Bonding for Silicon on Insulator

We have developed a pulse-field-assisted bonding technique to give void-free, low-temperature wafer bonding for SOI (silicon on insulator). We bonded a pair of oxided wafers by applying pulses of a few hundred volts across the wafers at 800°C in a 0.1 Pa nitrogen ambient. To reduce the volatile materials on the surfaces of wafers, which cause voids at low temperature, we heated the wafers at reduced pressure. The impulsive electrostatic force deforms the insulating oxide and allows bonding despite surface roughness and wafer warpage. Our pulse-field-assisted bonding reduces both the bonding temperature and time. We obtained a bond strength of over 1700 kgf/cm2 after thermal treatment at 800°C for 1 min. This paper also discusses surface roughness, voids, and bond strength.

Platinum silicide fusion bonding

Silicide direct bonding has been accomplished between silicon PtSi coated wafers and both PtSi coated and uncoated silicon wafers. Successful bonding occurred when the PtSi surface was rendered hydrophilic by a hot aqua regia selective etching and cleaning process. The PtSi provides bondable, relatively low resistance paths which provide electrical interconnections between circuit elements on the bonded pair of wafers.

Applications of the silicon wafer direct-bonding technique to electron devices

A silicon wafer direct-bonding (SDB) technique has been developed. A pair of bare silicon wafers, as well as an oxidized wafer pair, are bonded throughout the wafer surfaces without any bonding material. Conventional semiconductor device processes can be used for the bonded wafers, since the bonded interface is stable thermally, chemically, mechanically and electrically. Therefore, the SDB technique is very attractive, and has been applied to several kinds of electron devices. Bare silicon to bare silicon bonding is an alternative for epitaxial growth. A thick, high quality and high resistivity layer on a low resistivity substrate was obtained without autodoping. 1800 V insulated gate bipolar transistors were developed using these SDB wafers. No electrical resistance was observed at the bonded bare silicon interfaces. If oxidized wafers are bonded, the two wafers are electrically isolated, providing silicon on insulator (SOI) wafers. Dielectrically isolated photodiode arrays were fabricated on the SOI wafers and 500 V power IC's are now being developed.

Bonding of silicon wafers for silicon-on-insulator

Several aspects of a new silicon-on-insulator technique utilizing bonding of oxidized silicon wafers were investigated. The bonding was achieved by heating in an inert atmosphere a pair of wafers with hydrophilic surfaces contacted face-to-face. A quantitative method for the evaluation of the surface energy of the bond based on crack propagation theory was developed. The bond strength was found to increase with the bonding temperature from about 60–85 erg/cm2 at room temperature to ≂2200 erg/cm2 at 1400 °C. The strength was essentially independent of the bond time. Bonds created during 10-s annealing at 800 °C were mechanically strong enough to withstand the mechanical and/or chemical thinning of the top wafer to the desired thickness and subsequent device processing. A model was proposed to explain three distinct phases of bonding in the temperature domain. Electrical properties of the bond were tested using metal-oxide-semiconductor (MOS) capacitors. The results were consistent with a negative charge density at the bond interface of approximately 1011 cm−2. A double-etch-back procedure was used to thin the device wafer to the desired thickness with ±20 nm thickness uniformity across a 4-in. wafer. The density of threading dislocations in the remaining silicon layer was 102 –103 cm−2, and the residual dopant concentration less than 5×1015 cm−3, both remnants of the etchstop layer. Complimentary metal-oxide-semiconductor (CMOS) devices made in the 20–100 nm silicon thick layers had subthreshold slopes of 68 mV/decade (both n- and p-channel MOS transistors). The effective carrier lifetime was 15–20 μs in 80- and 300-nm-thick Si films and the interface state density at the Si film-buried oxide interface was ≤5×1010 cm−2.

Pulse-field-assisted bonding for SOI devices

A technique for obtaining bulk-quality silicon layers on silicon dioxide by pulse-field assisted bonding of oxidized silicon wafers has been developed. Radiation-hardened 64 K silicon-on-insulator (SOI) DRAMs (dynamic random-access memories) were fabricated for the first time to the authors' knowledge by a conventional bulk DRAM process. Void-free bonding is done by pressing the oxidized surfaces of two wafers together and applying an impulsive electrostatic force. The oxide thickness ranges from 0.05 to 4.0 mu m. The pair of wafers is then placed on a SiC-coated carbon strip heater and heated to 800 degrees C in a 0.1-Pa nitrogen atmosphere. A silicon strip electrode is placed on one wafer to make an electrical contact with the other. A bonding-pulse amplitude of 100 to 500 V is applied between the electrode and the lower heater. Voids are eliminated when the pulse is applied. Bonded wafers are then annealed and thinned by polishing and/or chemical etching to the desired thickness. The characteristics of the MOSFETs and DRAMs obtained by this method are briefly described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>