Page Mapping Research Articles

AVX-TSCHA: Leaking information through AVX extensions in commercial processors

Modern x86 processors support an AVX instruction set to boost performance. However, this extension set may also cause security issues. We discovered that there are vulnerable properties in the implementation of the masked load/store instructions. First, these instructions can suppress exceptions caused by invalid or inaccessible memory access. Second, the execution time of these instructions leaks the current state of the page mappings, permissions, and TLB states.Based on this, we present a novel AVX timing side-channel attack that can defeat address space layout randomization. We demonstrate the significance of our side-channel attack by showing User and Kernel ASLR breaks on the recent Intel and AMD processors in various environments, including cloud computing systems (Amazon AWS, Google GCP, and Microsoft Azure), an SGX enclave (a fine-grained ASLR break), and major OSes (Linux, Windows, and macOS). Our attack can identify the Linux kernel's base address in 0.29 ms as well as those of loaded kernel modules in 2.24 ms, with a near-zero error rate. We further demonstrate that our attack can be used to infer user behavior, such as mouse movements and data transmissions over the network. Our evaluation results on multiple mobile, desktop, and server processors (a total of 26 Intel and AMD CPUs) show that 1) the AVX timing side-channel works on the vast majority of Intel processors (from the Sandy Bridge microarchitecture) as well as AMD processors (from the Zen microarchitecture onward) and 2) our KASLR breaks are very fast and reliable. To the best of our knowledge, our attack is the first to demonstrate a KASLR break on both the recent Intel Alder Lake and AMD Zen 3 CPUs. We highlight that more robust isolation or fine-grained randomization should be adopted to mitigate our presented attacks successfully.

Taming Process Variations in CNFET for Efficient Last-Level Cache Design

Carbon nanotube field-effect transistors (CNFET) emerge as a promising alternative to CMOS transistors for the much higher speed and energy efficiency, which makes the technology particularly suitable for building the energy-hungry last level cache (LLC). However, the process variations (PVs) in CNFET caused by the imperfect fabrication lead to large timing variation and the worst-case timing dramatically limits the LLC operation speed. Particularly, we observe that the CNFET-based cache latency distribution is closely related to the LLC layouts. For the two typical LLC layouts that have the CNT growth direction aligned to the cache way direction and cache set direction respectively, we proposed variation-aware set aligned (VASA) cache and variation-aware way aligned (VAWA) cache in combination with corresponding cache optimizations such as data shuffling and page mapping to enable low-latency cache for frequently used data. According to our experiments, the optimized LLC reduces the average access latency by 32% and 45% compared to the baseline designs on the two different CNFET layouts respectively while it improves the overall performance by 6\% and 9\% and reduces the energy consumption by 4% and 8% respectively. In addition, with both the architecture induced latency variation and PV incurred latency variation considered in a unified model, we extended the VAWA and VASA cache design for the CNFET-based NUCA and the proposed NUCA achieves both significant performance improvement and energy saving compared to the straightforward variation-aware NUCA.

Performance and Area Trade-Off of 3D-Stacked DRAM Based Chip Multiprocessor with Hybrid Interconnect

Nowadays, the number of cores on a chip multiprocessor is growing to increase system performance. However, inadequate on-chip interconnection and memory bandwidth have diminished the potential of these chip multiprocessors. High performance interconnects, 3D-stacked main memory, and large on-chip caches are the architectural parameters used to tackle this issue. For a fixed die size, high performance interconnects, and the 3D-stacked memory fosters the increasing rate of the number of cores on a chip multiprocessor whereas increasing the size of on-chip cache poses a restriction. In this work, we study the trade-off between the performance and overall chip area (evaluated using the number of cores, their types and cache size per core) of the chip multiprocessor for different combinations of the interconnection network, DRAM memory (off-chip or on-chip) and self-adaptive page mapping. Our experiments show that for the base-case (chip multiprocessor with the off-chip DRAM and without hybrid interconnect) architecture and without page mapping technique, to increase the core count for a fixed die size, merely shrinking the cache size degrades the performance. Whereas, reducing the cache size and increasing the chip multiprocessor core count along with our considered target architecture and page mapping technique scale up the performance.

Secured Storage Path Using Cryptographic Virtual Mapping for Cloud Applications

Cloud computing can be seen as a working model in an environment that provides cloud users with access to virtualized and configurable computing resources, which can be easily specified as a shared pool of services from the cloud service provider's paid to use applications. The cloud storage path service has gained greater appeal due to the amazing growth of digital data. Cloud users can be relieved from the local data storage path and maintenance burden using cloud storage path services. It has difficulty maintaining the secure storage path because of many security challenges of that system like the disruption of services, loss of privacy, etc., on the cloud's data storage path in the previous system. To overcome this drawback, this disclosure provides the proposed Cryptographic Virtual Mapping(CVM) system readable data for secure storage page mapping in a virtual mapping environment in cloud computing. Asymmetric Key Encryption Algorithm can be used for the encryption of massive data. This encryption process is less computationally expensive and consumes minimum time for performing the encryption and decryption of the cloud storage data. This method determines the propagation of data verification based cryptographic input data to decide the input key. The address is under a suspected control of a user of interest. The secure storage for dynamically changing data stored in the cloud is achieved using a well-known data structure called a linked list. This linked list is generated and maintained by the data owner. Using this solution, operations such as inserting, modifying, appending and deleting dynamic data are possible without downloading the entire data from the cloud server. The experimental results prove that the Cryptographic Virtual Mapping method has the highest probability of detecting damage or deformation of dynamically changing data.

Run-time adaptive data page mapping: A Comparison with 3D-stacked DRAM cache

In the current chip-multiprocessor era, 3D-stacked DRAM became an attractive alternative to mitigate the DRAM bandwidth wall problem. In a chip-multiprocessor, the 3D-stacked DRAM is architect either (a) to cache both local and remote data or (b) to cache only the local data. Caching only local data into the 3D-stacked DRAM enforces the chip-multiprocessors to suffer inter-node latency overhead while accessing remote data. However, caching both local and remote data onto the 3D-stacked DRAM requires a large coherence directory (tens of MBs) to ensure correctness. In this paper, we consider a 3D-stacked DRAM based chip-multiprocessor and perform a comparative study between (a) high level adaptive run-time data page mapping onto DRAM with an auxiliary small SRAM buffer as a performance booster, and (b) DRAM used as coherent cache. Our experiment on a 64 core chip-multiprocessor system with 4GB of 3D-stacked DRAM shows that our adaptive run-time data page mapping on DRAM along with an SRAM buffer outperforms the base-case (where DRAM caches only local data) by an average of 48%. Moreover, our method shows a performance improvement by an average of 40% when compared with a recent state-of-art work (where DRAM caches both local and remote data).

Cover Page Map: Inoh's Small-scale Map from the Collection of the Tokyo National Museum

Cover Page Map: Inoh's Small-scale Map from the Collection of the Tokyo National Museum

Facebook pages of Latvian news portals: functionality utilization efficiency

Facebook has long considered media as partners, and therefore creates various tools to work with their audience. In turn, media companies and content providers use Facebook not only to increase traffic, but also to better understand their users. This study compares web pages of the three leading Latvian news portals (Delfi.lv, Apollo.lv and TVNET.lv) in order to study the effectiveness of using all the features provided by functionality of a social network. Applying conversionary analysis to build a typical communicative model and taking into consideration characteristic features of social network, it is established that the type of content significantly affects the user’s actions. It is revealed that the functionality of social network has characteristic features, among which is communication and entertainment component, as well as socialization and self-presentation. In order to obtain quantitative indicators necessary for modeling, we have used web service of content analytics of social networks: ER, LR, TR metrics are used to analyze dive depth, visit frequency and Facebook page mapping. The obtained results indicate a low level of user behavior on the pages of the examined portals in Facebook. The uniform distribution of attention of visitors between photos, text and hyperlinks does not allow to identify priority formats. It has been established that Facebook pages of online news resources are likely to be non-priority media activity, the task of which is to ensure the presence of resources in the system of social media and increase intensity of information exchange. The study shows that there is no systematic work on integrated representation of Latvian news portals Delfi, TVNet and Apollo on Facebook. Editorial offices do not adapt publications to the specifics of the social network without formatting content, but mainly promote links that lead to the official media portal. The general lack of hashtags system indicates minimal optimization of editorial content for the social network Facebook.

Reinforcement learning-driven address mapping and caching for flash-based remote sensing image processing

Abstract Flash memory is featured with salient advantages over conventional hard disks for massive data storage and efficient on-board data processing. A flash translation layer (FTL) is a critical component for flash-based storage devices to handle particular technical constraints of flash. It is desirable to use flash memory for the storage of massive remote sensing images and support on-board remote sensing data processing applications, which typically require high I/O performance and hence call for advanced FTL design and implementations. In this paper, we introduce our efforts in developing a reinforcement learning driven page-level mapping and caching scheme (named Q-FTL) that is adaptive and responsive to ever-changing I/O streams of on-board remote sensing image processing operations. The adaptability and responsiveness are achieved by the separation of large and small I/O requests, an integrated weighting scheme to measure access costs of cached translation pages, and a reinforcement learning driven cache replacement algorithm. We demonstrate the efficiency of the proposed approach using actual I/O traces generated from on-board remote sensing image processing applications. Experimental results show that Q-FTL improves over several current state-of-the-art FTLs by a large margin and even achieves competitive performance close to an idealized pure page mapping FTL in some cases.

Lifetime-aware FTL to improve the lifetime and performance of solid-state drives

Data compression techniques have been deployed in SSDs to prolong their lifetime due to the good tradeoff between data reduction and performance degradation. However, existing schemes either consume plenty of DRAM resources, or cause the read amplification problem, which may further result in significant performance degradation. In this paper, we propose a lifetime-aware FTL scheme (LAFTL) to improve both the lifetime and performance of SSDs by compressing several pages into one physical page. We then design a compression-aware page mapping table (PMT) to reduce the memory consumption, and propose a latency-aware approach to improve the performance. We conduct extensive trace-driven evaluations based on real-world workloads, and results show that our LAFTL reduces the average response time of reads by 3%–78% and ensures a minimal resource consumption in DRAM while obtaining an acceptable data reduction rate compared to other schemes.

CODA

To exploit parallelism and scalability of multiple GPUs in a system, it is critical to place compute and data together. However, two key techniques that have been used to hide memory latency and improve thread-level parallelism (TLP), memory interleaving, and thread block scheduling, in traditional GPU systems are at odds with efficient use of multiple GPUs. Distributing data across multiple GPUs to improve overall memory bandwidth utilization incurs high remote traffic when the data and compute are misaligned. Nondeterministic thread block scheduling to improve compute resource utilization impedes co-placement of compute and data. Our goal in this work is to enable co-placement of compute and data in the presence of fine-grained interleaved memory with a low-cost approach. To this end, we propose a mechanism that identifies exclusively accessed data and place the data along with the thread block that accesses it in the same GPU. The key ideas are (1) the amount of data exclusively used by a thread block can be estimated, and that exclusive data (of any size) can be localized to one GPU with coarse-grained interleaved pages; (2) using the affinity-based thread block scheduling policy, we can co-place compute and data together; and (3) by using dual address mode with lightweight changes to virtual to physical page mappings, we can selectively choose different interleaved memory pages for each data structure. Our evaluations across a wide range of workloads show that the proposed mechanism improves performance by 31% and reduces 38% remote traffic over a baseline system.

OrcFS

In this work, we develop the Orchestrated File System (OrcFS) for Flash storage. OrcFS vertically integrates the log-structured file system and the Flash-based storage device to eliminate the redundancies across the layers. A few modern file systems adopt sophisticated append-only data structures in an effort to optimize the behavior of the file system with respect to the append-only nature of the Flash memory. While the benefit of adopting an append-only data structure seems fairly promising, it makes the stack of software layers full of unnecessary redundancies, leaving substantial room for improvement. The redundancies include (i) redundant levels of indirection (address translation), (ii) duplicate efforts to reclaim the invalid blocks (i.e., segment cleaning in the file system and garbage collection in the storage device), and (iii) excessive over-provisioning (i.e., separate over-provisioning areas in each layer). OrcFS eliminates these redundancies via distributing the address translation, segment cleaning (or garbage collection), bad block management, and wear-leveling across the layers. Existing solutions suffer from high segment cleaning overhead and cause significant write amplification due to mismatch between the file system block size and the Flash page size. To optimize the I/O stack while avoiding these problems, OrcFS adopts three key technical elements. First, OrcFS uses disaggregate mapping , whereby it partitions the Flash storage into two areas, managed by a file system and Flash storage, respectively, with different granularity. In OrcFS, the metadata area and data area are maintained by 4Kbyte page granularity and 256Mbyte superblock granularity. The superblock-based storage management aligns the file system section size, which is a unit of segment cleaning, with the superblock size of the underlying Flash storage. It can fully exploit the internal parallelism of the underlying Flash storage, exploiting the sequential workload characteristics of the log-structured file system. Second, OrcFS adopts quasi-preemptive segment cleaning to prohibit the foreground I/O operation from being interfered with by segment cleaning. The latency to reclaim the free space can be prohibitive in OrcFS due to its large file system section size, 256Mbyte. OrcFS effectively addresses this issue via adopting a polling-based segment cleaning scheme. Third, the OrcFS introduces block patching to avoid unnecessary write amplification in the partial page program. OrcFS is the enhancement of the F2FS file system. We develop a prototype OrcFS based on F2FS and server class SSD with modified firmware (Samsung 843TN). OrcFS reduces the device mapping table requirement to 1/465 and 1/4 compared with the page mapping and the smallest mapping scheme known to the public, respectively. Via eliminating the redundancy in the segment cleaning and garbage collection, the OrcFS reduces 1/3 of the write volume under heavy random write workload. OrcFS achieves 56% performance gain against EXT4 in varmail workload.

Coordinate Channel-Aware Page Mapping Policy and Memory Scheduling for Reducing Memory Interference Among Multimedia Applications

In a modern multicore system, memory is shared among more and more concurrently running multimedia applications. Therefore, memory contention and interference are more and more serious, inducing system performance degradation significantly, the performance degradation of each thread differently, unfairness in resource sharing, and priority inversion, even starvation. In this paper, we propose an approach of coordinating channel-aware page mapping policy and memory scheduling (CCPS) to reduce intermultimedia application interference in a memory system. The idea is to map the data of different threads to different channels, together with memory scheduling. The key principles of the policies of page mapping and memory scheduling are: 1) the memory address space, the thread priority, and the load balance; and 2) prioritizing a low-memory request thread, a row-buffer hit access, and an older request. We evaluate the CCPS on a variety of mixed single-thread and multithread benchmarks and system configurations, and we compare them with four previously proposed state-of-the-art interference-reducing policies. Experimental results demonstrate that the CCPS improves the performance while reducing the energy consumption significantly; moreover, the CCPS incurs a much lower hardware overhead than the current existing policies.

Efficient Checkpointing of Live Virtual Machines

The ability to save the state of a running virtual machine (VM) for later restoration is an important tool for home, server, and virtual desktop cloud (VDC) environments in order to achieve optimal and balanced hardware utilization. With guest memory sizes of four to eight gigabytes being the norm the time- and space-overhead of storing VM checkpoints still prevents an effective use of the technique. This work presents a method for fast and space-efficient checkpointing of VMs. Based on the observation that operating systems cache disk blocks in memory, the proposed technique transparently intercepts I/O operations and maintains an up-to-date mapping of memory pages and disk blocks containing identical data. At a checkpoint, those memory pages are excluded from the checkpoint image leading to a significant reduction of both the time and space required to take a checkpoint of a running VM. The broad applicability and good performance of the proposed method is demonstrated by an extensive set of experiments. We have implemented the technique for para-virtualized (PV), PVHVM, and fully-virtualized (HVM) guests in the Xen hypervisor. In comparison with an unmodified Xen hypervisor, experiments with Linux and Windows guests, on average, achieve a 86, 76, 53, and 47 percent reduction in the stored data and a 73, 62, 47, and 38 percent shorter time required to take a checkpoint for PV, PVHVM, HVM Linux, and HVM Windows guests, respectively.

Wear-Leveling Aware Page Management for Non-Volatile Main Memory on Embedded Systems

Non-volatile Memories (NVMs), have many promising characteristics, such as low leakage power, low cost, non-volatility, and high scalability, which are all attractive for embedded systems to employ them as the main memory. However, one of the constraints that undermine the credential of NVMs as main memory is its limited write endurance. To tackle this problem, this paper proposes five techniques: Rearrangement Inequality Based Page Allocation (RIPA), Virtual Page Mapping (VPM), On-demand Memory Merging and Splitting (OMS), Periodical Page Swapping (PPS), and Normalized Boundary Calibration (NBC) to evenly distribute the writes on Non-volatile Main Memory (NVMM) purely on the Operating System (OS) level, which can greatly extend lifetime of NVMM. Without extra hardware support, OS management is easy to be integrated into existing embedded systems. The experimental results show that with less then $0.6$ percent performance overhead the proposed techniques can extend the lifetime of NVMM to $17.28$ times longer compared with traditional methods.

Algorithms for Warping of 2-D PAGE Maps.

Software-based image analysis of 2-D PAGE maps is an important step for the investigation of proteome. Warping algorithms, which are employed to register spots among gels, are able to overcome the difficulties due to the low reproducibility of this analytical technique. Over the years, the research of new matching and warping mathematical methods has allowed the development of several routine applications of easy-to-use software. This chapter describes common and basic spatial transformations used for the alignment of protein spots present in different gel maps; some recently new approaches are also presented.

The Use of Legendre and Zernike Moment Functions for the Comparison of 2-D PAGE Maps.

The comparison of 2-D maps is not trivial, the main difficulties being the high complexity of the sample and the large experimental variability characterizing 2-D gel electrophoresis. The comparison of maps from control and treated samples is usually performed by specific software, providing the so-called spot volume dataset where each spot of a specific map is matched to its analogous in other maps, and they are described by their optical density, which is supposed to be related to the underlying protein amount. Here, a different approach is presented, based on the direct comparison of 2-D map images: each map is decomposed in terms of moment functions, successively applying the multivariate tools usually adopted in image analysis problems. The moments calculated are then treated with multivariate classification techniques. Here, two types of moment functions are presented (Legendre and Zernike moments), while linear discriminant analysis and partial least squares discriminant analysis are exploited as classification tools to provide the classification of the samples. The procedure is applied to a sample dataset to prove its effectiveness.

Decoding 2-D Maps by Autocovariance Function.

This chapter describes a mathematical approach based on the study of the 2-D autocovariance function (2-D ACVF) useful for decoding the complex signals resulting from the separation of protein mixtures. The method allows to obtain fundamental analytical information hidden in 2-D PAGE maps by spot overlapping, such as the number of proteins present in the sample and the mean standard deviation of the spots, describing the separation performance. In addition, it is possible to identify ordered patterns potentially present in spot positions, which can be related to the chemical composition of the protein mixture, such as post-translational modifications.The procedure was validated on computer-simulated maps and successfully applied to reference maps obtained from literature sources.

NAND 플래시 메모리 기반 B+ 트리에서 페이지 매핑 로그를 이용한 색인 관리 기법

NAND flash memory has being used for storage systems widely, because it has good features which are low-price, low-power and fast access speed. However, NAND flash memory has an in-place update problem, and therefore it needs FTL(flash translation layer) to run for applications based on hard disk storage. The FTL includes complex functions, such as address mapping, garbage collection, wear leveling and so on. Futhermore, implementation of the FTL on low-power embedded systems is difficult due to its memory requirements and operation overhead. Accordingly, many index data structures for NAND flash memory have being studied for the embedded systems. Overall performances of the index data structures are enhanced by a decreasing of page write counts, whereas it has increased page read counts, as a side effect. Therefore, we propose an index management method using a page mapping log table in -Tree based on NAND flash memory to decrease page write counts and not to increase page read counts. The page mapping log table registers page address information of changed index node and then it is exploited when retrieving records. In our experiment, the proposed method reduces the page read counts about 61% at maximum and the page write counts about 31% at maximum, compared to the related studies of index data structures.

MOSKG: countering kernel rootkits with a secure paging mechanism

AbstractThe kernel‐level rootkits compromise the security of operating systems. In the current research studies, virtualization is used as a key tool against these attacks with virtualization‐based memory protection. There are glitches in the memory protection mechanism, and it is vulnerable to page mapping attack and hard to be used for protecting dynamic data. To address these problems, we proposed a secure paging mechanism and constructed an external and transparent architecture named multiple operating systems kernel guard (MOSKG), which can protect critical kernel data in different operating systems like Windows and Linux, both of 32‐bit and 64‐bit. To evaluate our proposed architecture, we applied some experiments that are based on the study of kernel rootkits. The results show that MOSKG can protect critical kernel data from dynamic kernel object manipulation and page mapping attack, and it defeats all of the kernel‐level attacks. It is also a significant conclusion that MOSKG only introduces a small performance overhead of 2.3%. Copyright © 2015 John Wiley & Sons, Ltd.

Design Tradeoffs of SSDs

In this work, we studied the energy consumption characteristics of various SSD design parameters. We developed an accurate energy consumption model for SSDs that computes aggregate, as well as component-specific, energy consumption of SSDs in sub-msec time scale. In our study, we used five different FTLs (page mapping, DFTL, block mapping, and two different hybrid mappings) and four different channel configurations (two, four, eight, and 16 channels) under seven different workloads (from large-scale enterprise systems to small-scale desktop applications) in a combinatorial manner. For each combination of the aforementioned parameters, we examined the energy consumption for individual hardware components of an SSD (microcontroller, DRAM, NAND flash, and host interface). The following are some of our findings. First, DFTL is the most energy-efficient address-mapping scheme among the five FTLs we tested due to its good write amplification and small DRAM footprint. Second, a significant fraction of energy is being consumed by idle flash chips waiting for the completion of NAND operations in the other channels. FTL should be designed to fully exploit the internal parallelism so that energy consumption by idle chips is minimized. Third, as a means to increase the internal parallelism, increasing way parallelism (the number of flash chips in a channel) is more effective than increasing channel parallelism in terms of peak energy consumption, performance, and hardware complexity. Fourth, in designing high-performance and energy-efficient SSDs, channel switching delay, way switching delay, and page write latency need to be incorporated in an integrated manner to determine the optimal configuration of internal parallelism.