Technologies in semiconductor industry have been developed into a three-dimensional multilayer wiring for high integration of devices. Chemical mechanical planarization (CMP) process is one of the key technologies for achieving multilayer wiring, which enables global planarization. In addition, highly integrated devices can be realized by increasing the depth of focus in the photolithography process. However, in the inter-layer dielectric (ILD) CMP of the transistor, the uppermost oxide layer has the step due to the arrangement of the devices. The ideal material removal mechanism is to gradually remove materials from the top of the step height which allows for global planarization. However, in the CMP of the patterned wafers, simultaneous polishing of the upper and lower layers occurs when the step height reaches a certain height. This means that the polishing is strongly dependent on the structural characteristics of the pattern. Especially, the difference in the material removal rate depending on the pattern density acts as a constraint in terms of device layout. Therefore, it is essential to develop an accurate prediction model of material removal rate as a function of pattern density, size and arrangement. This study aims to define the mathematical planarization model according to contact mode between a polishing pad and patterned wafer. Considering that the real contact area between the actual polishing pad and the wafer is about 1 %, the mathematical model is derived based on the microscopic deformation of the pad asperities, not the macroscopic deformation of the bulk pad. Finally, we describe the verification between the theoretical material removal rate model and step height reduction and the actual CMP results. The root mean square error of the upper layer material rate, the lower material removal rate, and the step height reduction were 24.59 nm/min, 22.03 nm/min and 22.6 nm, respectively. Compared with the previous studies, the new model of this study improved the error by up to 50.9 %.