Packet-switched Interconnection Research Articles

The RapidIO Routing Strategy Based on the Double-Antibody Group Multi-Objective Artificial Immunity Algorithm.

The RapidIO standard is a packet-switching interconnection technology similar to the Internet Protocol (IP) conceptually. It realizes the high-speed transmission of RapidIO packets at the transport layer, but this greatly increases the probability of network blocking. Therefore, it is of great significance to optimize the RapidIO routing strategy. For this problem, this paper proposes a Double-Antibody Group Multi-Objective Artificial Immune Algorithm (DAG-MOAIA), which improves the local search and global search ability of the population by adaptive crossover and adaptive mutation of the double-antibody groups, and uses co-competition of multi-antibody groups to increase the diversity of population. Through DAG-MOAIA, an optimal transmission path from the source node to multiple destination nodes can be selected to solve the Quality Of Service (QoS) problem during data transmission and ensure the QoS of the RapidIO network. Simulation results show that DAG-MOAIA could obtain high-quality solutions to select better routing transmission paths, and exhibit better comprehensive performance in all simulated test networks, which plays a certain role in solving the problem of the RapidIO routing strategy.

Power-aware high level evaluation model of interconnect length of on-chip memory network topology

Interconnect power is the factor that dominates the power consumption on the on-chip memory architecture. Almost all dedicated wires and buses are replaced with packet switching interconnection networks which have become the standard approach to on-chip interconnection. Unfortunately, rapid advances in technology are making it more difficult to assess the interconnect power consumption of NoC. To resolve this problem, a new evaluating methodology for interconnect power evaluation based on topology of on-chip memory (IP-ETOM) is proposed in this paper. To validate this method, two multicore architectures 2D-mesh and triplet-based architecture (TriBA) are evaluated in this research work. The on-chip memory network model is evaluated based on characteristics of on-chip architecture interconnection. MATLAB is used for conducting the experiment that evaluates the interconnection power of TriBA and 2D-mesh.

A Gigabit Fiber Optical Bus Based on the RapidIO Technology

The RapidIO architecture is an interconnect technology based on a high-performance and packet-switched interconnect technology. The paper uses the RapidIO Interconnect technology to design a fiber optic bus. The fiber optic bus provides a tightly coupled interconnect with Gigabit speed, which can improve the processing capability of the space distributed system, such as the weapons platform with high-speed and high-capacity multi-system.

All-optical packet-switched interconnection network based on modular photonic digital processing

Future interconnection networks will be required to achieve ultra-high bandwidth and low latency communications to cope with the increasing performance requirements of backbone routers, large data storage systems and supercomputing systems. Aiming at achieving ultra-high bandwidth communications and approaching optical time-of-flight processing latency while being robust to cascade impairments, the authors propose an all-optical packet-switched interconnection network, where not only the actual packet switching but also the packet processing is performed in the photonic domain. The authors present two modular architectures, based on the crossbar and the Batcher–Banyan topologies, capable of forwarding fixed-length packets with two classes of service. Both use photonic digital-processing subsystems built by combining a single integrable module which exploits cross gain modulation in a semiconductor optical amplifier. System level simulations on the crossbar switch controller guarantee that the control signals maintain an acceptable quality during the processing. Moreover, the Batcher–Banyan configuration is more cost-effective than the crossbar for increasing port count, while effective network performance in terms of packet loss rate can be obtained by adding just few recirculating delay lines.

Rotary router

The trend towards increasing the number of processor cores and cache capacity in future Chip-Multiprocessors (CMPs), will require scalable packet-switched interconnection networks adapted to the restrictions imposed by the CMP environment. This paper presents an innovative router design, which successfully addresses CMP cost/performance constraints. The router structure is based on two independent rings, which force packets to circulate either clockwise or anti-clockwise, traveling through every port of the router. It uses a completely decentralized scheduling scheme, which allows the design to: (1) take advantage of wide links, (2) reduce Head of Line blocking, (3) use adaptive routing, (4) be topology agnostic, (5) scale with network degree, and (6) have reasonable power consumption and implementation cost. A thorough comparative performance analysis against competitive conventional routers shows an advantage for our proposal of up to 50 % in terms of raw performance and nearly 60 % in terms of energy-delay product.

Optical packet-switched interconnect based on wavelength-division- multiplexed clockwork routing

A crucial part of large-scale high-performance computing systems is the interconnection network. We describe an optical self-routing network based on a combination of 'clockwork' routing and wavelength division multiplexing to provide low latency and high bandwidth, with large scalability. The optical-layer architecture is described in detail, and results obtained from full numerical simulations of traffic performance demonstrate scalability to networks as large as 2048 nodes in a flat single-stage network architecture.

Bit-parallel message exchange and data recovery in optical packet switched interconnection networks

Multiwavelength optical messages encoded in a bit-parallel fashion are successfully routed through five switching nodes of a 12-port optical packet switching interconnection network. The data payloads are entirely recovered and processed at the destination node using an embedded clock signal with a measured clock-to-data skew tolerance window of 150 ps.

A fully implemented 12 /spl times/ 12 data vortex optical packet switching interconnection network

A fully functional optical packet switching (OPS) interconnection network based on the data vortex architecture is presented. The photonic switching fabric uniquely capitalizes on the enormous bandwidth advantage of wavelength division multiplexing (WDM) wavelength parallelism while delivering minimal packet transit latency. Utilizing semiconductor optical amplifier (SOA)-based switching nodes and conventional fiber-optic technology, the 12-port system exhibits a capacity of nearly 1 Tb/s. Optical packets containing an eight-wavelength WDM payload with 10 Gb/s per wavelength are routed successfully to all 12 ports while maintaining a bit error rate (BER) of 10/sup -12/ or better. Median port-to-port latencies of 110 ns are achieved with a distributed deflection routing network that resolves packet contention on-the-fly without the use of optical buffers and maintains the entire payload path in the optical domain.

Design and operation of data switching circuits for a superconductive three-node parallel processor interconnection system

We have proposed a superconductive packet switching interconnection circuit for a three-node parallel processor system. At each node, the processor unit communicates with the others through a ring interface circuit (called RIF circuit). In this paper, we report the design of the switching protocols of the RIF circuit and the result of an operation experiment on each protocol. The protocols operate successfully at 20 kHz. Additionally, the functions of checking validity and setting validity of the packet operate successfully at over 1 GHz.

Prevention of congestion in packet-switched multistage interconnection networks

This paper proposes a simple, yet effective scheme to prevent congestion in a packet-switched multistage interconnection network (MIN) caused by hot spots. In this scheme, switches in the second and third stages of the MIN monitor their buffer occupancy to detect any notable nonuniform access behavior. When a switch detects congestion, packets generated by processors will be blocked from entering the congested switch until the congestion is cleared. Our scheme is compared with two well known schemes and shown to exhibit significantly better performance than these two. >

The design of the microarchitecture of UltraSPARC-I

The realization of a high performance modern microprocessor involves hundreds of person-years of conception, logic design, circuit design, layout drawing, etc. In order to leverage effectively the 5-10 millions of transistors available, careful microarchitecture tradeoff analysis must be performed. This paper describes not only the microarchitecture of UltraSPARC-I, a 167 MHz 64-b four-way superscalar processor, but more importantly it presents the analysis and tradeoffs that were made "en route" to the final chip. Among several issues, the in-order execution model is compared with alternatives, variations of the issue-width of the machine as well as the number of functional units are described, subtle features that are part of the memory hierarchy are explained, and the advantages of the packet-switched interconnect are exposed.

A contribution to the problem of avoiding congestion in multistage networks in the presence of unbalanced traffic

Multistage packet-switched interconnection networks (MINs) have been proposed for use in parallel processing systems and for implementation of fast packetswitch architecture designs. Performance of these networks has been known to severely degrade under unbalanced (nonuniform) traffic patterns. This article proposes various flow control procedures and corresponding logical implementations as possible solutions to the problem of performance degradation of such systems. Simulation results are presented to show the potential to improve MIN performance by introducing the proposed flow-control procedures.

Picosecond multistage interconnection network architecture for optical computing

We use nonlinear optical bistable devices to design a prototype of a building block for an all-optical multistage interconnection network architecture. This architecture is flexible in the sense that it can be used for either circuit-switched interconnection networks or packet-switched interconnection networks, depending on the user's applications and type of network architecture. Therefore this is a generalpurpose all-optical switch that is applicable to almost all types of network such as omega, banyan, perfect shuffle, etc. The system consists of several design units, each of which is described separately, and then all are synthesized together to form the complete system. When used with the packet-switched networks, the system is capable of buffering information optically with no need for electronic backup. The main functions of the architecture are achieved by the use of a nonlinear optical bistable device, namely, the interference filter (with the addition of mirrors and beam splitters). These optical c mponents are commercially available. They can also be integrated for future mass production. Therefore we anticipate that the implementation of this architecture is feasible.

Performance analysis of synchronous multibuffered packet-switching networks

In this paper, a general mathematical method for analysis of synchronous multibuffered packet-switching interconnection networks in multiprocessor systems is presented. The proposed mathematical method is general in that he analyzed synchronous interconnection networks under uniform and nonuniform traffic. The existing methods for analysis of buffered interconnection networks have assumed either single or infinite buffers at each output (or input) port of a switch, as well as uniform traffic pattern of the networks. Recently, H. Yoon et al. [1] have presented an analytical model of buffered delta networks, assuming finite buffers at each input port and uniform traffic. Firstly, in the paper, a general model of synchronous buffered switching element, using output buffering, under assumption of finite buffer size for a very general class of traffic, is presented. Traffic can be uniform or nonuniform. It is assumed that the subsequent stages of the network are nearly independent and a model is extended for entire network under this assumption. Analytical results obtained with proposed model are then compared with each other, and it is shown that the proposed mathematical method is more general then the known models of interconnection networks.

A program-driven simulation model of an MIMD multiprocessor

A simulation model that supports very accurate modeling of multiprocessors with a hierarchical, packet-switched interconnection network and private caches is explored. The simulation system contains workload simulators and a memory system simulator. The workload simulators are program-driven, i.e. they actually execute programs. The time unit of the simulator is the time between two consecutive memory references from the processors. The performance of the simulation model, although acceptable, could be improved using a trace-driven approach. The author shows that results obtained from trace-driven simulation methods in the course of multiprocessor performance evaluation are generally not valid. Furthermore, he shows that in the evaluation of certain processor architectural features, such as non-blocking architectures, the program-driven approach is necessary. >

Performance analysis of multibuffered packet-switching networks in multiprocessor systems

An analytic model and analytic results for the performance of multibuffered packet-switching interconnection networks in multiprocessor systems are presented. The performance of single-buffered delta networks is first modeled using the state transition diagram of a buffer. The model is then extended to account for multiple buffers. The analytic results for multibuffered delta networks are compared to simulation results. The performance of multibuffered data manipulator networks is analyzed to demonstrate the generality of the model.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Approximate analysis of single and multiple ring networks

Asynchronous packet-switched interconnection networks with decentralized control are very appropriate for multiprocessing and data-flow architectures. The authors present performance models of single- and multiple-ring networks based on token-ring, slotted-ring, and register-insertion-ring protocols. The multiple ring networks have the advantage of being reliable, expandable, and cost effective. An approximate and uniform analysis, based on the gate M/G/1 queuing model, has been developed to evaluate the performance of both existing single-ring networks and the proposed multiple-ring networks. Approximations are good for low and medium load. The analyses are based on symmetric ring structure with nonexhaustive service policy and infinite queue length at each station. They essentially involve modeling of queues with single- and multiple-walking servers. The results obtained from the analytical models are compared to those obtained from simulation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Performance evaluation of nonrectangular multistage interconnection networks

The performance is considered of unbuffered packet-switching nonrectangular multistage interconnection networks. Performance analysis is based on a simplified model for resolution of packet contention. An approximate closed-form analytical expression for the probability of packet acceptance is derived. Blocking characteristics of nonrectangular networks are analyzed and it is shown that for large nonrectangular networks, the probability of packet acceptance does not degrade with growth of network size. >

The importance of being square

We present a theory that defines performance of packet-switching interconnection networks (delay and capacity) and their cost in terms of their geometry. This is used to prove that square banyan networks have optimal performance/cost ratio. These results, together with some known results on the complexity of routing in multistage networks, show that multistage shuffle-exchange networks are the unique networks with both optimal performance and simple routing. Finally, square delta networks are shown to have optimal area complexity.