Package Substrate Research Articles

Hybrid package integration strategy for silicon ICs operating beyond 200 GHz

Abstract This paper proposes an innovative hybrid package integration strategy compatible with silicon-based technologies. It is evaluated beyond 200 GHz by the integration of a WR3 back-to-back waveguide-to-suspended stripline transition designed in BiCMOS technology, relying on metallic split-block package and organic laminate substrate. Simulated insertion loss below 3 dB is observed in the 220–320 GHz frequency band, competing with reported traditional solutions using III–V substrates. The achieved performances lead to promising perspectives for low-cost silicon packaging solutions beyond 200 GHz.

Sputtering of (111) highly-oriented nanotwinned Ag on polycrystalline Si3N4 substrates for high-power electronic packaging

Nanotwinned silver (NT-Ag) exhibits excellent mechanical and electrical properties, attributed to its high-density and (111) highly-oriented twinning structure in nanoscale. Therefore, it has recently drawn much attention in the field of electronic packaging, where it can be utilized as interconnection or metallization materials. However, it has been a critical challenge to fabricate the high-density and highly-oriented NT-Ag onto polycrystalline ceramic substrates, whose crystal structure does not support the epitaxial growth of NT-Ag films. In the current work, a high-density and highly-oriented NT-Ag film has been fabricated onto a polycrystalline ceramic substrate, i.e., NT-Ag on silicon nitride (NT-Ag@Si3N4), using the magnetron sputtering method. As results, a close-packed arrangement of high-density NT-Ag has been observed within columnar grains aligned along its growth direction, whereas the nanoindentation hardness of the NT-Ag film reached 1.82 GPa, with an electrical resistivity of 2.06 μΩ‧cm. Moreover, this study has discussed and explained the growth kinetics and mechanism of NT-Ag films, by controlling magnetron sputtering process parameters, such as sputtering power and argon flow rate. Additionally, the differences in the growth mechanism of NT-Ag on (100) Si and polycrystalline Si3N4 have also been investigated. With its superior material properties, NT-Ag@Si3N4 holds great promise in the applications of advanced packaging technology for high-power electronics.

Research on FBG curvature sensor based on PET substrate and silicone package

To address the low repeatability and accuracy in single package form and lack of strain transfer theory analysis in composite material form of fiber Bragg grating (FBG) curvature sensors, a flexible curvature sensing test scheme for FBG based on polyethylene terephthalate (PET) substrate and silicone package is proposed. Firstly, the factors affecting the strain response of the FBG are obtained through the analysis of the multilayer strain transfer theory, and the relationship between different material encapsulation forms and the strain response of the FBG is explored through finite element simulation. Secondly, the FBG curvature sensor with optimized simulation parameters is fabricated in package, and the curvature calibration verification experiments are performed on the sensor. Finally, the experimental results show that the deviation index of the FBG curvature sensor is between −1.89 % and 1.62 %, which indicates a better repeatability consistency. Based on the computation, the maximum sensitivity of the FBG curvature sensor is 13.32 µε/m−1 when the spacing between the fiber and the substrate layer is 2.50 mm, and its error is 0.30 % comparing with the simulation of the same condition, which supports the accuracy of the theoretical analysis and simulation of the multilayer strain transfer of the encapsulated FBG sensor conducted in this paper, meanwhile, the optimal encapsulation process of the FBG curvature sensor is obtained.

Rapid Construction of PVA@CDs/SiO2 Fluorescent/Structural Color Dual-Mode Anti-Counterfeiting Labels via Spray-Coating Method.

A method of sequential spraying of polyvinyl alcohol with carbon quantum dots (PVA@CDs) aqueous suspension and SiO2 aqueous suspension is proposed to rapidly prepare multicolor dual-mode anti-counterfeiting labels. With the optimization of the concentration (15%) of colloidal microspheres in the SiO2 aqueous suspension as well as the spraying process parameters (spray distance of 10 cm, spray duration of 3 s, and assembly temperature of 20 °C), different-sized SiO2 microspheres (168 nm, 228 nm, and 263 nm) were utilized to rapidly assemble red, green, and blue photonic crystals. Furthermore, the tunable fluorescence emission of carbon quantum dots endows the labels with yellow, green, and blue fluorescence. The constructed dual-mode labeling was used to develop an anti-counterfeiting code with dual-channel information storage capabilities and also to create dual-mode multicolor anti-counterfeiting labels on various packaging substrates. This work provides a novel solution for anti-counterfeiting packaging and information storage.

Toward flexible electronics: A novel polyurethane integrating self‐healing, UV‐protective, reprocessable, and degradable properties

AbstractFlexible electronics are striving in modern society, and they impose harsh and urgent requirements for flexibility on electronic package substrates. However, traditional materials, including ceramics, metals, or polymers are lack of flexibility. Herein, a polyurethane named PU‐D1Q1VF1 is proposed via incorporating carefully selected biobased units and synergistic dynamic bonds, and the PU‐D1Q1VF1 not only meets the basic requirements of flexibility but also possesses properties of self‐heal, UV‐protection, reprocessability, and degradability. The polycaprolactone diol (PCL diol) was employed as the soft segment, and the bis(2‐hydroxyethyl) disulfide (HEDS) and lignin derived model monomer hydroquinone were selected as chain extenders. Moreover, carefully synthesized bio‐based monomer (E)‐4‐(((furan‐2‐ylmethyl)imino)methyl)‐2‐methoxyphenol (VF) was used as the capping agent, which could facilitate the self‐healing process of the PU‐D1Q1VF1.

A universal packaging substrate for mechanically stable assembly of stretchable electronics

Stretchable electronics commonly assemble multiple material modules with varied bulk moduli and surface chemistry on one packaging substrate. Preventing the strain-induced delamination between the module and the substrate has been a critical challenge. Here we develop a packaging substrate that delivers mechanically stable module/substrate interfaces for a broad range of stiff and stretchable modules with varied surface chemistries. The key design of the substrate was to introduce module-specific stretchability and universal adhesiveness by regionally tuning the bulk molecular mobility and surface molecular polarity of a near-hermetic elastic polymer matrix. The packaging substrate can customize the deformation of different modules while avoiding delamination upon stretching up to 600%. Based on this substrate, we fabricated a fully stretchable bioelectronic device that can serve as a respiration sensor or an electric generator with an in vivo lifetime of 10 weeks. This substrate could be a versatile platform for device assembly.

Cold Gas Spraying Copper Metal On AlN Ceramics as an Alternative to Thick DBC Substrates for Power Electronics

Abstract This study investigates the use of cold gas spraying (CGS) as a low-temperature additive manufacturing method to bond copper onto aluminum nitride (AlN) substrates for electronic packaging of high-power applications. While direct bond copper (DBC) technique is commonly used, it has limitations due to the large mismatch in coefficient of thermal expansion, which affects substrate reliability. This work employed cold gas spraying (CGS) to mechanically bond Cu on AlN. The study explores the effect of multiple sprays, spray angle and spraying direction on deposition thickness, coating surface roughness, and deposited volume through a factorial design of experiments (DOE). The results, based on optical and scanning electron microscopy combined with profilometry data, showed that coatings sprayed at a 60° angle had a smoother profile topography and less surface roughness than those sprayed at a 90° angle. After depositing 10 layers, a surface roughness (Sa) of around 30 µm and a coating thickness of over 300 µm were successfully attained. These findings provide valuable insights into the processing factors affecting the growth and quality of copper coatings on AlN substrates via multiple sprays, thus enabling the realization of CGS technology as a potential solution to DBC substrates for electronic packaging of wide-bandgap semiconductors.

Towards void-free copper filling of low-aspect-ratio heat dissipation through holes in packaging substrate with high H2SO4 concentration electroplating system

The void-free filling of high-density low aspect ratio (AR≤5) through holes (THs) in the packaging substrate is beneficial for promoting the integration, reliability, and heat dissipation efficiency of high-power electronic devices. It is a challenge to fill the low ARs THs compactly in direct current (DC) electroplating. The copper filling process relies heavily on the additives’ complex interactions and multiple process parameters. Herein, an ideal convection-sensitive electroplating solution formula — 2.34 M H2SO4, 0.24 M Cu2SO4·5H2O, 30 mg/L Cl−, 9 mg/L SH110, 5 mg/L NTBC, and 200 mg/L PEG — that was appropriate for low ARs THs filling was provided by investigate the electrochemical characteristics of additives. The critical electroplating parameters were optimized by thoroughly examining their influence on filling process, including current density 1.5 ASD, solution flow rate 2.2 L/min, and temperature 25 °C. The process window was enlarged apparently by the combination of optimal parameters for simultaneous void-free filling of THs with a large AR range of 0.95–5, dense crystal structure, and high layer quality could be achieved. Subsequently, the low ARs THs array filled by the optimized technology was implemented in the packaging substrate as the heat dissipation channel, which significantly promoted the heat dissipation efficiency.

A Comparative Thermal and Lumen Performance Study of Thin-film Amorphous Silicon Dielectric Coating on Aluminum as an LED Packaging Substrate

A Comparative Thermal and Lumen Performance Study of Thin-film Amorphous Silicon Dielectric Coating on Aluminum as an LED Packaging Substrate

Comparative Analysis of Thermal Properties in Molybdenum Substrate to Silicon and Glass for a System-on-Foil Integration

Advanced electronics technology is moving towards smaller footprints and higher computational power. In order to achieve this, advanced packaging techniques are currently being considered, including organic, glass, and semiconductor-based substrates that allow for 2.5D or 3D integration of chips and devices. Metal-core substrates are a new alternative with similar properties to those of semiconductor-based substrates but with the added benefits of higher flexibility and metal ductility. This work comprehensively compares the thermal properties of a novel metal-based substrate, molybdenum, and silicon and fused silica glass substrates in the context of system-on-foil (SoF) integration. A simple electronic technique is used to simulate the heat generated by a typical CPU and to measure the heat dissipation properties of the substrates. The results indicate that molybdenum and silicon are able to effectively dissipate a continuous power density of 2.3 W/mm2 as the surface temperature only increases by ~15 °C. In contrast, the surface temperature of fused silica glass substrates increases by >140 °C for the same applied power. These simple techniques and measurements were validated with infrared camera measurements as well as through finite element analysis via COMSOL simulation. The results validate the use of molybdenum as an advanced packaging substrate and can be used to characterize new substrates and approaches for advanced packaging.

Phosphononitrile based bismaleimide electronic packaging substrate with both fire safety and dielectric properties: Assisting 5G communication

Due to the high polarizability of traditional flame retardants, it is difficult to meet the excellent dielectric properties and flame retardancy required for electronic packaging materials. Therefore, we have designed a novel linear polyphosphazene that can balance the dielectric properties and flame retardancy of bismaleimide (BMI) composites. Here, fluorinated aromatic ring structure with the large freedom volume is connected to the main chain of polydichlorophosphazene (PDCP) as a side group, resulting in multifunctional fluorinated linear polyphosphazene (PBTFP). Attributed to the excellent P/N/F combination flame retardant strategy, extremely low polarizability, and large molecular free volume, PBTFP simultaneously improves the dielectric properties and flame retardancy of the BMI composites, including UL-94 rating of V0, and a dielectric constant (Dk) as low as 2.69. In addition, as an elastomer, PBTFP exhibits positive effects on improving the hydrophobicity and toughness of BMI. Therefore, through a simple affinity substitution reaction, we prepared a multifunctional fluorinated linear polyphosphazene modified BMI based electronic packaging substrate material that can be applied to 5G high-frequency communication.

Residual Stress Characterization in Microelectronic Manufacturing: An Analysis Based on Raman Spectroscopy

AbstractIn the rapidly evolving era of information and intelligence,microelectronic devices are pivotal across various fields, such as mobile devices, big data computing, electric vehicles, and aerospace. However, the electrical performance of these devices often suffers due to residual stress from microelectronic manufacturing. This issue is compounded by the additional thermal stress that accumulates during device operation. Therefore, it is essential to understand, characterize, and control this residual stress to ensure the reliability and efficiency of microelectronic devices. Raman spectroscopy emerges as an invaluable tool for nondestructive, fast, noncontact, and precise testing of micro‐scale mechanics, significantly aiding in stress and strain analysis within microelectronic manufacturing. This article aims to provide a thorough overview of the theory and application beyond a mere compilation of recent advances. Theoretically, it critically evaluates existing models that describe the Raman‐stress relation. Practically, it explores the application of Raman spectroscopy in researching residual stress in various components, including substrate materials, epitaxial films, and packaging. Through a detailed examination of current applications, it highlights the significance of Raman spectroscopy in understanding micro‐scale mechanics. Finally, it offers both theoretical and practical insights into the future developments of Raman‐stress detection technology.

Comprehensive fluorescence profiles of contamination-prone foods applied to the design of microcontact-printed in situ functional oligonucleotide sensors

With both foodborne illness and food spoilage detrimentally impacting human health and the economy, there is growing interest in the development of in situ sensors that offer real-time monitoring of food quality within enclosed food packages. While oligonucleotide-based fluorescent sensors have illustrated significant promise, the development of such on-food sensors requires consideration towards sensing-relevant fluorescence properties of target food products—information that has not yet been reported. To address this need, comprehensive fluorescence profiles for various contamination-prone food products are established in this study across several wavelengths and timepoints. The intensity of these food backgrounds is further contextualized to biomolecule-mediated sensing using overlaid fluorescent oligonucleotide arrays, which offer perspective towards the viability of distinct wavelengths and fluorophores for in situ food monitoring. Results show that biosensing in the Cyanine3 range is optimal for all tested foods, with the Cyanine5 range offering comparable performance with meat products specifically. Moreover, recognizing that mass fabrication of on-food sensors requires rapid and simple deposition of sensing agents onto packaging substrates, RNA-cleaving fluorescent nucleic acid probes are successfully deposited via microcontact printing for the first time. Direct incorporation onto food packaging yields cost-effective sensors with performance comparable to ones produced using conventional deposition strategies.

Organic package substrate embedded coupled magnetic core inductors using lithographic via technology for power supply in package

In this work, a cost-effective organic package substrate embedded coupled magnetic core inductor technology is proposed and demonstrated for power supply in package applications. Based on a novel lithographic via process, it involves a solid copper pillar electroplating step for creating a groove and integration of the vertical interconnects of the inductor. The primary and secondary windings of the coupled inductor are interleaved on the rectangular magnetic composite core which is accommodated within the groove. The coupled inductor combines solid vertical interconnecting with low loss magnetic composite core, therefore bringing together tight process tolerances and superior current capability. Experimental results show that the 2.9-mm2 coupled inductor achieves a high inductance to resistance ratio of 0.28 nH/mΩ, and a coupling factor of 0.57. In addition, the proposed inductor achieves an ultra-high saturation current of 16.52 A that is the highest reported value for a high-frequency integrated magnetic core inductor to the best of our knowledge. The performance of the coupled inductor has been calculated for a standard 1.8 to 1 V interleaved converter. Notably, it demonstrated a remarkable efficiency exceeding 95% across a wide range of phase currents between 0.11 and 2.32 A.

Low stress packaging of the small three-axis gyro

High-precision combined three-axis MEMS gyroscope is popular because of its high integration and miniaturization, but it also puts forward higher requirements for packaging. In this paper, the designed stress isolation structure is bonded between the MEMS chip and the package substrate according to the low stress method, which said the external stress is blocked and offset by the reverse stress generated by the elastic beam in the stress isolation structure, so as to ensure that the MEMS chip is kept in a low stress state. Simulation results show that the stress isolation structure can block 93.3% of the stress transmitted by the outside world. In the actual test, the stress isolation structure can also ensure that the output of the single-axis module of the three-axis gyro is stable and reliable, so as to improve the survival rate of the product.

Review of RF microsystem packaging process technology

The 3-D heterogeneous integration technology of microsystem is the best technical means to achieve higher integration, higher performance and higher working frequency of radio frequency (RF) electronic system. RF microsystem integration technology is categorized into three main types based on the packaging substrate: silicon-based, ceramic-based, and resin-based. In this work, the principle of RF microsystem integration technology is demonstrated in detail, and the process routes and characteristics of different packaging structures are clarified. Moreover, through the multi-dimensional comparison of different packaging structures, the application conditions of specific packaging structures are obtained. According to the comprehensive evaluation, the resin-based embedded chip package shows outstanding potentials in RF performance, integration capability, batch production capability and process cost. However, there are three shortcomings that limit its application in RF microsystems: Firstly, in terms of the universality of RF chips, metal grounding on the back of RF chips cannot be realized by this packaging, and special design of RF chips is required. At present, however, the universal chip with gold back grounding on the market cannot meet the requirements of the packaging process. Secondly, because of the high cost of customized chips, this packaging process is not suitable for small-scale production. Thirdly, the resin-based package does not have the sealing function, thus reliability of the product still needs to be verified. Ceramic-based RF microsystems do not require customized chips and have advantages in chip versatility compared to resin-based systems, with integration capabilities comparable to resin-based systems. However, its batch production capacity is much lower than resin based. In contrast, the silicon-based embedded chip package is as excellent as the resin-based products in chip versatility, RF performance, integration capability, batch production capability, etc., except that the manufacturing cost is high, and the yield should be effectively guaranteed in the manufacturing process. The conclusion provides a guidance for the future research of RF microsystem integration technology.

National advanced packaging manufacturing program materials and substrates (DOC)

National advanced packaging manufacturing program materials and substrates (DOC)

Nanocellulose as Sustainable Bio-Nanomaterial for Packaging and Biomedical Applications

Fibrous substrates made of cellulose like paper and paperboard are widely used in packaging. Furthermore, cellulose materials are biodegradable and completely safe for the environment. The water vapor barrier properties of paper and paperboard are limited due to the hydrophilic nature of cellulose fibrils. Paper is frequently combined with other materials, such as plastics, wax, and aluminum to improve its water barrier properties. Unfortunately, these materials lead to significant environmental problems and are difficult to recycle. Nanocellulose has shown the potential of being a substitute natural nanomaterial for creating environmentally friendly and sustainable barrier materials for a range of uses, including food packaging materials and substrates for the development of functional materials. Numerous cellulose sources can be used to create nanocellulose, which offers benefits like a high aspect ratio and tensile strength, making it useful for a variety of applications. The production of nanocellulose is done through a variety of processes. Potential biomedical applications of nanocellulose are tissue engineering, drug delivery, wound dressings, biosensors, implants and prosthetics, and nerve regeneration. Its application in these fields will result in the advancement of medical technology and the improvement of healthcare outcomes. Furthermore, biodegradable materials, barrier coatings, antimicrobial packaging, sustainable packaging solutions, smart packaging, and lightweight, high-strength packaging can all be made with nanocellulose. Nanocellulose-based packaging will improve the sustainability and efficiency of the packaging supply chain while providing environmentally friendly substitutes for conventional packaging materials.

Cost Analysis of Fan-out Processes for Chiplet Packaging

When building a design around chiplets, there are many factors to consider: industry standards, availability of chiplets within the supply chain, size requirements, and cost, to name a few. The cost of chiplet packaging is a particularly important factor that must be understood, because even if all design requirements can be met, the chiplet package will not come to fruition if the total cost is too high. The basic tradeoff between a monolithic die and a series of chiplets is a reduction in silicon costs countered by an increase in packaging costs. This analysis will compare a monolithic die flip chip package to two fan-out processes that support chiplet packaging. In the first scenario, a two-chiplet chip-last fan-out on substrate package will be compared to a standard flip chip package. For the second comparison, a monolithic flip chip package will be compared to a four-chiplet fan-out package that utilizes embedded silicon for additional interconnect. For both scenarios, a detailed cost comparison will be provided. Activity based cost modeling will be used for this analysis. In addition to looking at the direct costs of the substrated and assembly processes, yield considerations and the prices of the incoming silicon (which varies by node) will be included. The goal of this analsysis is to evaluate the cost of monolithic flip chip package versus a chiplet scenario for two designs, and to highlight the cost drivers of the fan-out chiplet packaging processes.

An Analysis of Various Design Pathways Towards Multi-Terabit Photonic On-Interposer Interconnects

In the wake of dwindling Moore’s Law, to address the rapidly increasing complexity and cost of fabricating large-scale, monolithic systems-on-chip (SoCs), the industry has adopted dis-aggregation as a solution, wherein a large monolithic SoC is partitioned into multiple smaller chiplets that are then assembled into a large system-in-package (SiP) using advanced packaging substrates such as silicon interposer. For such interposer-based SiPs, there is a push to realize on-interposer inter-chiplet communication bandwidth of multi-Tb/s and end-to-end communication latency of no more than 10 ns. This push comes as the natural progression from some recent prior works on SiP design, and is driven by the proliferating bandwidth demand of modern data-intensive workloads. To meet this bandwidth and latency goal, prior works have focused on a potential solution of using the silicon photonic interposer (SiPhI) for integrating and interconnecting a large number of chiplets into an SiP. Despite the early promise, the existing designs of on-SiPhI interconnects still have to evolve by leaps and bounds to meet the goal of multi-Tb/s bandwidth. However, the possible design pathways, upon which such an evolution can be achieved, have not been explored in any prior works yet. In this paper, we have identified several design pathways that can help evolve on-SiPhI interconnects to achieve multi-Tb/s aggregate bandwidth. We perform an extensive link-level and system-level analysis in which we explore these design pathways in isolation and in different combinations of each other. From our link-level analysis, we have observed that the design pathways that simultaneously enhance the spectral range and optical power budget available for wavelength multiplexing can render aggregate bandwidth of up to 4 Tb/s per on-SiPhI link. We also show that such high-bandwidth on-SiPhI links can substantially improve the performance and energy-efficiency of the state-of-the-art CPU and GPU chiplets based SiPs.