Package-on-package Assembly Research Articles

Stacking Yield Prediction of Package-on-Package Assembly Using Uncertainty Propagation Analysis—Part II: Implementation of Stochastic Model

The stochastic model for yield loss prediction proposed in Part I is implemented for a package-on-package (PoP) assembly. The assembly consists of a stacked die thin flat ball grid array (TFBGA) as the top package and a flip chip ball grid array (fcBGA) as the bottom package. The top and bottom packages are connected through 216 solder joints of 0.5 mm pitch in two peripheral rows. The warpage values of the top and bottom package are calculated by finite element analysis (FEA), and the corresponding probability of density functions (PDFs) are obtained by the eigenvector dimension reduction (EDR) method. The solder ball heights of the top and bottom package and the corner pad joint heights are determined by surface evolver, and their PDFs are determined by the EDR method, too. Only 137 modeling runs are conducted to obtain all 549 PDFs in spite of the large number of input variables considered in the study (27 input variables). Finally, the noncontact open-induced staking yield loss of the PoP assembly is predicted from the PDFs.

Reliability study of package-on-package stacking assembly under vibration loading

The vibration reliability of lead-free solder joints of Package-on-Package (PoP) is investigated by experimental tests and finite element method (FEM) simulations in this paper. A 14×14mm two-tier PoP module was selected for this study. The natural frequencies and modes were determined by FEM and verified by experimental tests. The printed circuit board (PCB) assemblies are tested under harmonic vibration. Vibration test results show that the vibration reliability of top package is better than the bottom package, and the outermost corner solder joints of the bottom package are the critical solder joints for the PoP under vibration loading. The stress characteristics of solder joints obtained by FEM are well correlated with the experimental results. Failure mechanism analysis indicates that the bottom solder joints become the most vulnerable part of the PoP under vibration due to the bigger relative displacements between the PCB and the bottom package. The micro-structural analysis indicates that cracks usually originate in the bottleneck position of the solder balls, extend within bulk solder and then propagate along the interface between the IMC layer and the bulk solder. The influence of bottom solder joints standoff for vibration reliability was analyzed by FEM as well. Results show that the higher the bottom solder joints' standoff, the more difficult the failure for the PoP assembly.

Optimal Design for Vibration Reliability of Package-on-Package Assembly Using FEA and Taguchi Method

In this paper, the Taguchi method and finite-element analysis (FEA) were used to improve the vibration reliability of the package-on-package (PoP) assembly and to achieve an optimal design of the PoP under random vibration loading. A finite-element model of the PoP assembly was developed, and experimental modal tests were performed to verify the finite-element model. Four geometry parameters of the PoP were chosen as the variable factors, including body size of PoP, bottom solder joint standoffs, thickness of bottom substrate, and top solder joint standoffs. The volume averaged von Mises stress of the critical solder joint obtained by FEA was chosen as the quality factor, and an $L_{9}$ ( $3^{4})$ orthogonal array was applied for Taguchi experiment to estimate the effects of the four factors and find the optimal design of the PoP on the vibration reliability. It is found that bottom solder joint standoffs have an important effect on the reliability, and more than 36% of the volume averaged Von Mises stress could be reduced by the optimal design.

Model for Inverse Determination of Process and Material Parameters for Control of Package-on-Package Warpage

Package-on-package (PoP) assemblies may experience warpage during package fabrication and later during surface mount assembly. Excessive warpage may result in loss of coplanarity, open connections, misshaped joints, and reduction in package board-level reliability under environmental stresses of thermal cycling, shock, and vibration. Previous researchers have shown that warpage may be influenced by a number of design and process factors including underfill properties, mold properties, package geometry, package architecture, board configuration, underfill and mold dispense and cure parameters, and package location in the molding panel. A comprehensive inverse model incorporating a full set of design and process parameters and their effect on PoP and PoP assembly warpage is presently beyond the state of the art. In this paper, data have been gathered on multiple PoP assemblies under a variety of assembly parameters. The packages have been speckle coated. The warpage of the PoP assemblies have been measured using a glass-top reflow oven using multiple cameras. Warpage measurements have been taken at various temperatures of the reflow profile between room temperature and the peak reflow temperature. Finite-element models have been created, and the PoP warpage predictions have been correlated with the experimental data. The experimental data set has been augmented with the simulation data to evaluate configurations and parameter variations, which were not available in the experimental data set. Statistical models have been developed to capture the effect of single and multiple parameter variations using principal component regression and ridge regression. The best subset variables obtained from stepwise methods have been used for model development. The developed models have been validated with the experimental data using a single factor design of the experimental study and are found to accurately capture material and geometry effects on part warpage. The results show that the proposed approach has the potential of predicting both single and coupled factor effects on warpage.

Package-on-Package Assembly Yield Assessment in the ODM/EMS Environment Using Monte Carlo Simulation

Package-on-package (PoP) is one of the major manufacturing strategies for achieving an electronic component miniaturization. Achieving a desired process yield is critical to maintaining competitiveness. This paper develops a scientific approach to assess the PoP assembly yield in both the x- y in-plane and the z-direction using a Monte Carlo simulation. Influences of variations of materials such as components and printed circuit boards (PCBs) are investigated. Equipment accuracy and different process strategies are also under consideration. The scenarios under which defects occur are defined through the geometric phenomena, process incidence, and theoretical inferences. Defects such as shorts and soldering open may occur after reflow soldering if there is an excessive amount of offset between the centers of the solder ball and the bonding pad during the component placement stage. The amount of component/PCB warpage during the reflow heating and coplanarity of the solder balls beneath the substrate will also impact the package stacking yield. The simulation-based design for experiment is employed to investigate the effects of soldering materials, stencil thickness, reflow temperature profile, and component ball height variation on the assembly yield. The optimal materials and process combinations are then identified.

High Performance 3D Package for Wide IO Memory

3D processor-memory packages potentially offer very high performance due to short interconnects between the two chips. Current Package-on-Package (PoP) technology offers less than 300 interconnects between the processor and memory. To meet future bandwidth requirements of greater than 25.8 GB/s bandwidth at low power, wide IO memory in x512 configuration is expected. This memory requires more than 1,000 interconnects and current PoP technologies do not scale to meet these requirements. To address this problem, a new PoP technology called Bond Via Array (BVA) PoP is presented that offers very fine pitch (0.24 mm and lower) and high height/diameter aspect ratio (8:1 and higher). This is achieved by forming free-standing wire-bonds along the periphery of the processor chip and encapsulating the package leaving miniature posts projecting from the top of the package to be connected to the memory package. More than 1,000 interconnects can be formed within the same footprint as current packages. The BVA PoP process development, assembly and reliability test results are presented. The assembly and all reliability tests including Moisture Sensitivity Level (MSL) testing, on-board temperature cycling, high temperature storage, and drop tests were successfully completed. These results demonstrate that the BVA PoP is ready for high volume manufacturing.

Control of Package Warpage by Package Substrate Design for Low Profile Package-on-Package Structure

In recent years, with increasing demand for high-density assembly in mobile electronics products, a package-on-package (PoP) structure has been standardized. The demand for lowering the PoP profile is getting stronger as consumers demand thinner mobile devices. To assemble a low profile PoP and mount it on a mother board, it is necessary to have a precise warpage control of PoP components, including its bottom package. It is expected that a flip-chip chip-scale-package (FCCSP) with thin mold cap will be used as the bottom package of the PoP in the next 2–3 years. In order to control the package warpage, it is necessary to optimize a large number of parameters related to the package substrate, silicon die and mold compound. Among them, equivalent coefficient of thermal expansion (CTE) of the package substrate is one of the most important factors. In this paper, control of the package warpage was studied by focusing on the glass-cloth content ratio in the package substrate. Glass-cloth has the lowest CTE among the constituent materials of the substrate, so it contributes to reduce the equivalent CTE of the substrate. To maximize the glass-cloth content, a substrate with a thick core and thin build-up structure was prepared, and the package with thin mold cap was subsequently formed. Compared with a similar package with a conventional substrate structure, its warpage, measured experimentally, was about 20% smaller. Consequently, it was concluded that the glass-cloth content ratio is a key factor to control package warpage behavior in the PoP assembly process.

Epoxy Flux – A Low Cost High Reliability Approach for PoP Assembly

Package on package (PoP) is a packaging that rapidly prevails in mobile devices of the electronic industry, due to its flexibility in combining memory and processor into one component with a reasonably low profile. However, similar to BGA, the solder joints of assembled PoP are prone to cracking upon dropping onto the floor, thus needing reinforcement by underfilling. The underfilling process needs an underfill material plus additional dispensing equipment, dispensing and flowing steps, and subsequent time-consuming curing. Furthermore, underfilled PoP suffers solder extrusion upon rework, particularly when reworking at the opposite side of the board right underneath the PoP. Epoxy flux is a new material developed to address the issues described above. It is a liquid epoxy with fluxing power, and it is compatible with solder paste. Applied by a dipping process, epoxy flux can be used at the mounting of bottom package and top package. First, the bottom package is dipped in a film of epoxy flux, and then placed onto the footprint pad on a PCB with or without solder paste. Then, the top package is dipped in epoxy flux and placed on top of the bottom package. The PCB with a stacked PoP is subsequently reflowed in the oven together with other surface mount components placed on printed solder paste. Epoxy flux combines soldering and reinforcement into one single process. With a controlled pick up flux volume, a venting channel is formed, allowing outgassing at reflow. The low stress characteristics of epoxy flux prevents the formation of solder extrusion. Overall, epoxy flux provides a low cost and high reliability solution for PoP assembly.

Dippable Paste: A Robust Assembly Material and Enabling Technology

Despite the tackiness offered by ball attach fluxes, they have failed to prevent ball movement on Solder on Pad (SoP) finishes when the solder protrudes above the solder mask. Dippable solder paste provides the tackiness needed for these adverse situations as well as small solder particles that inhibit ball rolling due to mechanical or convective forces downstream. Also, other pad finishes like OSP has issues with oxidation with partial pad wetting as a common defect. The use of dippable paste has also demonstrated relief with these wetting related issues. The most current application of dippable pastes is in the assembly of stacked BGA's also known as Package on Package (PoP). Although water clean formulations are typical in BGA assembly, PoP assembly typically utilizes no clean formulations. Although tacky flux has been successful in many PoP applications, issues such as coplanarity and package tolerances that require increasing the sphere size during assembly have found benefit from dippable solder paste.