Package-level Model Research Articles

A Methodology for Chip - Package Interaction (CPI) Modeling in 3D IC Structures

Chip-Package Interaction (CPI) is a significant concern for modern electronic devices and this concern is magnified for 3D Stacked IC. Hard bumps, soft dielectrics, thin die and complex geometries of the stacked die require an ability to model and evaluate the interactions and risks. In packaged IC, dissimilar materials along with the thermal history during the assembly process results in significant residual stresses. These stresses can impact process yields, reliability and die electrical performance. Examples of these effects are ball cracking, ILD/ELK cracking or delamination and shifts in the behavior of sensitive devices such as transistors in analog circuits. Traditionally modeling and evaluation of these risks have been handled by different groups/companies (foundry, OSAT, Fabless Device Mfg) and have been hindered by the difficulty of using different tools and more importantly collaborating without revealing proprietary models and process information/recipes. In this paper we present a modeling flow which incorporates a seamless interface between the tools traditionally used for both package and silicon modeling. This is accomplished by utilizing Boundary Conditions (BC's) to act as a hand-off between the two simulation tools. A package level modeling approach is developed incorporating package assembly processes to predict residual stresses at the end of package assembly process. This package level simulator uses a nested sub-modeling approach for detailed extraction of stresses at different locations within BEOL layers of die, u-bumps, and C4 bumps from package level simulations. Additionally, it allows complete flexibility in selecting boundaries at chip-package interface and then the extraction of BC's necessary for die and transistor level simulations. These boundaries for Chip-Package Interaction are selected by the device manufacturer and the output from this simulation is fed into device level simulations. To provide flexibility for the user and to attain quick turnaround time, a web hosted interface is enabled to run package simulations online. The capabilities of this modeling approach are demonstrated by studying the impact of design and material parameters on stresses at various interconnect structures constituting a typical 3D IC stack package. An example of active silicon layer stress correlation from package level model and die-level model will be presented, thus validating this overall modeling flow.

Modeling in the Cloud: Web Hosted CPI Modeling for Fabless Design Houses and OSATs Method for Mechanical Stress Simulation across the Chip & Package Domains in 3D IC's

Chip-Package Interaction (CPI) is a significant concern for modern electronic devices and this concern is magnified for 3D Stacked IC. Hard bumps, soft dielectrics, thin die and complex geometries of the stacked die require ability to model and evaluate the interactions and risks. In packaged IC, dissimilar materials along with the thermal history during the assembly process results in significant residual stresses. These stresses can impact process yields, reliability and die electrical performance. Traditionally modeling and evaluation of these risks have been handled by different groups/companies (foundry, OSAT, Fabless Device Mfg) and have been hindered by the difficulty of using different tools and more importantly collaborating without revealing proprietary models and process information/recipes. In this paper we present a modeling flow which incorporates an interface between the tools traditionally used for both package and silicon modeling. This is accomplished by utilizing Boundary Conditions (BC's) to act as a hand-off between the two simulation tools. A package level modeling approach is developed incorporating package assembly processes to predict residual stresses at the end of package assembly process. It allows flexibility in selecting boundaries at chip-package interface and then the extraction of BC's necessary for die and transistor level simulations. These boundaries for Chip-Package Interaction are selected by the device manufacturer and the output from this simulation is fed into device level simulations. To provide flexibility for the user and to attain quick turnaround time, a web hosted interface is enabled to run package simulations online. Examples are presented to demonstrate the influence and impacts of materials, process recipes and chip/package design; including an example of the flow from package level through silicon electrical level modeling to silicon hardware measurements.

Boundary-Condition-Independent Reduced-Order Modeling of Complex Electronic Packages by POD-Galerkin Methodology

The objective of the current work is to introduce the concept of boundary-condition-independent (BCI) reduced-order modeling (ROM) for complex electronic packages by employing the proper orthogonal decomposition (POD)-Galerkin methodology. Detailed models of complex electronic packages that consume large computational resources are used within system-level models in computational fluid dynamics (CFD)-based heat transfer analysis. If a package-level model that reduces computational resources (reduced-order model) and provides accurate results in many different flow situations (boundary-condition-independent model) can be deployed, it will accelerate the design and analysis of the end products that make use of these packages. This paper focuses on how the proper orthogonal decomposition-Galerkin methodology can be used with the finite volume method (FVM) to generate reduced-order models that are boundary-condition-independent. This method is successfully used in the present study to generate boundary-condition-independent reduced-order models for 1-D and 2-D objects for isothermal and isoflux boundary conditions. Successful implementation of the method is also shown on 2-D objects made of multiple materials and multiple heat generating sources for isoflux boundary conditions.