Package Height Research Articles

Agronomic biofortification of Eruca sativa L. with iron in nutrient film technique hydroponic cultivation

The global need for greater production of biofortified foods has increased especially in the case of hidden hunger. The agronomic biofortification of arugula with iron has become a strategy to solve the low intake of this nutrient in population. Therefore, the objective of this study was to evaluate the agronomic biofortification of two arugula cultivars in a hydroponic-NFT system, in two seasons (winter and summer), under the effect of different concentrations of iron in the nutrient solution. The experimental design was carried out in randomized blocks, in a factorial scheme with 4 concentrations of chelated iron (EDDHA) (1.8, 3.6, 5.4 and 7.2 g 1000 L-1) in the nutrient solution with fertilizers and 2 arugula cultivars (Astro and Roka), and four repetitions. The harvest was To carried out 25 days after transplanting (DAT) in winter, and in summer at 20 DAT. The agronomic analyzes were: plant diameter, number of leaves per plant, length and width of leaves, package height, fresh root mass and fresh shoot mass productivity in m², and iron content in shoots and roots. We found that the cultivation period influenced the plant's ability to accumulate iron. In summer, the faster metabolism of plants together with greater transpiration caused a faster daily saturation of Fe content by the roots. The plants showed an intense green color, with an increase in the iron concentration in the nutrient solution of both cultivars. We concluded that agronomic biofortification of arugula is possible in both cultivars. We observed that a concentration of 3.6 mg 1000L-1 of iron (iron content 9.70% above control) in winter is suitable for Astro. For cv.Roka, we indicated a concentration of 7.2 mg 1000 L-1 of iron (iron content 47.9% higher than the control), in summer. Both are recommended for consuming iron from plants for human nutrition.

Development of all new structure of Dicing Die Attach Film (DDAF) for Stealth Dicing and Cool Expansion processes

Mobile devices, including smart phones and tablets, are increasing in complexity and require ever greater amounts of memory storage. In the past the challenge of higher memory densities and increase functionality has been met through miniaturization of device features, but as we reach the physical limits of feature size, packaging is being relied on more and more to achieve the necessary higher densities in memory and additional device functionality. Thin dies reduce overall package height, however, to achieve high memory densities in low profile packages the die attach material must have an even, thin bond line thickness. DAF (Die Attach Film) is an excellent solution. LINTEC developed an all new DDAF (Dicing Die Attach Film) with thinner DAF for CE (Cool Expansion) process. Conventional tape has a large area of exposed DAF surface which creates the risk of wafer and / or equipment contamination if DAF flies off during the CE process. We developed an all-new tape structure which is compatible with the SD (Stealth Dicing) and CE processes. The structure consists of DAF, IB (Intermediate Basefilm), and dicing tape. The diameter of the DAF and IB is close to the wafer diameter size to significantly reduce the risk of DAF separation and ejection during CE. We considered IB to improve DAF separation and it was found that a thinner IB layer is a good approach to separate DAF effectively. We can adjust adhesion between the DAF and the IB by changing the material properties of the IB, as an effective means to control die-fly and pick-up.

Torsional and compression loading of paperboard packages: Experimental and FE analysis

The present study investigates torsional and compressive loading of a paperboard package. Finite element (FE) analyses simulating the tests were performed to improve understanding of the stresses and deformations in the paperboard during loading. A simple experimental characterization of the necessary material properties could be performed to represent the multi‐ply paperboard as a single‐ply structure. The results from the single‐ply model were compared with a laminate model, and the differences between the models were small. Comparing experimental and FE simulations of box compression and torsion showed that the FE models could accurately predict the response curves. However, in the simulations, there was an overprediction of the maximum compressive force and maximum torque, which was expected since geometrical imperfections and the heterogeneous internal structure of the material were not accounted for in the material model or the FE model. Local yield lines formed at the onset of non‐linearities in the package load–displacement curves. Therefore, the strength of the paperboard affects the maximum compressive strength and maximum torque, and the bending stiffness of the paperboard only had a minor effect. When a first local maximum was reached, the number of FE that reached the failure stress increased exponentially. The simulations also showed that box compression was not an effect of package height, but higher packages had a lower maximum torque.

Experimental Confirmations of a Constant Driving Force Lift Cart with Package Height Holding Function by Distance Sensors

Experimental Confirmations of a Constant Driving Force Lift Cart with Package Height Holding Function by Distance Sensors

Development of a Constant Driving Force Lift Cart with Package Height Holding Function

Development of a Constant Driving Force Lift Cart with Package Height Holding Function

Advanced Semiconductor Design through Specialized Printable Conductive Layer

Semiconductor package miniaturization and thinning have become of particular interest among semiconductor manufacturing industries, with each manufacturing company having specific approach and technical directions in providing unique solutions in their products. The paper provides a specialized design of manufacturing flow for semiconductor device through advanced fabrication method using stencil printing. The advanced process would significantly reduce the carrier thickness for the overall package height configuration of the device. The implementation of the specialized design and process would mitigate common assembly barriers and defects related in producing thin devices, hence, enabling cost-saving realization and manufacturing solution to package thinning and miniaturization with multiple input/output (I/O) requirements.

Incorporating Package Grinding Process for QFN Thin Device Manufacturing

Package thinning, down-scaling, and miniaturization are common interests among semiconductor industries, with each manufacturing site having different approach and technical directions in providing novelties in their products. The paper offers an innovative design of manufacturing flow to reduce the semiconductor package height of a Quad-Flat No-leads (QFN) device through the application of a specialized package grinding process. The process would significantly reduce the carrier thickness for the overall package height configuration of QFN. Through this integration, the common assembly barriers and defects related in producing thin devices are eliminated, thus thinner version manufacturing becomes more simplified and efficient.

A reflection-type vapor cell using anisotropic etching of silicon for micro atomic clocks

This paper reports the design, fabrication and evaluation of a reflection-type optical Rb vapor cell for chip-scale micro atomic clocks. To reduce the physical package height, the reflection-type vapor cell is developed, in which optical components can be mounted on one side of the vapor cell. A (100)-oriented Si wafer with a cut-off 9.74° toward [011] direction is used to make 45° mirrors by anisotropic wet etching. 90° mirrors are fabricated by Si deep reactive ion etching and surface planarization using H2 annealing. Following the detection of D1 optical absorption for Rb atoms, coherent population trapping resonance was observed.

Quality deterioration of bananas in the post-harvest supply chain- an empirical study

Purpose Quality deterioration in bananas along the supply chain (SC) due to cosmetic damage has been a persistent challenge in Australia. The purpose of this paper is to investigate the incidence of cosmetic defects in bananas across the post-harvest SC and determining the causes of the diminished fruit quality at the retail stores. Design/methodology/approach The study quantified the level of cosmetic damage in 243 cartons of Cavendish bananas across three post-harvest SCs in Australia from pack houses to retail stores and identified the risk factors for cosmetic defects. Findings The level of cosmetic damage progressively increased from pack house (1.3 per cent) to distribution centre (DC) (9.0 per cent) and retail (13.3 per cent) and was significantly influenced by package height and pallet positioning during transit. Abrasion damage in ripened bananas was influenced by the travel distance between DC and retail store. The study also revealed a range of risk factors contributing to the observed damage including weakened paperboard cartons due to high moisture absorption during the ripening process. Research limitations/implications This study only investigated damage incidence in three post-harvest banana SCs in Australia and the damage assessments were confined to packaged bananas. Originality/value This study assessed the quality of bananas along the entire post-harvest SC from farm gate to retail store. The study provided knowledge of the extent of the quality defects, when and where the damage occurred and demonstrated the underlying factors for damage along the SC. This will enable the development of practical interventions to improve the quality and minimize wastage of bananas in the retail markets.

ELASTICITY PROPERTIES OF DATE FRUITS UNDER DEFICIT IRRIGATION TO PREDICT PACKAGE HEIGHT

The aim of this work was to determine the effect of deficit irrigation on the physical and elasticity properties of date fruits (Phoenix dactylifera, cv. Khudary) during three stages of repining (Khelaal, Rutab and Tamr) for two years (2014 and 2015) to predict the package height of date fruit. Four irrigation treatments were studied: (ET1): 1.0 ETc ) one time potential crop evapotranspiration(, ET2: 0.85 ETc, ET3: 0.75 ETc and ET4 :0.65 ETc). The physical properties included date mass, volume, dimensions, moisture content, bulk density, solid density, flesh thickness, flesh mass and elasticity of fruits. The elasticity properties of fruit included young's modulus of elasticity (E), firmness coefficient (FC), bio-yield stress point (σb), bio-yield strain point (eb), rupture stress point (σr) and rupture strain point (er). The results showed that the deficit irrigation affected both physical and mechanical properties, therefore, affected on package height of date fruits. The maximum packing heights for Khellal, Rutab and Tamr were 6360.51, 654.2 and 1850 mm with ET1, ET2 and ET3, respectively. While, the minimum packing heights for Khellal, Rutab and Tamr were 3738, 206.6 and 1411 mm with ET4, ET3 and ET1, respectively.

Development of Fan Out Package Platform for High Performance and RF Applications

ABSTRACT Over the last few years quite significant and well publicized advancements have been made in the IC industry in the potential adoption of fan out wafer level package platforms for both analog and digital applications. HD-FO platforms are likely to find significant adoption in the mobility, consumer application space as these have the capability to achieve sub-micron package routing density, high processor/memory and interconnect band width, very thin package height and small foot print area. Development of HD-FO package development reported in this work includes:Multiple advanced silicon technology nodesBroad range of package sizesSingle die, multi-die packagesDifferent package configurations that include with substrate, without substrate, organic and inorganic package redistribution layer optionsSystem in Package (SiP) for RF applications An electrical simulation based lateral and vertical interconnect insertion loss comparison is being reported for high density fan out packages and silicon interposer with through silicon via (TSV). Multiple metal layers, interconnect widths, organic and inorganic redistribution layers are modelled. High density fan out package provides orders of magnitude less vertical interconnect loss in comparison to TSV. Least lateral interconnect insertion loss is demonstrated by organic interconnect based HDFO package. For RF applications HDFO package based inductors of 1.1nH and 3.3nH demonstrate ~ 3 X improvements in Qmax when compared to similar CMOS based inductors. In addition to providing differentiating technology value propositions through the advanced HD-FO packaging platform collaborative ecosystem, customer centric business model and flexible supply chains are also being built to meet the business requirements for the integrated circuit customers. Finally, silicon/package co-design environment and RF enablement will ensure that customers realize the benefits of seamless product design, fast yield feedback and reduced time to market.

Package Thickness - Ultrathin WLFO (Wafer-Level Fan-Out)

Abstract NANIUM's Fan-Out Wafer-Level Packaging technology WLFO (Wafer-Level Fan-Out) is based on embedded Wafer-Level Ball Grid Array technology eWLB of Infineon Technologies [1]. Since it′s invention almost 10 years ago, it became the leading technology for Fan-Out Wafer-Level packages. The WLFO technology is based upon the reconstitution of KGD (known good die) from incoming device wafer, independent of wafer diameter and material, to recon wafer format of active semiconductor dies or other active/passive components separated by mold compound applied through compression molding on a temporary mold carrier. The resulting recon wafer can be processed in standard wafer processing equipment. One of the challenges for the future of semiconductor packaging is reduction of the board level volume real estate occupied by each component. With the drive towards lower profile end user devices incorporating large display area and battery life the three dimensional space available for semiconductor packages is diminishing. It is well known that WLFO single die packaging but even more significant system integration enables the shrinkage of the XY footprint of the package through flexible very dense heterogeneous system-in-package integration [2]. But one of the disruptive advantages of the substrate-less WLFO technology is to also permit significant reduction of the overall package height (Z). A total package height for a BGA package including solder balls <500um and for a LGA package with solder land pads only <300um is achievable today, and further development towards even thinner packages is on the way.

Impact of Top Die Thickness on Cu Pillar Fatigue in Exposed Die 3D Packages

Customer demand for more powerful, faster, and multifunctional electronic devices in lighter and smaller form factors is forcing the electronics industry to expand the edges of the packaging envelope. 3D packaging is a result of such initiatives. Logic and memory dice (or logic and logic dice) are stacked on top of one another and connected through vertical Through Silicon Vias (TSVs). 3D integration has several well documented benefits such as lower power consumption, higher bandwidth, and low latency, to name a few. An added benefit of such a packaging scheme is that it reduces overall package dimensions compared to Multi-Chip Modules (MCMs). However, since the dies are stacked, total package height generally increases. One of the methods to minimize this effect is to use exposed die package construction. In this paper, exposed die 3D packages are examined and challenges associated with stacking thin dies with exposed molding are discussed. Exposed die package construction is of high importance to customers in mobile markets where power requirements and heat generation are low, but package thickness is of utmost importance. Data has been generated using a 20nm CPI (Chip Package Interaction) die which is packaged in a 3D format to study the impact of die stacking along with the presence of TSVs on Ultra Low-k (ULK) dielectrics. ULKs are commonly used in the Back End of Line (BEoL) during Si device wafer fabrication. Via middle TSV integration scheme is used to integrate TSVs in the CPI chip and a face-to-back (F2B) approach is used to assemble the top die on the CPI chiplet. The top die is mechanical in nature with Cu micro pillars and a few metal layers to form daisy chain structures when joined to the backside of TSV die. The CPI wafers are bumped on the frontside using Cu pillars and the wafers are then thinned to ~50um. The TSVs are carefully exposed from the wafer backside and wettable landing pads are patterned on the backside of the thinned wafer so as to align with the Cu micro pillars on the front side of top die. Two different thicknesses of top dies are used to study the impact of top die thickness on overall package warpage and Si-to-substrate interconnect reliability. Assembly is performed by first bonding the front side of TSV CPI chip to a substrate, and then by bonding the front of the top dies to the back of the bottom (TSV) die. The 3D packages were subjected to a variety of package level stresses and the reliability results will be presented. The effect of top die thickness is analyzed using two die thicknesses. As the packages are stressed, it is evident that packages with thinner top die show higher package level warpage and greater Cu pillar fatigue. Various mold compounds are used to improve the package warpage and data will be presented.

Quality Monitors and Inspection Criteria for Bare Die Flip Chip Ball Grid Array and Bare Die PoP Packages.

Package form factor and cost are one of the key drivers in smart phone and tablet landscape. In order to meet these requirements hand held market has seen emergence of bare die flip chip ball grid array (BD FCBGA) and bare die package on package (BD PoP). As the name implies, these packages don't have a mold cap or heat spreader surrounding the silicon die resulting in lower cost and smaller form factor. Further package thickness reduction is possible by thinning of silicon die without significantly affecting high temperature (HT) warpage or coplanarity. One of the main concerns with aforementioned bare die package (BDP) configurations is die crack failure during assembly, testing, shipping or surface mount operation (SMT). The propensity of die crack failures further increases as thinner die is employed to meet overall package height requirements. This work focusses on evaluating various inspection tools for detecting gross die cracks to fine line cracks up to ~ 0.7 μm wide. Some of the key considerations for inspection tools, at assembly and test operations will be presented.

Absorber design for the improvement of the efficiency of post-combustion CO2 capture

The objective of this paper is to design the absorber unit in order to separate the CO2 of the flue gases resulted from coal combustion. The design model was made for various types of packages using plastic, ceramic or metal rings. It was also considered that the capture process efficiency was 85%, and the monoethanolamine concentration in the solution varied between 10 and 30%. We analyzed the oldest and the newest types of package rings (Raschig rings, ceramic Berl saddle rings), as well as various types of metal and plastic Pall rings. In the model developed in this paper, the physical properties of package materials were taken into account (density, surface area, void fraction, etc). By applying the proposed model, we obtained results concerning the influence of the L/G ratio on the CO2 capture efficiency, the rich and the lean loading solvent, the solvent flow pumped through the absorber unit, the type and the size of package (height, diameter, etc). The objective of the paper is to compare the experimental results obtained in the CFBC (Circulating Fluidized Bed) pilot installation with those obtained in the mathematical model.

Mechanical Analyses of Advanced Multi-Chip Embedded Wafer Level Packages

ncreasing functionality accompanied with device miniaturization in microelectronics has led to increased market demand for packages with small form factor. Over the years, embedded wafer level packaging (EWLP) has become an attractive option since it allows a reduction in package size and height. In the EWLP approach, the singulated dies are embedded within the molding compound through the wafer level compression molding process. For this study, critical mechanical challenges such as die shift and thermal cycling performance of a multi-chip embedded wafer level package (MCEWLP) are addressed through numerical modeling. For improved accuracy in die shift predictions, both mechanical effects and fluidic effects need to be taken into account. Mechanical effects account for around 75% of the die shift while fluidic effect contributes to the remaining 25%. It is shown that reducing the die size and the inclusion of UBM as a buffer layer can effectively increase the fatigue life of the packages.

3D Packaging Solution Providing DDR & LPDDR Co-Support for Ultrabooks and Next Generation Servers

Effective 3D stacking of DRAM devices can offer many benefits; improved performance, increased component density and greater surface area utilization. To enable the new generations of processors to reach their performance potential many manufacturers have developed more efficient interface formats that enable greater memory bandwidth. This revolution in performance driven electronic systems continues to challenge the IC packaging industry. The challenge is clear. To ensure that the memory functions are able to support the increased signal speed, product developers will need to explore more innovative 3D package assembly techniques and process refinement methodologies. The methodology selected for package assembly, however, must consider process complexity, the costs associated with each process, overall package assembly yield and, from the users perspective, end product reliability. For some applications companies have had limited success in stacking die elements directly onto an interposer substrate using wire-bond processes. High performance DRAM die, however, is especially difficult to stack. This is due to the center positioned wire-bond sites. This factor has complicated the DRAM die stacking process and because of the excessively long wire-bond interface, functional signal speed is significantly degraded. Stacking individually packaged DRAM (package-on-package) has had considerable success but the package outline dimension and package height can be excessive. In this paper the authors will introduce a very innovative and very thin 3D package developed specifically for center-bond pad DRAM die. The package assembly methodology promises to remain economical because it requires no special die level process steps and it can utilize the existing package assembly infrastructure. Additionally, data compiled during extensive performance and reliability modeling will be presented along with the results from actual physical qualification testing.

Ultra-Slim Packages

What does thin or ultra-slim packaging mean? That of course depends on the particular cross-section of the substrate e.g. single layer vs. double layer vs. coreless or embedded component substrate, etc. The thinnest prepreg based substrate and concomitant package is a single layer substrate termed a-S3 ™ and can be as thin as 90 μ and 400 μ, respectively, with the appropriate mold cap. The manufacturing concept for a-S3 has inspired a new manufacturing concept for thin prepreg based coreless substrates with any number of layers. Layers two through five have been demonstrated successfully. The practical layer count is limited only by yield and cycle time. The same concept has been extended also to embedding active die as well as passives, a-EASI™. The total package height here is governed by the thickness of the embedded elements. The simplest embedded substrate is a two layer substrate with a MOSFET die. The advantage is a very low profile power package with excellent electrical and thermal performance. The interconnections to the die/passives are formed by plated laser vias as is common practice. Process flows and concepts will be introduced here. Thin substrates do pose many challenges during substrate manufacturing as well as during assembly. Some of the handling concepts will be elucidated. Sample pictures will be shown to demonstrate successful builds and some reliability data will be presented as well.

Thin Substrates Bursting into the Market

The continued drive for miniaturization by mobile applications demands its toll also from packaging. Innovative packages are required to shrink volume and weight of packages. This has led to the development of single layer, coreless and embedded component substrates. The thinnest prepreg based substrate and concomitant package is a single layer substrate termed a-S3 ™ and can be as thin as 90 μ and 400 μ, respectively, with the appropriate mold cap. The manufacturing concept for a-S3 has inspired a new manufacturing concept for thin prepreg based coreless substrates with any number of layers. Layers two through seven have been demonstrated successfully. The practical layer count is limited only by yield and cycle time. The same concept has been extended also to embedding active die as well as passives, a-EASI™. The total package height here is governed by the thickness of the embedded elements. The simplest embedded substrate is a two layer substrate with a MOSFET die. The advantage is a very low profile power package with excellent electrical and thermal performance. The interconnections to the die/passives are formed by plated laser vias as is a common practice. Process flows and concepts will be introduced here. Thin substrates do pose many challenges during substrate manufacturing as well as during assembly. Some of the handling concepts will be elucidated. Sample pictures will be shown to demonstrate successful builds and some reliability data will be presented as well.

300mm Large Scale eWLB(embedded Wafer Level BGA) : Cost Effective Solution with Performance

Demand for Wafer Level Package (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. The increasing demand for new and more advanced electronic products with smaller form factor, superior functionality and performance is driving the integration of functionality into the third dimension. There are some restrictions in possible applications for fan-in WLPs since global chip trends tend toward smaller chip areas with an increasing number of interconnects. The shrinkage of the pitches and pads at the chip to package interface is happening much faster than the shrinkage at the package to board interface. This interconnection gap requires fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. eWLB is a type of fan-out WLP that has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology. 200mm eWLB is in HVM from industry last three years and there was need to move 300mm for scaling-up and low-cost solutions. This paper will highlight some of the recent advancements in large scale 300mm eWLB development. Compared to 200mm case, 300mm has more warpage and process issues due to its area increase. Thermo-mechanical simulation shows 100~150% more warpage with 300mm compared to 200mm. So various design parameters were studied to optimized warpage, such as dielectric materials and thickness, molding compound thickness etc. This paper presents study of process optimization for 300mm eWLB and mechanical characterization, reliability data including component/board level, challenges encountered and overcome, and future steps of scalability for higher throughput and manufacturability.