Package Ball Research Articles

Ball: An R Package for Detecting Distribution Difference and Association in Metric Spaces

The rapid development of modern technology has created many complex datasets in non-linear spaces, while most of the statistical hypothesis tests are only available in Euclidean or Hilbert spaces. To properly analyze the data with more complicated structures, efforts have been made to solve the fundamental test problems in more general spaces (Lyons 2013; Pan, Tian, Wang, and Zhang 2018; Pan, Wang, Zhang, Zhu, and Zhu 2020). In this paper, we introduce a publicly available R package Ball for the comparison of multiple distributions and the test of mutual independence in metric spaces, which extends the test procedures for the equality of two distributions (Pan et al. 2018) and the independence of two random objects (Pan et al. 2020). The Ball package is computationally efficient since several novel algorithms as well as engineering techniques are employed in speeding up the ball test procedures. Two real data analyses and diverse numerical studies have been performed, and the results certify that the Ball package can detect various distribution differences and complicated dependencies in complex datasets, e.g., directional data and symmetric positive definite matrix data.

Study of unsteady thermal conductivity of a package consisting of one layer of equal-size balls

The study of unsteady heat transfer of a package consisting of the equal-size balls was performed at boundary conditions of the first kind. The package was located on a horizontal surface and was limited by the walls of a cylindrical thermostat 129 mm in diameter. The experiments were carried out using glass balls with a diameter of 8.85 mm, 16.0 mm, as well as polyoxymethylene balls with a diameter of 9.0 mm. The package was filled with water. The height of the water layer was equal to the diameter of the balls. In the experiments, the time was determined during which the ball package was heated or cooled to the temperature of the thermostat. It is shown that the time of temperature equalization between the package and the thermostat depends not only on the material and size of the balls but also on the direction of the heat flux. It is shown that the heating time of one layer of equal-size balls is much shorter than the cooling time.

New Method for Determining and Predicting Test Interconnect Pin Current Carrying Capacity

With new advances in the semiconductor technology, current carrying requirements for electronic packages and interconnects (sockets) are on the rise. Although there are a lot of documented methods for determining current carrying capacity (CCC) of electrical wires, there is no specific industry standard for determining current carrying capacity of socket pins and their contact interface with package balls and pads. This paper presents a new current carrying capacity measurement method, developed specifically to address the challenges of test socket pins and their contact interface with solder balls and pads. In addition, a method for predicting CCC in future test socket pins is presented and correlated to measured data.

Level of exposure to fluorides by the consumption of different types of milk in residents from an area of Mexico with endemic hydrofluorosis

IntroductionSeveral studies have shown the presence of fluorosis (DF) in primary dentition, suggesting an exposure to fluorides (F−) in early childhood. Breast milk is recommended as an exclusive food until 6 months of age. Although it is mentioned that only a small amount of F− can be eliminated by breast milk, studies have shown the presence of this element in milk of women living in contaminated areas, as well as in infant formulas. The objective of this project was to evaluate the exposure level to F− through milk in children living in an area with endemic hydrofluorosis. MethodologyThe study included 110 children between 6 and 36 months of age from the municipality of Lagos de Moreno, Jalisco. Water samples were collected from the homes, as well as samples of milk (maternal, formula, whole or raw), and urine. Measurements were made with a selective ion electrode. The exposure level of F− for milk intake was calculated using the Oracle Crystal Ball package. ResultsLevels greater than the reference level for DF were observed in infant formula reconstituted with public supply water, pasteurised cow's milk (whole) and untreated cow's milk treatment (raw) in the 90th, 70th, and 50th percentile, respectively, with a correlation being found between the levels of F− in milk and F− in urine (r=0.41, P<0.001). ConclusionsThe identification of sources of F− in the early stages of child development could reduce the risk of developing DF.

Level of exposure to fluorides by the consumption of different types of milk in residents from an area of Mexico with endemic hydrofluorosis

Several studies have shown the presence of fluorosis (DF) in primary dentition, suggesting an exposure to fluorides (F-) in early childhood. Breast milk is recommended as an exclusive food until 6 months of age. Although it is mentioned that only a small amount of F- can be eliminated by breast milk, studies have shown the presence of this element in milk of women living in contaminated areas, as well as in infant formulas. The objective of this project was to evaluate the exposure level to F- through milk in children living in an area with endemic hydrofluorosis. The study included 110 children between 6 and 36 months of age from the municipality of Lagos de Moreno, Jalisco. Water samples were collected from the homes, as well as samples of milk (maternal, formula, whole or raw), and urine. Measurments were made with a selective ion electrode. The exposure level of F- for milk intake was calculated using the Oracle Crystal Ball package. Levels greater than the reference level for DF were observed in infant formula reconstituted with public supply water, pasteurised cow's milk (whole) and untreated cow's milk treatment (raw) in the 90th, 70th, and 50th percentile, respectively, with a correlation being found between the levels of F- in milk and F- in urine (r=0.41, P<.001). The identification of sources of F- in the early stages of child development could reduce the risk of developing DF.

Z-Directed Component (ZDC) Technology for Power Integrity Applications

An important aspect of ensuring the power integrity of a power distribution network (PDN) design is to determine the layout, value, package size, and number of decoupling capacitors. To solve the limitation of the vertical connection of the surface-mounting-type capacitor to the power net area fill, a new concept of a capacitor denoted the Z-directed component (ZDC) is proposed in this paper. There are many applications possible with the ZDC with the first implementation as a decoupling capacitor. The ZDC capacitors can be integrated within the printed circuit board (PCB) substrate directly below the package ball and eliminate the integrated circuit (IC) to decoupling capacitor horizontal distance across the power net area fill. Furthermore, the inductance associated with the vertical current paths on the vias from the IC package to the horizontal power net area fill and similarly for the surface-mounted technology decoupling capacitors is eliminated. Since only the inductance of the ZDC capacitor itself remains, there is the possibility of using far fewer capacitors to achieve a high-frequency target impedance specification. The ZDC is a promising technology that gives the PCB designer the opportunity to integrate low equivalent series inductance decoupling capacitors much closer to the noise source than traditional surface-mount capacitors. In addition, in this paper, a high-order model is introduced for the ZDC capacitor to better understand the high-frequency characteristics of the component and is verified with measurements.

Design of High Cleanliness Globe Valve with Sine Mechanism Drive

This paper give a new type of quick-opening globe valve for life support pneumatic control system of the safety cabin at underground coal mine. The valve adopts the sine mechanism to transmit the rotating of the handle in the range of 90° to the reciprocating motion of the spool. The mechanism implements the quick-opening function of the valve through controlling the contact and separation between the Oring and the end face of the valve. Since there is no relative sliding between the sealing interfaces, the valve solute uncontrollable disadvantage wear particles which produced by package ball valve, to ensure high cleanliness in flow path. Traditional transmission mechanism has a reinforcement effect, and reduce handle open torque. By the finite element method, the relationship between the contact force and the compression of O-ring is analyzed to provide the boundary condition for the calculation of the rotational torque. Meanwhile the velocity field and pressure field along the flow path are simulated. The caliber size of the valve and the flow resistance coefficient are obtained. There are higher cleanliness, more reliable sealing, and smaller handle open torque advantage compared with existing packing ball valve. The above work presents a new technical approach for the design of pneumatic control valve of the safety cabin.

Temperature progression in a mixer ball mill

The influence of the operating frequency, the milling ball and grinding stock filling degree, the material of the milling balls and beakers, the milling ball diameter and the size of the milling beakers on the temperature increase inside the milling beakers in a mixer ball mill was investigated. These parameters influence the temperature progression and the equilibrium temperature of the system. The grinding stock filling degree with regard to the void volume in the milling ball package showed huge influence on the heating rate and the equilibrium temperature. In this context, the behavior of the temperature progression changes if the complete void volume is filled with the grinding stock.

Optimal design of fatigue life for RCP with PoP package by using the Taguchi method

SummaryIn recent years, the electronic industries tend to offer products with smaller scales, lower cost, larger storage space and integration of various functions. The development of redistributed chip package (RCP) technology is facilitated to reduce package size for three‐dimensional integration and to enhance packaging capability for miniature requirements. Meanwhile, the logic unit is required to be combined with the memory unit to achieve miniaturization and system integration.The RCP with package on package (PoP) is constructed by stacking the RCP for the very fine pitch ball grid array at topside and the stack package ball grid array (SPBGA) at bottom side. The finite element software ANSYS is adopted in this study using the Global/Local modeling approach. The reliability of the RCP with PoP is subjected to a thermal cycle test of ‐40‐125 °C based on JEDEC specification. The Coffin‐Manson strain‐based model and the Morrow energy‐based model are employed for prediction of package fatigue life, in which the SAC387 (95.5Sn3.8Ag0.7Cu) solder joints are treated as viscoplastic behavior according to the Anand constitutive model. The other materials are modeled as elastic behavior.To investigate the solder joint reliability for the stacked package design, a numerical experiment by means of the single factor analysis is first conducted for investigation. The material factors such as Young's Modulus and coefficient of thermal expansion, the geometric factors such as component thickness are evaluated. Accordingly, the significant factors are filtered and analyzed by the Taguchi method to obtain the optimal combination. As a result, the optimal design increases package fatigue life, which contributes a significant improvement by up to 86.5% when comparing with the original model.Copyright © 2014 John Wiley &amp; Sons, Ltd.

Small-Size Low-Cost Wideband Continuous-Time Linear Passive Equalizer With an Embedded Cavity Structure on a High-Speed Digital Channel

This paper proposes a wideband continuous-time passive equalizer with an embedded cavity structure that is more compact in size and enables lower-cost processing than conventional technologies. The proposed passive equalizer is composed of a lumped resistor and capacitance in a cavity structure generated by a parasitic channel parasitic component, such as a package ball pad. This equalizer design in which the capacitance is embedded in the cavity structure offers the advantages of reducing the additional occupied printed circuit board (PCB) area and of enabling a small-sized equalizer with a large capacitance for application in high-density systems. For a 40-cm transmission line on PCB with a data rate of 12.5 Gb/s, the measured eye diagram is successfully demonstrated and the eye opening significantly improved to 81.1 mV, with a timing jitter of 28.7 ps.

A study of row-based area-array I/O design planning in concurrent chip-package design flow

IC-centric design flow has been a common paradigm when designing and optimizing a system. Package and board/system designs are usually followed by almost-ready chip designs, which causes long turn-around time communicating with package and system houses. In this article, the realizations of area-array I/O design methodologies are studied. Different from IC-centric flow, we propose a chip-package concurrent design flow to speed up the design time. Along with the flow, we design the I/O-bump (and P/G-bump) tile that combines I/O (and P/G) and bump into a hard macro with the considerations of I/O power connection and electrostatic discharge (ESD) protection. We then employ an I/O-row based scheme to place I/O-bump tiles with existed metal layers. By such a scheme, it reduces efforts in I/O placement legalization and the redistribution layer (RDL) routing. With the emphasis on package design awareness, the proposed methods map package balls onto chip I/Os, thus providing an opportunity to design chip and package in parallel. Due to this early study of I/O and bump planning, faster convergence can be expected with concurrent design flow. The results are encouraging and the merits of this flow are reassuring.

Ball Grid Array Solder Joint Reliability Under System-Level Compressive Load

Heatsinks have been widely used in the electronics industry as a thermal solution for high-performance and highpower-density devices. The thermal efficiency of heatsink solutions may be improved by increasing the compressive load applied on the interface between the electronic package and heatsink. Typical approaches for heatsink retention, however, would also lead to high levels of compressive load on the package ball grid array (BGA) solder joints. In this paper, the effect of compressive load on SnPbAg solder joint reliability is investigated by using both experimental and numerical approaches. Accelerated system-level solder joint reliability tests under temperature cycling and isothermal aging conditions, with the presence of compressive loads, are first performed to identify and characterize the critical reliability failure mode. Creep constitutive behavior under compression is then characterized and implemented in numerical finite-element simulations for developing a phenomenological model of the BGA solder joint failure under compressive loading. A life prediction formula for SnPbAg solder joint subject to constant compressive load is also proposed.

Validated High Speed Pull and Shear Test Methodologies to Evaluate Pb-Free BGA Mechanical Strength

The conversion to lead free Ball Grid Array (BGA) packages has raised several new assembly and reliability issues. Lead-free solder joints are generally stiffer than tin-lead solder joints, and mechanically induced failures have become more prevalent in lead-free solder assemblies. Traditionally, assembly bend and shock testing is performed to evaluate mechanical assembly reliability. However, bend and shock tests are expensive, cumbersome and not feasible for evaluating lot-to-lot variations in mechanical strength. Consequently, there is a need for a validated, component level test method that can be used as an accurate indicator of assembly level mechanical strength. Several publications have been written to evaluate the efficacy of high speed pull and shear testing as a viable reliability indicator [1 – 10]. In this study, a comprehensive Gauge R&amp;R study was performed to evaluate the accuracy of the test equipment, including high speed video calibration. Then, test studies were performed to compare the accuracy of the results, spread across different package constructions, solder metallurgies, ball pitch and surface finish. In addition, the effect of parameters like multiple reflows and aging on specific metallurgies and surface finishes was studied. The results were generated over more than 2000 test runs. Finally, the study rank orders all critical test parameters and articulates what precise steps can be taken to generate relevant data for standard and custom devices during early evaluation stages and during high volume manufacturing.

Fast Flip-Chip Pin-Out Designation Respin for Package-Board Codesign

Deep submicrometer effects drive the complication in designing chips, as well as in package designs and communications between package and board. As a result, the iterative interface design has been a time-consuming process. This paper proposes a novel and efficient approach to designating pin-out, which is a package ball chart describing pin locations for flip-chip BGA package when designing chipsets. The proposed approach can not only automate the assignment of more than 200 input/output (I/O) pins on package, but also precisely evaluate package size which accommodates all pins with almost no void pin positions, as good as the one from manual design. Furthermore, the practical experience and techniques in designing such interface has been accounted for, including signal integrity, power delivery and routability. This efficient pin-out designation and package size estimation by pin-block design and floorplanning provides much faster turn around time, thus enormous improvement in meeting design schedule. Our pin-block design contains two major parts. First, we have pin-block construction to locate signal pins within a block along the specific patterns. Six pin patterns are proposed as templates which are automatically generated according to the user-defined constraints. Second, we have pin-blocks grouping to group all pin-blocks into package boundaries. Two alternative pin-blocks grouping strategies are provided for various applications such as chipset and field-programmable gate array (FPGA). The results on two real cases show that our methodology is effective in achieving almost the same dimensions in package size, compared with manual design in weeks, while simultaneously considering critical issues and package size migration in package-board codesign.

Study on the behavior characteristics of solder balls for FCBGA package

Warpage issues are of concern for flip chip Ball Grid Array (FCBGA) package reliability on thin substrates. Despite advantages in electrical performance of thin substrates, FCBGA warpage hampers reliability of the solder balls making up the ball grid array. Warpage and plastic strain of both the FCBGA package and solder balls are calculated under assembly conditions. Temperature dependent material properties were investigated using finite element analysis. FEM calculations of thermal deformation and equivalent plastic strain of solder balls considered to determine overall reliability of the solder balls. Solder ball plastic strain decreased with substrate core thickness. This can explain why solder ball reliability decreases with substrate thickness. Substrate surface warpage fluctuated significantly as core thickness decreased due to reduced stiffness. In addition, it is possible that solder balls and surface mounted components can be affected by surface fluctuations. Although thinner substrates have advantages in terms of electrical performance, high warpage is a critical root cause of package failure. Despite these tradeoffs, developing thinner substrates while avoiding warpage is a forefront issue.

A Methodology for Drop Performance Modeling and Application for Design Optimization of Chip-Scale Packages

As handheld electronic products are more prone to being dropped during useful life, package to board interconnect reliability has become a major concern for these products. This has prompted the industry to evaluate the drop performance of CSP packages while mounted on printed wiring boards using board level drop testing. Although a new board level test method has been standardized through JEDEC (JESD22-B 111), characterization tests take quite a long time to complete, extending the design cycle. This paper proposes a method to compare and evaluate the drop performance through simulations at the design stage. A global-local approach is used to first determine the dynamic response of the board during drop and then to translate it into stresses and strain energy density in solder joints and intermetallic layers. The dynamic response of the board is validated by using data from actual board level testing as per JEDEC standard. The solder joint and intermetallic stresses are then related to drop to failure test data to derive a prediction model. The method is then applied to quantify the effect of package design parameters on the drop performance. Factors considered include material set, thickness of various material layers, pad size, and ball size. The same factors were tested in board level drop to further validate the prediction model. Experiments were also conducted to quantify the effects of package ball pad finish on the drop performance through board level testing according to JESD22-B111. The results indicate that the drop performance can be increased by a factor of 4 or more by changing package design and material variables.

SLICK − Scoring and Energy Functions for Protein−Carbohydrate Interactions

Protein-carbohydrate interactions are increasingly being recognized as essential for many important biomolecular recognition processes. From these, numerous biomedical applications arise in areas as diverse as drug design, immunology, or drug transport. We introduce SLICK, a package containing a scoring and an energy function, which were specifically designed to predict binding modes and free energies of sugars and sugarlike compounds to proteins. SLICK accounts for van der Waals interactions, solvation effects, electrostatics, hydrogen bonds, and CH...pi interactions, the latter being a particular feature of most protein-carbohydrate interactions. Parameters for the empirical energy function were calibrated on a set of high-resolution crystal structures of protein-sugar complexes with known experimental binding free energies. We show that SLICK predicts the binding free energies of predicted complexes (through molecular docking) with high accuracy. SLICK is available as part of our molecular modeling package BALL (www.ball-project.org).

Thermal deformation measurements and predictions of MAP–BGA electronic packages

The thermally-induced deformations of MAP–BGA (matrix array package–ball grid array) packages are investigated experimentally, numerically and theoretically. In the experiments two full-field optical methods: Moiré and Twyman–Green interferometries are employed for the in-plane displacement measurements on the edge and center surfaces of the specimen and the out-of-plane displacement measurements on the top surface of the specimen, respectively. The thermal deformations under various temperature loads are recorded during the heating history. The 3-D linear finite element model is used to validate the experimental observations. A simple beam deflection theory is also newly proposed for prediction of the deformations. The results from the experiments are presented and compared in detail with those from the 3-D linear finite element and theoretical analysis. The good agreements in the experimental and modeling results reveal the validation of experimental data in mechanics sense and the effectiveness of the numerical and theoretical models in physics predictions. It is also observed and verified that the compliance of die attach material above its T g (glass transition temperature) give more than 25% warpage reduction of that without taking into account T g effect at high temperature. As a result, neglecting this effect in the modeling will significantly influence the solder ball reliability prediction.

Uniformity and characterisation of PVD aluminium films

Aluminium is a very important material used in the semiconductor industry as an interconnection layer. The most popular method of depositing aluminium films is the physical vapour deposition (PVD) process. The objective of the present study is to improve aluminium film uniformity by optimising the process conditions to use a thicker target and meet the demand for more uniform films on wafer surfaces. Aluminium films were deposited by a sputtering process on 200 mm wafers in PVD chambers. Experiments were carried out to find the process factors that affect film uniformity. The results revealed that film uniformity was affected significantly by wafer to target spacing and process pressure. Film characterisation was then performed by measuring grain size and film surface roughness, and performing package level electron migration, ball shear and bond pull tests. A higher process pressure resulted in more uniform films with bigger grains, lower surface roughness, longer reliability lives and higher ball shear values. With optimised process conditions, the aluminium layer uniformity can be maintained at <1·5% throughout the whole target life (∼1000 kWh).

Electrical design of a cost-effective thermal enhanced plastic ball grid array package-NuBGA

An electrically and thermally optimized plastic ball grid array (PBGA) package, called new and useful ball grid array (NuBGA) is presented. NuBGA is a cavity down package with a metal heat spreader covering the entire back-side of the chip. The heat spreader is laminated with a single-core double-sided organic substrate. Super electrical performance is achieved by using the split-wrap-around (SWA) or split-via-connection (SVC) design concepts. All traces on the core substrate are designed into /spl mu/-stripline and co-planar stripline structures. In this paper, the focus is on (1) the unique design concepts; (2) the electrical measurement; (3) the electrical analysis; (4) the electrical performance comparison with other standard packages.