Power Amplifier Module Research Articles

Electronically Tuned Local Oscillators for the NOEMA Interferometer

We present an overview of the electronically tuned local oscillator (LO) system developed at the Institut de RadioAstronomie millimetrique (IRAM) for the superconductor–insulator–superconductor (SIS) receivers of the NOrthern Extended Millimeter Array interferometer (NOEMA). We modified the frequency bands and extended the bandwidths of the LO designs developed by the National Radio Astronomy Observatory (NRAO) for the Atacama Large Millimeter Array (ALMA) project to cover the four NOEMA LO frequency ranges 82–108.3 GHz (Band 1), 138.6–171.3 GHz (Band 2), 207.7–264.4 GHz (Band 3), and 283–365 GHz (Band 4). The NOEMA LO system employs commercially available MMICs and GaAs millimeter MMICs from NRAO which are micro-assembled into active multiplied chain (AMC) and power amplifier (PA) modules. We discuss the problem of the LO spurious harmonics and of the LO signal directly multiplied by the SIS mixers that add extra noise and lead to detections of unwanted spectral lines from higher order sidebands. A waveguide filter in the LO path is used to reduce the higher order harmonics level of the LO at the output of the final frequency multiplier, thus mitigating the undesired effects and improving the system noise temperature.

Low‐loss compact power combiner for solid state power amplifiers with high reliability

In this study, a low-loss and compact planar power combiner for solid state power amplifiers (SSPAs) is proposed. It combines eight power amplifier modules with low insertion loss (IL) and high reliability by utilising a novel magic-Tee configuration and E-plane bend along with a suitable microstrip-to-waveguide transition. The fabricated prototype was implemented through automatic milling machines to produce three planar layers that form the final structure. This novel approach enabled precise fabrication, simple assembly of the SSPAs as well as low-cost manufacturing in comparison with existing traditional approaches. This process is suitable for SSPAs operating from 4 to 40 GHz. The combined IL of the implemented combiner network is less than 0.6 dB at Ka-band, 0.5 dB at Ku-band, and 0.4 dB at X-band while exhibiting a 10% fractional bandwidth.

A WCDMA Multiband Power Amplifier Module With Si-CMOS/GaAs-HBT Hybrid Power-Stage Configuration

This paper describes a newly developed Si/GaAs hybrid multiband power amplifier module (MB-PAM) that supports major quad wideband code division multiple access (WCDMA) bands (Bands 5, 8, 2, and 1) for handset applications. With four dies (two GaAs-HBT dies, one GaAs-HEMT die, and one CMOS die) and several surface-mount devices, the hybrid MB-PAM accommodates two amplifier chains and two single-pole double-throw HEMT band-select switches on a 5 mm $\,\times\, $ 5.5 mm laminate, covering 824–915 and 1850–1980 MHz. Each amplifier chain has two switchable signal paths corresponding to dual (high and low) power modes [high-power mode (HPM) and low-power mode (LPM)] for saving battery current in practical handset use. One of the main features of this MB-PAM is the integration of driver stages, RF switches, and their bias control circuits on the CMOS die for pursuing cost reduction. Only the two output power stages are fabricated in a GaA-HBT process. Measurements conducted under the condition of a 3.4-V supply voltage and a WCDMA (Third Generation Partnership Project Release 99) modulated signal are as follows. Owing to optimized linear design and broadband output matching design, the hybrid MB-PAM achieves a power-added efficiency (PAE) as high as 39%–40% at 28 dBm of output power ( ${ P}_{\rm out}$ ) over 824–915 MHz in the HPM while maintaining a $\pm {\hbox{5-MHz-offset}}$ adjacent channel leakage power ratio (ACLR1) to less than $-{\hbox{39 dBc}}$ . In the LPM, PAE of 15% at a ${ P}_{\rm out}$ of 17 dBm is obtained while ACLR1 of less than $-{\hbox{40 dBc}}$ is maintained. For 1850–1980 MHz, the MB-PAM delivers 35% of PAE with ACLR1 of less than $-{\hbox{40 dBc}}$ at 28 dBm of ${ P}_{\rm out}$ in the HPM and 15% PAE at 17.5 dBm of ${ P}_{\rm out}$ in the LPM.

High-Performance CMOS Power Amplifier With Improved Envelope Tracking Supply Modulator

A differential cascode CMOS power amplifier (PA) with a supply modulator for envelope tracking (ET) has been implemented using 0.18- $\mu {\hbox{m}}$ RF CMOS technology. For maximizing the PA’s performance, the CMOS power cell has been optimized. The CMOS PA employs 2nd harmonic control circuits at the input, source, and output of the PA to improve efficiency and linearity at the same time. The CMOS PA utilizes an improved ET supply modulator, which is suitable for a CMOS PA with high knee voltage. By utilizing this modulator, we achieve not only higher linearity, but also higher efficiency in all power levels. For a long-term evolution signal at 1.70 GHz with a 10-MHz bandwidth and a 16-QAM 7.5-dB peak-to-average power ratio, the CMOS ET PA module achieves a power-added efficiency of 36.6%, an error vector magnitude of 3.0%, and an adjacent channel leakage ratio of $-{\hbox{35.6}}~{\hbox{dBc}}$ at an average output power of 28.5 dBm. The proposed ET operation reduces the total current consumption over the standalone PA, by 10% at the peak power and up to 56% at a low power.

Setting stress conditions that qualify application expectations

This is a demonstration that blends failure mechanism information and application expectations in order to set goals and make predictions that can be used in setting guidelines or requirements for qualification methods, sample sizes, and durations which are relevant to intrinsic and extrinsic reliability. This information is required to fill in the gaps for new types of knowledge-based and application-specific qualification requirements. Instead of generalizing requirements for convenience and uniformity, as with 29year old stress-driven qualification methods, specific information can be used to pinpoint needs for one type of device — assuming failure mechanism, degradation distribution, and acceleration factor information is known and exists in the public domain. For illustration, a Power Amplifier Module is demonstrated. The overall synthesis of proper qualification requirements for this type of semiconductor module will result in efficient stressing to protect customers and allow for the completion of meaningful qualifications efficiently.

Multi-mode multi-band power amplifier module with high low-power efficiency**Project supported by the National Natural Science Foundation of China (No. 61201244).

Increasingly, mobile communications standards require high power efficiency and low currents in the low power mode. This paper proposes a fully-integrated multi-mode and multi-band power amplifier module (PAM) to meet these requirements. A dual-path PAM is designed for high-power mode (HPM), medium-power mode (MPM), and low-power mode (LPM) operations without any series switches for different mode selection. Good performance and significant current saving can be achieved by using an optimized load impedance design for each power mode. The PAM is tapeout with the InGaP/GaAs heterojunction bipolar transistor (HBT) process and the 0.18-μm complementary metal-oxide semiconductor (CMOS) process. The test results show that the PAM achieves a very low quiescent current of 3 mA in LPM. Meanwhile, across the 1.7–2.0 GHz frequency, the PAM performs well. In HPM, the output power is 28 dBm with at least 39.4% PAE and −40 dBc adjacent channel leakage ratio 1 (ACLR1). In MPM, the output power is 17 dBm, with at least 21.3% PAE and −43 dBc ACLR1. In LPM, the output power is 8 dBm, with at least 18.2% PAE and −40 dBc ACLR1.

CMOS Power Amplifier on Top of Embedded Transformer for Compact Module

A small-sized high-performance complementary metal-oxide-semiconductor (CMOS) power amplifier (PA) module is presented. To reduce insertion loss of the output matching network (OMN), an off-chip transformer is designed on a FR-4 printed circuit board (PCB). To minimize the area of the OMN, the transformer is embedded underneath the PA chip. Coupling between the PA and the transformer is minimized so that the performance is not affected. For the 7.5 dB peak-to-average power ratio, 16-QAM long-term evolution signal, the proposed CMOS PA module achieves a power-added efficiency of 38.5% and an adjacent channel leakage ratio level under ${-}31$ dBc at an average output power of 27.5 dBm. The proposed technique can be used in any wireless Tx applications requiring small form-factor and high performance.

RF and Microwave Power Amplifiers assembly – Interaction between materials, design and process on reliability

The demand for data anywhere and at anytime (mobile internet) is putting increasing pressure on network operators in their deployment of wireless communication infrastructure. This has pushed upwards across the supply chain, from suppliers to customers. At the core of the infrastucture are RF power amplifiers (PA) with very costly design, hence important to get it right first time. Thermo-mechanical compliance are key attributes to consistent product performance and reliability amidst stringent mission profiles. Most transistor component manufacturers focus on their core competence – component design. Network operators on the other hand focus on the PA design. In most cases, the assembly of the PA module is an after-thought and a key enabler. These transistors are usually high power devices (> 100 watts), hence demanding excellent thermal management. The packages used have a metal flange in addition to RF/DC leads which are soldered in the PA module. These act as a heat spreader and electrical interconnect which affects the product performance. Since these interconnects are in different planes, assembly requires heatsinks with cavities (flange soldering). The main challenge being tackled in this study is the response of the materials being soldered in a different plane – leads to board and flange to heatsink interface. This is why proper soldering of the transitors (flange & leads) is an essential part in PA assembly due to the impact on module performance & reliability. To achieve the desired thermal and reliability requirements, a variety of factors are critical including the cavity design, solder and reflow soldering process. In this paper, these factors are evaluated via both thermo-mechanical simulations and experimental work. Since there are lots of materials with different properties involved in the assembly, it is vital to evaluate its behavior prior to the actual process evaluation as it has impact on cost and timing effectiveness of the study. These simulations are used as initial indication for trends which are later validated by experimental evaluations. The thermal impedance (Rth) in combination to acoustic microscopy / x-rays is used to assess the soldered flange during assembly & reliability.

Modeling and compensation of transmitter nonlinearity in coherent optical OFDM

We present a comprehensive study of nonlinear distortions from an optical OFDM transmitter. Nonlinearities are introduced by the combination of effects from the digital-to-analog converter (DAC), electrical power amplifier (PA) and optical modulator in the presence of high peak-to-average power ratio (PAPR). We introduce parameters to quantify the transmitter nonlinearity. High input backoff avoids OFDM signal compression from the PA, but incurs high penalties in power efficiency. At low input backoff, common PAPR reduction techniques are not effective in suppressing the PA nonlinear distortion. A bit error distribution investigation shows a technique combining nonlinear predistortion with PAPR mitigation could achieve good power efficiency by allowing low input backoff. We use training symbols to extract the transmitter nonlinear function. We show that piecewise linear interpolation (PLI) leads to an accurate transmitter nonlinearity characterization. We derive a semi-analytical solution for bit error rate (BER) that validates the PLI approximation accurately captures transmitter nonlinearity. The inverse of the PLI estimate of the nonlinear function is used as a predistorter to suppress transmitter nonlinearity. We investigate performance of the proposed scheme by Monte Carlo simulations. Our simulations show that when DAC resolution is more than 4 bits, BER below forward error correction limit of 3.8 × 10(-3) can be achieved by using predistortion with very low input power backoff for electrical PA and optical modulator.

A novel PWM power amplifier of magnetic suspension spindle control system for micro EDM

Considering the traditional power amplifier has the disadvantage of poor reliability and flexibility, a three-level pulse-width modulation (PWM) power amplifier which is based on a novel field-programmable logic gate array (FPGA) algorithm and hardware solution is proposed. The power amplifier can provide various signals flexibly and realize rapid response of the magnetic suspension spindle in micro-electrical discharge machining (EDM). In this paper, the principle of three-level PWM amplifier with half bridge and full bridge power circuit is introduced. According to different functions, the amplifier is divided into four function modules which include PWM signal generator module, voltage signal convert module, bootstrap drive module, and power bridge module. PWM signal generator module is also divided into four sub-modules in term of a new FPGA algorithm. Voltage signals are converted by high-speed photo coupler HCPL-2630. IR2110S chips are applied to drive the half bridge and full bridge power circuits. According to Kirchhoff voltage law, when the period of PWM signals is 50 μs and the duty cycles are larger than 0.76 and 0.665, the average current of half bridge and full bridge are more than 3 and 4 A; however, the ripple of the half bridge and full bridge are still less than 0.25 and 0.2 A, this advantage is suitable for the control system of magnetic suspension spindle. Test results of the average current and ripple are close to theoretical value. The axial response frequency of the spindle can reach 125 Hz, using this power amplifier and the magnetic suspension spindle, micro EDM can be achieved in Z axis with 1.2 mm stroke.

High-Efficiency, High-Temperature Continuous Class-E Sub-Waveform Solution AlGaN/GaN Power Amplifier

This letter presents the realization of a high-efficiency, high-temperature Continuous Class-E Sub-Waveform Solution power amplifier using for the first time GaN technology. The recently introduced Continuous Class-E PA mode theory has revealed new and various impedance solutions for which high efficiency switch mode PAs can be realized. The investigation carried out in this work clearly shows that very high efficiency is still delivered despite the smaller voltage waveform peak when compared to standard Class-E, leading to more reliable PAs. The Continuous Class-E Sub-Waveform Solution PA prototype shows efficiency as high as 80% while delivering output power of 4 W and gain ${>} 10$ dB at 2 GHz of frequency and ambient temperature. The PA module has also been tested at high temperature ${\rm T}=150^{\circ}$ C revealing targeted performance with efficiency up to 71% while delivering 3.5 W of output power. Reliability measurements also show satisfactory results in the time frame up to 1500 hours.

Efficient Wi-Fi Power Amplifier LTCC Module Using a Buck Converter With a Power Inductor Implemented in Ferrite-Filled PCB Technology

This paper presents a power amplifier module (PAM) that operates efficiently in low-power mode for IEEE 802.11g Wi-Fi applications. The PAM consists of a power amplifier (PA), a buck converter, and a power detector. Two packaging technologies were used to integrate the compact module: a low-temperature co-fired ceramic (LTCC) technology and a ferrite-filled printed circuit board (PCB) technology. The LTCC portion includes radio-frequency inductors, capacitors, transmission lines, and interconnection lines to minimize the overall size, while a power inductor for the buck converter is implemented in ferrite-filled PCB. The PA and the buck converter are designed in 2-μm InGaP/GaAs heterojunction bipolar transistor technology and 0.35-μm CMOS technology, respectively. The output power level is converted into a voltage by the power detector, and the voltage controls the buck converter, thereby optimizing the supply voltage of the PA. This adaptive supply voltage helps to improve the power-added efficiency (PAE) in the low-power regime while maintaining linearity. The PAM showed an error vector magnitude of less than 4% up to an output power of 22 dBm. The PAE is 8% and 11% at output powers of 11 and 16 dBm, respectively, representing respective improvements of 60% and 43%. The overall size of the PAM is 5×7.5×1.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> .

A Novel Load Mismatch Detection and Correction Technique for 3G/4G Load Insensitive Power Amplifier Application

This paper proposes a novel load mismatch detection and correction technique to develop a load insensitive power amplifier (PA). The presented algorithm for the technique can simply be implemented by handling load impedance as a region rather than a point. Based on the detection results, a tunable output matching network (TOMN) corrects a mismatched load and transforms it into a desired region, thereby dramatically enhancing PA performances under load mismatched condition with a minimal compromising at a matched load. The detectors and TOMN were simply implemented using a 0.18-μm silicon-on-insulator field-effect transistor, which were integrated with a 2-μm InGaP/GaAs HBT PA monolithic microwave integrated circuit into a single module. A PA module was implemented using more advanced impedance detectors having eight-phase regions, which was measured with WCDMA R'99 and 10-MHz 16QAM long-term evolution signals centered at 1.95 GHz for verification of the proposed idea. When compared to a conventional PA, excellent adjacent channel leakage ratio improvements of 12.7 and 8.3 dB, respectively, were achieved under output voltage standing-wave ratio (VSWR) of 2.5:1 for both applications. Moreover, the idea was extended for efficiency enhancement in a linearity spec-compliant impedance region, and the PA showed power-added efficiency improvements of 1.6% and 0.5%, respectively, under output VSWR of 2.5:1 for both applications.

Investigation of Intermodulation Distortion of Envelope Tracking Power Amplifier for Linearity Improvement

An intermodulation distortion of an envelope tracking (ET) power amplifier (PA) is investigated in this paper. For this purpose, the distortion characteristics are simulated based on the inter-connection model between the PA and supply modulator. For the sweet spot tracking ET operation, the fifth-order distortion is the most important one, which is generated by AM–PM nonlinearity. To reduce the distortion, the phase compensation network (PCN) is proposed. The efficiency of the PA is also improved by a properly designed bias circuit. For demonstration purposes, the PA and supply modulator are implemented using an InGaP/GaAs heterojunction bipolar transistor and a 0.18- $\mu$ m CMOS process, respectively. The ET PA is tested at 1.85 GHz using a long-term-evolution signal with 10-MHz bandwidth, a 7.5-dB peak-to-average power ratio, and 16 quadrature amplitude modulation. The ET PA with the proposed PCN and the bias circuit delivers a power-added efficiency of 44.3%, a gain of 23.4 dB, an evolved universal terrestrial radio access adjacent channel leakage ratio of ${-}{\hbox{38.4}}$ dBc, and an error vector magnitude of 1.8% at an average output power of 27 dBm. The multiband characteristics of the proposed ET PA are measured across 1.7–2.0 GHz. These results are achieved without any digitally supported techniques, indicating that the design approach is a promising technique for handset ET PA applications.

다중대역 RRH를 위한 Class-J 전력증폭기의 광대역과 고효율 특성분석

Until recently, power amplifiers using LDMOS were Class-AB and Doherty type, and showed 55 % efficiency for narrowband of 60 MHz bandwidth. However, owing to the RRH application of base stations power amplifier module, a bandwidth expansion of at least 100 MHz and high efficiency power amplifiers of at least 60 % power efficiency are required. In this study, a Class-J power amplifier was designed by optimizing an output matching circuit so that the second harmonic load will contain a pure reactance element only and have broadband characteristics by using GaN HEMT. The measurements showed that a 45 W Class-J power amplifier with a power added efficiency of 60~75 % was achieved when continuous wave signals were input at 1.6~2.3 GHz, including W-CDMA application.

Design and test of a pulse-width modulator and driver for space-borne GaN switch mode power amplifiers in P-band

In this paper, the design and test of a single-chip RF pulse-width modulator and driver (PWMD) aimed at exciting a high-power class-E GaN high-power stage at 435 MHz is described. For the required buffer size, avoiding potential ringing of the pulses within the buffer structure presents a major challenge in the design process. Therefore, a smaller test chip capable of driving capacitive loads of up to 5 pF was initially designed, fabricated, and tested. An approach based on three-dimensional electromagnetic simulations was used to validate the test results and offers excellent simulation accuracy. Based on the results obtained for test chip an enlarged PWMD chip capable of driving a 40 W high-power stage has been designed and tested on passive loads representing the targeted final stage.

Envelope Tracked Pulse Gate Modulated GaN HEMT Power Amplifier for Wireless Transmitters

This paper proposes a complete transmitter prototype for wireless applications using envelope tracked pulsed gate modulated power amplifier (PA). The proposed transmitter architecture is developed using two high power 10 W gate modulated PAs combined in a fashion to operate as a switched voltage source for the range of duty cycles of pulses driving the gates of power amplifiers. These PAs are designed and implemented using packaged GaN HEMT transistors from CREE to operate at the carrier frequency of 2.35 GHz. For a 5 MHz bandwidth WiMAX 802.16e down-link signal with the PAPR of 7.9 dB and the oversampling ratio of 100, the average drain efficiency of 46.2% is achieved at the average output power of 35.8 dBm. Using a 5 MHz bandwidth LTE down-link signal with 11 dB PAPR and centered at 2.35 GHz, the power amplifier delivers the average output power of 33.2 dBm with the average drain efficiency of 46%. The adjacent channel leakage ratio (ACLR) measured for this signal is less than -36.85 dBc at 10 MHz offset from the center frequency of 2.35 GHz.

0.8-/1.5-GHz-Band WCDMA HBT MMIC Power Amplifiers with an Analog Bias Control Scheme

This paper describes 0.8-/1.5-GHz-band GaAs-HBT power amplifier modules with a newly designed analog bias control scheme. This scheme has two features. One is to achieve approximately linear quiescent current control using not a BiFET process but only the usual HBT process. The other is to help improve linearity under reduced supply voltage and lower quiescent current operation. The following two key techniques are incorporated into the bias scheme. The first is to employ two different kinds of bias circuits: emitter follower bias and current injection bias. The second is the unique current injection bias block, based on the successful combination of an input buffer with an emitter resistance load and a current mirror. These techniques allow quiescent current control that is almost proportional to an externally applied analog control voltage. To confirm the effectiveness of the scheme, 0.8-GHz-band and 1.5-GHz-band power amplifier modules were designed and fabricated using the usual HBT process. Measurements conducted under the conditions of a 3.4V supply voltage and an HSDPA WCDMA modulated signal are as follows. The 0.8-GHz-band amplifier can deliver a 28-dBm output power (Pout), a 28.4-dB power gain (Gp), and 42% PAE while restricting the ACLR to less than -40dBc. For the 1.5-GHz-band amplifier, 28dBm of Pout, 29dB of Gp, and 41% of PAE are obtained with the same ACLR levels. The measurements also confirm that the quiescent current for the second stage in the amplifiers is approximately linearly changed from 14mA to 58mA over a control voltage ranging from 1.1V to 2.2V. In addition, our measured DG.09-based current dissipation with both supply voltage and analog bias controls is as low as 16.9mA, showing that the analog bias control scheme enables an average current reduction of more than 20%, as compared to a conventional supply voltage and two-step quiescent current control.

A 3.5-GHz-Band GaAs HBT Stage-Bypass-Type Step-Gain Amplifier Using Base-Collector Diode Switches and Its Application to a WiMAX HBT MMIC Power Amplifier Module

This paper describes circuit design and measurement results of a newly proposed GaAs-HBT step-gain amplifier configuration and its application to a 3.3-3.6 GHz WiMAX power amplifier module for use in customer premises equipment. The step-gain amplifier implemented using only a usual HBT process is based on a current-mirror-based, base-collector diode switches and a passive attenuator core for the purpose of bypassing a power-gain stage. The stage allows an individual design approach in terms of gain and attenuation levels as well as large operating current reduction in the attenuation state. To confirm the effectiveness of the proposed step-gain amplifier, a prototype of the amplifier was designed and fabricated, and then a WiMAX power amplifier module was also designed and fabricated as an application example of the proposed configuration to an amplifier product. Measurements are as follows. For a 3.5-V power supply and a 3.5-GHz non-modulated signal, the step-gain amplifier delivers 23.7 dBm of 1-dB gain compressed output power and 10.7 dB of linear gain in the amplification state. In the attenuation state, the amplifier exhibits 21 dBm of 1-dB gain expanded input power, -9.7 dB of gain, and 15 mA of current dissipation while keeping the gain stage switched off and maintaining input and output return loss of less than -10 dB at a 3.5-GHz band. The WiMAX amplifier operating with a 5-V supply voltage and a 64-QAM modulated signal is capable of delivering a 28.5-dBm linear output power, a 37-39 dB gain, and 15% of PAE over a wide frequency range from 3.3 to 3.6 GHz in the high-gain state while keeping error vector magnitude as low as 2.5%. This amplifier, which incorporates the proposed step-gain configuration into its interstage, enables a 24-dB gain reduction and a 45-mA large quiescent current reduction in the low-gain state.

Traveling wave 전력 결합기를 이용한 X-대역 전력증폭기 개발에 관한 연구

본 논문은 X대역 고출력증폭기의 전력 결합 손실을 최소화 하기위하여 Al2O3 박막 기판으로 제작한 divider/Combiner 회로를 X-대역의 PAM(Power Amplifier Module)에 적용하여 25W 급 전력증폭기 모듈을 구현하였다. 제작은 MMIC 칩과 수정된 형태의 10way traveling wave divider/Combiner회로를 사용하였으며 제작된 Traveling wave구조의 전력증폭기는 출력전력 45.2dBm, 16dB 이득, PAE 26 % 특성을 얻었으며 IMD3 는 17dBc@44dBm의 특성을 보였다. 본 연구의 divider/Combiner 회로는 다단계 구조의수동 결합기 및 분배기에 사용될 수있으며 협소한 크기의 전력증폭기에 사용될 수 있다. In this study, we have implemented a PAM(Power Amplifier Module) with 25W output power using by cooperate divider/Combiner circuit in X-band to minimize combine loss on a Al2O3 substrate. The PAM(Power Amplifier Module) is consisted of MMIC and 10way traveling wave divider/Combiner with proposed structure what have showed that 45.2dBm output power, 16dB gain, PAE 26 % and 17dBc@44dBm IMD3 characteristics. This combine/divider structure can be used when multistage passive divider and combiner needs. especially, power amplifier with very compact size.