P-type Metal-oxide Semiconductor Transistors Research Articles

Ge Nano-Heteroepitaxy: From Nano-Pillars to Thick Coalesced Layers

Ge co-integration with Si has always attracted a lot of attention. Thanks to its superior electronic properties, Ge can be used as a channel material in p-type Metal Oxide Semiconductor transistors (high hole mobility) or low power devices such as tunnelling field effect transistors (steep sub-threshold swing operation). Furthermore, Ge is a key enabler in numerous optoelectronic devices (light emitters and photo-detectors). The epitaxial growth of Ge on Si is far from being lattice matched, with a 4.2% difference between Si and Ge, making high quality growth difficult, especially for thick layers.Several schemes have been explored in the literature to obtain thick, good crystalline quality Ge layers, such as a low temperature/high temperature approach followed by a cyclic anneal which yielded flat, slightly tensile strained thick Ge layers with threading dislocation densities around 107 cm-2. Other methods based on epitaxial lateral overgrowth, aspect ratio trapping and 3D heteroepitaxy of Ge films on patterned Si substrates have shown promising results thanks to defect blocking against sidewalls or their containment in certain directions. However, some planar defects were still present at the coalescence fronts with those growth methods.Another interesting method is to perform a heteroepitaxy of Ge in nanometer-size Si windows surrounded by SiO2. Lee et al [1] succeeded in obtaining high quality Ge layers using nano-heteroepitaxy but did not go further in the analysis of defects generated with such an approach. In a previous work [2], we were able to obtain smooth, fully strain relaxed Si0.76Ge0.24 layers with heteroepitaxial growth in nanometer-size Si windows surrounded by SiO2. In that case, SiGe epitaxial growth was carried out on a patterned substrate with a regular array of nanometre-size seed pillars, and growth fronts from individual nano-pillars coalesced to form complete 2D layers. However, planar defects such as stacking faults and twins were present in the final layers. In this work, we wanted to test this growth approach for pure Ge and provide an in-depth analysis of any defects generated.An original process flow based on diblock copolymer patterning was thus used to fabricate nanometer-size SiO2 based templates for growth (Figure 1a). The nano-heteroepitaxy of 2D Ge layers on these templates was performed at 90 Torr, using GeH4 as a precursor, and compared to growth on blanket Si.Ge nano-pillar growth was first investigated, with a delayed Ge growth found at 400°C. Nano-pillars obtained after the growth of 35 nm of Ge were not as homogeneous and well-defined as the 20 nm high SiGe nano-pillars in Ref. [3]. Raising the growth temperature to 600°C resulted in a highly selective and uniform process, with homogeneous and well-defined Ge nano-pillars for growth nominally 20 nm thick. The expected nano-pillar coalescence scheme was also observed at this growth temperature [3]. Transmission Electron Microscopy (TEM) imaging of the 20 nm sample grown at 600°C showed facetted Ge nano-pillars, with numerous 90° edge dislocations at the Ge/Si interface as expected given the low critical thickness of Ge on silicon (4 nm, typically) and the 20 nm nano-pillar width (Figure 1b).Ge thick layers were then grown with a low temperature/high temperature strategy on bulk and nano-patterned substrates for a benchmark of the nano-heteroepitaxy approach. Atomic Force Microscopy (AFM) showed micrometric-size holes at the surface for Ge layers grown on nano-patterned substrates. This might be due to an incomplete coalescence of the thick Ge layers, which were by contrast very smooth on bulk Si (Figure 1c). TEM analysis of a 600 nm thick Ge layer grown on Ge nano-pillars suggested that coalescence resulted in planar defects such as twins and stacking faults starting at the oxide walls, as found for SiGe pillars in previous studies, in addition to edge dislocations at the Ge/Si interface. Despite these morphological differences, similar structural properties (in terms of degree of strain relaxation and Full Width at Half Maximum of the Ge spot along the in-plane direction) were inferred from X-Ray Diffraction (XRD) for layers grown on nano-patterned and bulk substrates (Figure 1d).[1] J. Lee et al., J. Cryst. Growth 301–302, 330 (2007).[2] M. Mastari et al., Nanotechnology 29, 275702 (2018).[3] M. Mastari et al., ECS J. Solid State Sci. Technol. 8, 180 (2019). Figure 1

Fabrication and characterization of entirely inkjet-printed polysilicon thin film transistors

In this paper, the fabrication and material innovation involved in the first and only entirely inkjet-printed polysilicon thin film transistors (TFTs) are described. To form TFT layers, five inkjet printing inks were developed with the goal of fabricating TFTs by using purely additive processing without vacuum deposition or conventional lithography. A silicon ink was developed to form both the channels and polysilicon gates, and boron and phosphorus dopant inks were developed for N+ and P+ doping. In addition, a silver nanoparticle (NP) ink was developed to form interconnect traces, and a palladium chloride ink was formulated to create palladium silicide for the ohmic contacts between the source and the drain. The first N-type metal-oxide-semiconductor (MOS) polysilicon TFT was fabricated with a top-gate self-alignment scheme. This exhibited a mobility of approximately 80 cm2 V s−1. Next, P-type MOS transistors as well as complementary MOS devices were also successfully fabricated.

Ultra-High Boron Doping of Si and Ge for Nanoelectronics and Photonics

Si:B or Ge:B layers can used to fabricate devices such as p-type metal oxide semiconductor transistors, photo-detectors, light emitting diodes and so on. We have explored here the in-situ boron-doping of Si and Ge with Si2H6 + B2H6 and Ge2H6 + B2H6. Such chemistries enable Si or Ge epitaxy at temperatures definitely lower than with mainstream precursors such as SiH4 or GeH4. Growth temperatures and pressures in our 200mm Reduced Pressure - Chemical Vapor Deposition tool were 550°C, 20 Torr (Si) and 350°C, 100 Torr (Ge). X-ray Diffraction was used to convert the tensile strain in Si:B or Ge:B layers into substitutional B concentrations, while Secondary Ions Mass Spectrometry gave us the atomic B concentration. As far as Si:B was concerned, a huge growth rate increase (from 9.5 up to 39.8 nm min.-1) was evidenced when adding relatively small amounts of B2H6 to Si2H6. Ultra-high substitutional and atomic boron contents were obtained in those Si:B layers (at most: 2.7x1020 and 1.1x1021 atoms cm-3). For higher B2H6 flows, films became poly-crystalline. A similar growth rate increase (from 5.8 up to 20.8 nm min.-1) and really high substitutional B concentrations (at most: 4.8x1020 atoms cm-3) were otherwise obtained for Ge:B. Such concentrations were several times higher than with conventional chemistries.

Electronically Pure Single-Chirality Semiconducting Single-Walled Carbon Nanotube for Large-Scale Electronic Devices.

Single-walled carbon nanotube (SWCNT) networks deposited from a purple single chirality (6,5) SWCNT aqueous solution were electrically characterized as pure semiconductors based on metal/semiconductor/metal Schottky contacts using both complex instruments and a portable device. Both air-stable PMOS (p-type metal-oxide-semiconductor) and NMOS (n-type metal-oxide-semiconductor, resembling amorphous silicon) thin film transistors were fabricated on (6,5) SWCNT in large scale showing the characteristics of fA off current and ION/IOFF ratio of >1 × 10(8). CMOS (complementary metal-oxide-semiconductor) SWCNT inverter was demonstrated by wire-bonding PMOS (6,5) SWCNT TFT and NMOS (6,5) SWCNT TFT together to achieve the voltage gain as large as 52.

Writing the identity in radio frequency identity tags with focused ion-beam implantation of transistor gates

The soon-to-be-ubiquitous radio frequency identity (RFID) tag consists of a Si chip (less than 1mm2) attached to an antenna on a plastic sheet. Each tag needs to have a unique, electronically readable identity number. Currently, the preferred direction of industry appears to be to fabricate all chips the same, and then program the unique identity into the chip electrically in a permanent or semi-permanent fashion. This may make the tags reusable and permit the identity number to be written by the customer. On the other hand, writing the identity into the chips permanently, during fabrication has advantages; mainly, low cost, less real estate, and less vulnerability to tampering or accidental loss of identity. Permanent programming of the chip is currently done using selective laser cutting of metal connections on the chip, but has not been widely adopted because of cost and reliability. We propose an alternate method whereby transistors are substituted for the metal links and selectively focused-ion-beam (FIB) implanted to permanently turn some of them off. Moreover, we have demonstrated that a low ion dose (∼1012∕cm2) is sufficient, so that the throughput is calculated to be practical. For post-fabrication implantation, the region above the transistor channel must be thinned to 100to200nm to use reasonable ion energies. (Of course, in-process implantation is also an option before the passivation layer is applied.) We have used n-type metal oxide semiconductor (NMOS) and p-type metal oxide semiconductor (PMOS) test transistors fabricated at Berkeley and etched away the oxide and part of the poly over the gate. This process did not alter the transistor characteristics. The transistors were implanted with a series of doses and energies using both FIB and broad-beam implantation (Ar, As, and B with broad-beam and Ga, As, and B with FIB). The required dose to turn transistors off is of order 1012∕cm2 as long as the ions have sufficient energy to alter the gate oxide and/or the channel. In PMOS transistors there is a strong shift in threshold voltage as well as a decrease in drain current, while in NMOS the main effect is the latter. Since Ga+ ions work, a robust FIB system can be used to implant the RFID tags. Moreover, neither high resolution nor high placement accuracy are needed. We only need to implant a given transistor without implanting its neighbors. Assuming a 200mm wafer with 30 000 chips, 120 transistors per chip, 2μm2 gate area, and a 100pA beam current results in an implant time of 6min∕wafer. Using a write-on-the-fly scheme the wafer would have to be scanned at 6cm∕s. Since 50μs are needed to implant each transistor, deflection and blanking times should not be limitations.

Selective epitaxial growth of Si and SiGe for metal oxide semiconductor transistors

We have studied in reduced pressure chemical vapor deposition the selective epitaxial growth (SEG) of Si and SiGe using a dichlorosilane+germane+hydrochloric acid chemistry. We have first of all highlighted the specifics of the SEG of Si on patterned wafers with a dichlorosilane+hydrochloric acid chemistry. We have then dealt with the SEG of SiGe, focusing notably on the so-called loading effects (increase of the SiGe growth rate and of the Ge concentration when switching over from a blanket to a dielectric-masked substrate). Finally, we have studied the thermal stability of typical Si/SiGe/Si stacks versus conventional anneals used nowadays for advanced devices in the microelectronics industry. All this knowledge can be used to selectively grow Si or Si/SiGe/Si stacks inside the Si windows of patterned wafers for the formation of raised sources and drains or for the channel engineering of p-type metal oxide semiconductor transistors.

Investigation of active Si pitting and its impact on 0.15 and 0.30 μm n-type metal–oxide–semiconductor and p-type metal–oxide–semiconductor transistors

The causes of pitting on an active silicon surface and its impact on 0.15 and 0.30 μm n-type metal–oxide semiconductor (NMOS) and p-type metal–oxide–semiconductor (PMOS) transistors have been assessed. During polysilicon gate patterning, the gate oxide at the source/drain regions of the NMOS transistors may be etched away due to insufficient selectivity of the etch chemistry, improper etch chamber configuration, pattern density, and the adoption of dual-doped gate technology. The exposed silicon substrate has poor selectivity against the polysilicon gate, this causes Si pitting to occur on the source/drain active regions of the NMOS transistors. However, there is no significant pitting observed for the PMOS transistors due to the slower etch rate of the undoped polysilicon of the PMOS transistors. Pitting on the active areas severely degrades the device parameters, such as drive current, series resistance, and transconductance. This is worse for the 0.15 μm NMOS transistors compared to the 0.30 μm NMOS transistors. The channel resistance of the 0.30 μm transistors is much larger than any increase in the external resistance caused by the pitting. As a result, Si pitting has negligible effects on the device performance of long channel devices.