P-type Guard Ring Research Articles

A Novel DTSCR Structure with High Holding Voltage and Enhanced Current Discharge Capability for 28 nm CMOS Technology ESD Protection.

To cope with the much narrower ESD design window in 28 nm CMOS technology, a novel diode-triggered silicon-controlled rectifier with an extra discharge path (EDP-DTSCR) for ESD protection is proposed in this paper. Compared with the traditional DTSCR, the proposed DTSCR has an enhanced current discharge capability that is achieved by creating a slave SCR path in parallel with the master SCR path. Moreover, the improved triggering and holding characteristic can be obtained by the proposed EDP-DTSCR. By sharing the anode emitter junction, a slave SCR path is constructed that is symmetrical to the position of the master SCR path to add an additional ESD discharge path to the EDP-DTSCR. In this way, the current discharge capability of the entire device is obviously improved. The TCAD simulation result shows that the proposed device has a remarkably lower on-resistance compared with the traditional DTSCR and the DTSCR with p-type guard ring (PGR-DTSCR). In addition, it is structurally optimized to further increase the holding voltage and reduce the trigger voltage to improve the anti-latching capability of the device, which is more conducive to the ESD protection window application of 28 nm CMOS technology.

Novel Symmetrical Dual-Directional SCR With p-Type Guard Ring for High-Voltage ESD Protection

The negative holding voltage of high-voltage (HV) dual-directional silicon-controlled rectifier (DDSCR) is usually attenuated to a very low level due to the grounded guard ring, which has been ignored by many researchers nowadays. In this brief, a novel symmetrical DDSCR (SDDSCR) is proposed to suppress the deterioration of DDSCR's negative holding voltage. By introducing a diffusion resistor into the p-type guard ring (PGR), experimental results indicated that the reverse parasitic SCR path associated with PGR is suppressed effectively. Thus, a symmetric high holding voltage characteristic is implemented for SDDSCR without increasing any silicon footprint. Moreover, the PGR resistor technology presented in this brief can be extended to various existing HV DDSCRs, which could improve their negative holding voltage deteriorated by guard ring.

High-Performance Back-Illuminated Three-Dimensional Stacked Single-Photon Avalanche Diode Implemented in 45-nm CMOS Technology

We present a high-performance back-illuminated three-dimensional stacked single-photon avalanche diode (SPAD), which is implemented in 45-nm CMOS technology for the first time. The SPAD is based on a P+/Deep N-well junction with a circular shape, for which N-well is intentionally excluded to achieve a wide depletion region, thus enabling lower tunneling noise and better timing jitter as well as a higher photon detection efficiency and a wider spectrum. In order to prevent premature edge breakdown, a P-type guard ring is formed at the edge of the junction, and it is optimized to achieve a wider photon-sensitive area. In addition, metal-1 is used as a light reflector to improve the detection efficiency further in backside illumination. With the optimized 3-D stacked 45-nm CMOS technology for back-illuminated image sensors, the proposed SPAD achieves a dark count rate of 55.4 cps/μm2 and a photon detection probability of 31.8% at 600 nm and over 5% in the 420–920 nm wavelength range. The jitter is 107.7 ps full width at half-maximum with negligible exponential diffusion tail at 2.5 V excess bias voltage at room temperature. To the best of our knowledge, these are the best results ever reported for any back-illuminated 3-D stacked SPAD technologies.

A new guard ring for radiation induced noise reduction in photodiodes implemented in 0.18 μm CMOS technology

A new p-type guard ring by introduction of a thin p-type layer which encloses shallow trench isolation (STI) layer is utilized to reduce radiation induced noise in photodiodes implemented in 0.18 $$\upmu$$ m standard complementary-metal-oxide-semiconductor (CMOS) technology. The guard ring efficiency is characterized according to a new radiation model developed for p–n photodiodes implemented in the same technology. The extracted model which is the oxide trapped charges and interface state values is verified using a simulation setup for two different structures. The optimized guard ring with the doping concentration of $$10^{+19}$$ atoms cm $$^{-3}$$ reduces the dark current of photodiodes at 1 Mrad dose of ionizing radiation from $$6.97\,\times \,10^{-13}$$ A (without the guard ring) to $$1.29\,\times \,10^{-14}$$ A for STI in contact with the active region structure and from $$5.95\,\times \,10^{-13}$$ A (without the guard ring) to $$2\,\times \,10^{-14}$$ A for STI surrounded p-well structure. The proposed guard ring can be used as a promising structure for ionizing radiation hardening of photodiodes.

A robust and area-efficient guard ring edge termination technique for 4H-SiC power MOSFETs

A robust and area efficient adjusted multi-section guard rings (AMS) edge termination structure is employed to a 4H-SiC power MOSFET device rated at 1.7kV and fabricated without extra process steps or masks in this paper. The lightly doped p-type guard ring with adjusted multi-section spacing, which is similar with varied lateral doping technology widely used in silicon edge termination, creates a smoother and more uniform surface electric field distribution across all rings, resulting in a higher reverse blocking voltage with minimal edge termination area. The fabricated AMS-MOSFET devices with an active area of 2.5mm2 have reverse blocking voltage up to 2.5kV at room temperature. Compared to the conventional SiC MOSFETs with the uniform ring spacing, the AMS-MOSFET with the same edge termination area shows more than a 25% increase in the reverse blocking voltage. Furthermore, high-temperature reverse bias stress test is performed to verify junction and termination robustness of the AMS-MOSFET device. A small variation in the reverse blocking voltage and drain-source leakage current are achieved under 168h high-temperature reverse bias stress with the drain bias of 1360V at ambient temperature of 175°C, which suggests an expected robustness in high power application for the fabricated SiC MOSFET with the AMS structure.

Characterization of Si-PIN radiation detector with photon counting mode CMOS readout front-end

An X-ray pixel detector with photon counting technique for digital X-ray imaging was designed and developed. Si detector was fabricated starting from 5 in., FZ-refined, 620 μm-thick, 〈1 1 1〉 oriented, n-typed silicon wafer with high resistivity of 6000–12,000 Ω cm. Readout front-end, which consists of the preamplifier, comparator, and bias circuits including the band-gap reference circuits, was designed and fabricated using 0.25 μm-triple-well CMOS standard process. In detector, the several types of guard-ring structures were tested. The biased p-type guard ring showed more reasonable results in the leakage current and breakdown voltage. The experimental results for the readout chip prove that its functionality is correctly operated up to 100 mV, 2.5 M events/s. In radiation experiment under irradiation of 60Co at dose rate 10 krad/h the measurement indicate that the band gap reference generator (BGR) circuits work up to 240 krad and the maximum variation of output voltage is 0.4% (peak-to-peak) of operational voltage at the range of 0–240 krad. It cannot lead to any critical problem for use in its operation.

Performance comparison of substrate coupling effect between silicon and SOI substrates in RF-CMOS technology

Substrate coupling may severely degrade the electrical performances of high-speed and RF integrated circuits. An isolation technique study of parasitic effects due to substrate coupling between two blocks of integrated circuits in an RF CMOS 90 nm technology is presented. Isolation performances are compared for both bulk silicon (Si) and silicon-on-insulator (SOI) substrate. For every substrate, a compact electrical model matching well with measurement results is proposed for test structures composed of 50×50 µm cells surrounded with an appropriate guard ring. An isolation improvement of 10 dB is reached by an additional P-type guard ring placed around one cell and an isolation level of 45 dB is achieved at 1 GHz for bulk Si substrate.

Design of edge termination for GaN power Schottky diodes

The GaN Schottky diodes capable of operating in the 300–700-V range with low turn-on voltage (0.7 V) and forward conduction currents of at least 10 A at 1.4 V (with corresponding forward current density of 500 A/cm2) are attractive for applications ranging from power distribution in electric/hybrid electric vehicles to power management in spacecraft and geothermal, deep-well drilling telemetry. A key requirement is the need for edge-termination design to prevent premature breakdown because of field crowding at the edge of the depletion region. We describe the simulation of structures incorporating various kinds of edge termination, including dielectric overlap and ion-implanted guard rings. Dielectric overlap using 5-µm termination of 0.1–0.2-µm-thick SiO2 increases the breakdown voltage of quasi-vertical diodes with 3-µm GaN epi thickness by a factor of ∼2.7. The use of even one p-type guard ring produces about the same benefit as the optimized dielectric overlap termination.

Charge storage effects in p-n junction-Schottky barrier hybrid diodes

The influence of metal barrier height and diffusion profile on the charge storage characteristics of p-n junction guard ring or hybrid Schottky barrier diodes is discussed and examined experimentally. It is shown that the use of high barrier height metals, such as gold or platinum silicide on n-type silicon can severely limit high speed device operation at high forward current levels, due to minority carrier injection by the p-n junction. It is further shown that essentially majority carrier operation (i.e., no charge storage effects) can be maintained at high drive levels with the use of lower barrier height metals in combination with properly controlled surface concentration of the diffused p-type guard ring.

Metal-semiconductor impatt diode

Microwave cw oscillation at 8 GHz has been obtained in passivated metal-semiconductor diodes. The diodes were fabricated using the beam-lead process of PtSi on epitaxial n-type Si substrates, including a diffused p-type guard ring. The result indicates that (1) the devices behave similarly as abrupt p- n junctions with the same background dopings, (2) the devices are passivated and can be incorporated into integrated circuits, and (3) the devices can handle high power density. Although the efficiency is low for the preliminary devices, this shortcoming is attributed to a non-optimum doping profile.