p-GaN HEMT Research Articles

Improved p-GaN/AlGaN/GaN HEMTs with magnetronsputtered AlN cap layer

In this paper, a low temperature sputtered AlN cap-layer p-GaN HEMT with high gate breakdown and improved reliability is realized. XPS test shows that the valence band offset of p-GaN and low-temperature magnetron sputtered AlN is 1.2 eV, which successfully suppresses the gate leakage current and greatly improves the gate reliability. Low capacitance–voltage hysteresis and small pulsed threshold voltage shift predict good AlN/p-GaN interface quality. The threshold voltage of the AlN/p-GaN HEMT is improved from 0.61 V to 0.82 V compared to the conventional p-GaN HEMT with tungsten Schottky gate (W/p-GaN HEMT), the DIBL decrease from 34.4 mV/V in W/p-GaN HEMT to 1.1 mV/V in AlN/p-GaN HEMT. The gate forward and reverse leakage is significantly suppressed, and the gate forward breakdown voltage is improved to 17 V. The gate operating range is improved from 7 V to 12 V, and the ID/IG under saturation state is improved from 104 to 107. In addition, a smaller on-resistance of 67.5 Ω·mm was obtained, which is 15.3 % lower than that of the W/p-GaN HEMT, minimizing on-state loss. The gate leakage mechanism of the AlN/p-GaN HEMT is mainly dominated by the PF emission in the medium gate voltage range. Based on this leakage mechanism, the maximum forward VG for a ten-year lifetime was extracted as 6.8 V at room temperature at a failure level of 63.2 % for the AlN/p-GaN HEMT, while this value for W/p-GaN HEMT is 5.4 V. In addition, the AlN cap layer attenuates the depletion region of metal/p-GaN by the gate Schottky metal, which keeps the GaN channel better depleted, thus keeping a higher off-state breakdown voltage. These results demonstrate the good potential of magnetron sputtering AlN as a low-cost, methodologically simple growth method for the commercial use of p-GaN HEMTs.

A fin-gate p-GaN HEMT with high threshold voltage and improved dynamic performance

A novel fin-gate p-GaN (FPG) HEMT is proposed to simultaneously increase threshold voltage (Vth) and improve dynamic performance of the p-GaN HEMT. The fin-gate structure works as a normally-on p-channel MESFET between gate and source by forming a Schottky-type contact on sidewall and a source-connected Ohmic-type contact on top of the fin. Thus, the Vth can change with the shutdown voltage of the p-channel MESFET, which can be modulated by the doping concentration and width of the fin-p-GaN. By optimizing the fin structure, a high positive Vth of 4V is achieved without transconductance and breakdown voltage degradation in this work. It breaks the restriction between Vth and on-resistance for conventional p-GaN HEMT. The dynamic characteristics of the FPG HEMT are investigated by SPICE simulations. Owing to the well-grounded p-GaN through the normally-on MESFET, the recovery process of the dynamic shift in Vth (ΔVth) after on/off-state stress can be accelerated by two orders of magnitude. It means an imperceptible dynamic degradation and a great potential in high frequency application for the FPG HEMT.

Ultra-Low Gate Leakage Current and Enhanced Gate Reliability in p-GaN HEMT With AlN/GaN/AlN Double Barriers Cap Layer

Ultra-Low Gate Leakage Current and Enhanced Gate Reliability in p-GaN HEMT With AlN/GaN/AlN Double Barriers Cap Layer

A Study on the Dynamic Switching Characteristics of p-GaN HEMT Power Devices.

This study employs an innovative dynamic switching test system to investigate the dynamic switching characteristics of three p-GaN HEMT devices. The dynamic switching characteristics are different from the previous research on the dynamic resistance characteristics of GaN devices, and the stability of GaN devices can be analyzed from the perspective of switching characteristics. Based on the theory of dynamic changes in threshold opening voltage and capacitance caused by electrical stress, the mechanism of dynamic switching characteristics of GaN HEMT devices is studied and analyzed in detail. The test results have shown that electrical stress induces trap ionization within the device, resulting in fluctuations in electric potential and ultimately leading to alterations in two critical factors of the dynamic switching characteristics of GaN HEMT devices, the parasitic capacitance and the threshold voltage. The dynamic changes in capacitance before and after electrical stress vary among devices, resulting in different dynamic switching characteristics. The test system is capable of extracting the switching waveform for visual comparison and quantitatively calculating the changes in switching parameters before and after electrical stressing. This test provides a prediction for the drift of switch parameters, offering pre-guidance for the robustness of the optimized application scheme.

Investigation of the forward gate leakage current in pGaN/AlGaN/GaN HEMTs through TCAD simulations

In this study, we examined the gate leakage characteristics of normally off pGaN/AlGaN/GaN HEMTs through a simulation study. The Fowler Nordheim Tunneling (FNT) mechanism mainly contributes to the gate leakage process as indicated by the Technology Computer-Aided Design (TCAD) simulation. However, at low bias, the FNT undercalculates the leakage current since the electric field is low in this region. This extra leakage current component at this low bias region can be attributed to the presence of surface traps. Trap-assisted tunneling current along with the FNT current can explain forward leakage characteristics of the pGaN HEMTs. Our TCAD simulations were matched with the experimental data for five devices from four different research groups to support this claim. Using TCAD simulations, we have been able to analyze several device parameters including the various potential drops inside the gate stack structure. We were able to identify some of the trap levels and compare them to the dominant defects expected to be present in the pGaN cap layer. Furthermore, we studied the effects of different device parameters on the gate leakage process in the pGaN HEMT.

Analysis and simulation of bulk polarization mechanism in p-GaN HEMT with AI component gradient buffer layer

In this paper,bulk polarization mechanism and radiation simulation of the Al component gradient buffer layer (GBL) and constant buffer layer (CBL) of p-GaN HEMT (p-GaN GBL-HEMT and p-GaN CBL-HEMT) are analyzed and studied. It is found that the p-GaN GBL-HEMT can significantly reduce the buffer leakage current. The linear gradient amplitude (the range of linear gradients of Al components vertically in the buffer) of 20%–25% Al components can significantly increase the breakdown voltage (V BK) of the device, up to 1312 V. Simultaneously, although the p-GaN GBL-HEMT reduces the 2DEG concentration, the device still has a specific on-resistance (R ON,sp) and drain saturation current (I DS,sat) equivalent to the p-GaN CBL-HEMT due to the conductivity modulation effect. Its Baliga figure of merit is up to 2.27 GW cm−2. Finally, through the SEE simulation and the bulk polarization mechanism analysis, it is found that the drain transient current (I DS,trans) by the identical incident particles in the p-GaN GBL-HEMT is lower than that in the p-GaN CBL-HEMT, and the I DS,trans decreases with the increase of the Al components gradient amplitude. Therefore, the p-GaN GBL-HEMT provides a new idea for improving the electrical performance and SEE hardening.

Evaluation of p-GaN HEMTs degradation under high temperatures forward and reverse gate bias stress

In this study, the degradation behavior and physical mechanism of the p-GaN HEMT devices under high-temperature gate bias (HTGB) with +5 V and −5 V were investigated. The DC characteristics show that the device after forward HTGB stress exhibits an obvious negative threshold voltage (Vth ) shift, while the device after reverse HTGB exhibits a negligible shift. The following explanations could be given for the deterioration mechanism: a portion of the two-dimensional hole gas (2DHG) accumulated in the p-GaN layer at the p-GaN/AlGaN interface under long-term forward bias may fill the trap in the AlGaN layer through the tunneling effect. In addition, the drain-source on-resistance of the device had increased after +5 V HTGB stress, and a distinct decrease of accumulated capacitance was observed in the Cg -Vg curve. It indicates a degradation of the gate quality of the device after applying a forward-biased HTGB stress.

Over-voltage and cross-conduction hard switching stress on schottky gate-type p-GaN HEMT in half-bridge operation. Experimental and physical approaches

The GaN HEMT power device emerges as a promising wide-bandgap component for obtaining ultra-compact and very high efficiency power converters. Nevertheless, its long-time switching operation capability in high overload regimes near or just above its maximum ratings remains unknown. The physical degradation mechanisms specific to GaN HEMT as well as the associated electrical signatures must now be established and better understood. In this article a stress protocol is proposed combining or not functional drain-source over-voltage switching and transient low dead-time cross-conduction stresses. A no-loaded Half Bridge (HB) is used. All stress parameters studied have been associated to electric changes such as drain-source, gate-source leakage currents, and threshold voltage drifts of intrinsic values and even some physical degradation by LIT compound analysis. After analysis, it appears that both the electric field and the current are very stressful for the devices and lead to current leakage caused by physical degradation. The aging observed might be generated from the injection of hot electrons and located depending upon the drain voltage value which influences the depletion region and thus the electric field peak.

Total Ionizing Dose Effects on the Threshold Voltage of GaN Cascode Devices.

GaN devices are nowadays attracting global attention due to their outstanding performance in high voltage, high frequency, and anti-radiation ability. Research on total ionizing dose and annealing effects on E-mode GaN Cascode devices has been carried out. The Cascode device consists of a low-voltage MOSFET and a high-voltage depletion-mode GaN MISHEMT. Cascode devices of both conventional processed MOSFET and radiation-hardened MOSFET devices are fabricated to observe the TID effects. Experiment results indicate that, for the Cascode device with conventional processed MOSFET, the VTH shifts to negative values at 100 krad(Si). For the Cascode device with radiation-hardened MOSFET, the VTH shifts by -0.5 V at 100 krad(Si), while shifts to negative values are 500 krad(Si). The annealing process, after the TID experiment, shows that it can release trapped charges and help VTH recover. On one hand, the VTH shift and recover trends are similar to those of a single MOSFET device, suggesting that the MOSFET is the vulnerable part in the Cascode which determines the anti-TID ability of the device. On the other hand, the VTH shift amount of the Cascode device is much larger than that of a previously reported p-GaN HEMT device, indicating that GaN material shows a better anti-TID ability than Si.

Abnormal on Current Tendency in Saturation Region Between High and Light Carbon Doped Buffer Layer in p-GaN HEMT

To reduce drain leakage current, carbon doping is introduced in the GaN layer of the p-GaN HEMT device. The focus of this study is on the discussion of the abnormal current behavior that occurs in the saturation region of carbon-doped p-GaN HEMT. This abnormal phenomenon disappears when the device is heated up to 150°C. The abnormal current behavior corresponds to the hot electron stress (HES) result, which indicates that electron trapping causes this abnormal current behavior. An energy band is proposed to describe the lesser trapping effect that occurs in the saturation region.

Threshold voltage shift model for p-GaN gate enhancement mode HEMT

In this paper, we based on the gate structure of p-GaN HEMT connected with Schottky diode and PIN diode and analyzed the threshold voltage shift mechanism under the influence of gate voltage. Based on the carrier transport mechanism, the electron injection current and hole injection current of the p-GaN layer is discussed and calculated, while the gate current model and threshold voltage shift model of the p-GaN HEMT are analyzed. The accuracy of the model is verified by comparing with the experimental data. The effects of p-GaN doping concentration, AlGaN barrier layer thickness and Al component on the gate current and VTH shift are discussed based on the model. By optimizing the device structure and process parameters, the gate current of HEMT can be reduced and the stability of VTH can be improved.

Resonant driving scheme for p-doped gallium nitride high electron mobility transistor to reduce driving power loss

In high-frequency power electronics applications, gallium nitride high electron mobility transistors (GaN HEMTs) can switch at frequencies of several megahertz. In this case, the driving loss of transistors becomes one of the important reasons that affect the entire conversion efficiency of the system. p-doped GaN (p-GaN) as a new GaN HEMT structure has achieved commercial success in recent years, but due to its special structure, traditional resonant driving schemes designed for Si-MOSFETs have poor applicability to p-GaN HEMTs. Therefore, according to the structure characteristics and the driving requirements of p-GaN HEMTs, an improved resonant driving scheme is proposed. In the proposed driving scheme, the gate charge energy is recycled to the resonant capacitor when the p-GaN HEMT is turned off, and released when it is turned on, thus reducing the driving power loss. The working principle of the driving circuit and the design method of component parameters are given in this paper. The experimental results show that for high-frequency applications with switching frequencies exceeding several megahertz, the power loss of the proposed resonant driving scheme is significantly lower than that of non-resonant driving scheme, which verifies the effectiveness and feasibility of the proposed scheme.

Preconditioning of p-GaN power HEMT for reproducible Vth measurements

In reliability studies, the instability of the threshold voltage (Vth) is problematic when Vth is used as an indicator as it totally blurs an eventual drift due to real device aging. This instability is observed during electric characterization measurements and is related to the “biasing history” of the transistor which can introduce carrier trapping/detrapping in different layers of the structure. New methods are therefore required to overcome this trapping related instability issues in order to accurately monitor device aging. To solve the repeatability issue of threshold voltage measurement, we investigated its instability on GaN transistors. A preconditioning step applied right before the actual Vth measurement was studied. The proposed preconditioning method is based on the application of a dedicated VGS (t) biasing on the gate terminal which leads to a stable and repeatable value of Vth. The mechanisms enabling the observed stability of Vth are identified through the analysis of the drain leakage measurement after the preconditioned Vth measurement. It demonstrates the role of hole injection into the structure. The preconditioned-Vth measurement method is proposed as a complementary measurement to correctly follow the aging of pGaN HEMT in future reliability studies.

Double-Phase Adaptive Neural Network for Condition-Based Monitoring of p-GaN HEMT Under Repetitive Short-Circuit Stresses

Double-Phase Adaptive Neural Network for Condition-Based Monitoring of p-GaN HEMT Under Repetitive Short-Circuit Stresses

Optimizing breakdown voltage and on-state resistance by modulating the barrier height along 2DEG channel for power p-GaN HEMTs

This article proposes a novel step-type gate p-GaN HEMT (STG-HEMT) to optimize breakdown voltage (BV) and on-state resistance (R ON) by modulating the barrier height along the two-dimensional electron gas (2DEG) channel. The step-type gate consists of thicker and thinner p-GaN layers. At off-state, the barrier height is higher due to the clamping potential effect induced by the thinner p-GaN layer, which contributes to improving BV. At on-state, the barrier height under the thinner p-GaN layer is lower, which contributes to improving 2DEG density under the gate (namely reducing R ON). Verified by the calibrated simulation, the results show STG-HEMT’s BV is increased by 55% and STG-HEMT’s R ON is decreased by 20% compared with the conventional power p-GaN HEMT (C-HEMT). At transient behavior, the total switching loss keeps nearly unchanged, while the gate driver loss is increased by about 19%. Furthermore, the impact of the gate length and p-GaN layer’s parameters (including thickness, length, activated Mg doping density) on R ON, BV, and threshold voltage are discussed.

Unclamped-Inductive-Switching Behaviors of p-GaN HEMTs at Cryogenic Temperature

In this letter, the unclamped-inductive-switching (UIS) behaviors of GaN-based high-electron-mobility transistors with p-type GaN gate (p-GaN HEMTs) at cryogenic temperature (CT) are first revealed. Unlike the temperature-dependent avalanche-induced failure for SiC devices during UIS process, the withstanding behaviors and final critical breakdown voltage of p-GaN HEMT during UIS process at CT are completely consistent with the results at room temperature. As proved, the resonant circuit formed by device output capacitance and load inductor is the key factor influencing UIS waveforms, and such state is temperature insensitive. Furthermore, the inverse-piezoelectric effect induced by high electric field during UIS process is demonstrated to be the original cause that makes this temperature-independent failure phenomenon. In conclusion, the UIS withstanding capability of p-GaN HEMT will not be degraded in such an extremely low temperature scene, indicating a superiority of p-GaN HEMT for special applications compared with traditional devices.

Demonstration of Schottky barrier diode integrated in 200 V power p-GaN HEMTs technology with robust stability

Development of integration of different components with GaN-based technologies has been gaining traction in recently. Among these, diodes play important roles in GaN power ICs. For this work, a fabrication approach for integrating a Schottky barrier diode (SBD) with a p-GaN enhancement (E-mode) for 200 V switching application is demonstrated. The integrated SBD with 30-mm width shows a low forward voltage (Vf) with more than 10A and 6A at Vac = 3 V at 25 °C and 150 °C, respectively. Additionally, the devices show a stable ON-resistance (RON) (<20% increase) up to 200 V at 25 °C/150 °C under pulsed IV characterization and OFF-state stress, pointing out the robust stability for integrated GET-SBDs on a power p-GaN HEMT platform.

Hole Injection Effect and Dynamic Characteristic Analysis of Normally Off p-GaN HEMT with AlGaN Cap Layer on Low-Resistivity SiC Substrate.

A p-GaN HEMT with an AlGaN cap layer was grown on a low resistance SiC substrate. The AlGaN cap layer had a wide band gap which can effectively suppress hole injection and improve gate reliability. In addition, we selected a 0° angle and low resistance SiC substrate which not only substantially reduced the number of lattice dislocation defects caused by the heterogeneous junction but also greatly reduced the overall cost. The device exhibited a favorable gate voltage swing of 18.5 V (@IGS = 1 mA/mm) and an off-state breakdown voltage of 763 V. The device dynamic characteristics and hole injection behavior were analyzed using a pulse measurement system, and Ron was found to increase and VTH to shift under the gate lag effect.

A Π-shaped p-GaN HEMT for reliable enhancement mode operation

This paper presents a TCAD based investigation of virtually fabricated Π-shaped Gate p-GaN HEMT for reliable enhancement mode operation. A detailed comparison with the Conventional T-Gate counterpart, with a focus towards the trap related dispersive effect reveals the superiority of Π-shaped Gates P-GaN HEMT for suppressing both the vertical substrate and gate leakage currents, thereby enhancing the breakdown characteristics of the device. A modification of the electric fields, into a stepped profile, demonstrates effective suppression of the leakage through the surface defects, and spillover into GaN buffer, thereby mitigating the trap related dispersive effects. Dispersive effect of the two devices has also been compared using current Slump Ratio (SR) which is lower for Π-shaped Gate P-GaN HEMT. Further analysis into laterally scaled drain-access regions, demonstrates superiority of Π-shaped Gates in achieving a reliable thermal operation, and applicability of Π-shaped Gate P-GaN HEMT for future RF and High Power applications.

Investigation on the Thermal Characteristics of Enhancement-Mode p-GaN HEMT Device on Si Substrate Using Thermoreflectance Microscopy.

In this paper, thermoreflectance microscopy was used to measure the high spatial resolution temperature distribution of the p-GaN HEMT under high power density. The maximum temperature along the GaN channel was located at the drain-side gate edge region. It was found that the thermal resistance (Rth) of the p-GaN HEMT device increased with the increase of channel temperature. The Rth dependence on the temperature was well approximated by a function of Rth~Ta (a = 0.2). The three phonon Umklapp scattering, point mass defects and dislocations scattering mechanisms are suggested contributors to the heat transfer process for the p-GaN HEMT. The impact of bias conditions and gate length on the thermal characteristics of the device was investigated. The behaviour of temperature increasing in the time domain with 50 µs pulse width and different drain bias voltage was analysed. Finally, a field plate structure was demonstrated for improving the device thermal performance.