p-GaN Gate High-electron-mobility Transistors Research Articles

Monolithic fully-controlled HEMT bidirectional power switch with merged Schottky barrier diodes and p-GaN gate transistors for ultra-low turn-on voltage and high threshold voltage

A monolithic fully-controlled high electron mobility transistor (HEMT) bidirectional power switch (FC-HEMT BPS) is studied and implemented for ultra-low turn-on voltage and high threshold voltage. The alternately embedded recess Schottky barrier diodes with p-GaN gate HEMTs in the common active region is a distinctive feature of the proposed device. The FC-HEMT BPS is a sophisticated device with two independent gate controls, capable of operating in four distinct modes. Its flexibility in managing current and voltage in the first and third quadrants makes it versatile for a range of applications in power electronics. The proposed device offers notable advantages over conventional counterparts, including reduced turn-on voltage V ON-D of ∼0.4 V in diode modes and the elimination of turn-on voltage V ON-B (i.e. 0 V) in bidirectional conduction mode. These features make it a promising solution for efficient power electronics applications.

Incorporation of total ionizing dose effects into a compact model for p-GaN gate high electron mobility transistors

Total ionizing dose (TID) characteristics of p-GaN gate high electron mobility transistors (HEMTs) under different bias conditions are explored in this work. Potential mechanism accounting for the TID response of p-GaN gate HEMTs is analyzed, based on which a TID effects model is developed. The TID effects model describes the relationship among threshold voltage of p-GaN gate HEMTs, total radiation dose, and electric field inside the p-GaN cap layer. Furthermore, an approach incorporating the TID effects model into Advanced Spice Model for HEMT (ASM-HEMT) is proposed, the reliability of which is validated by the well-fitted modeled results in comparison with the measured ones. This approach makes it possible to probe into the impact of TID effects on p-GaN gate HEMTs from the perspective of circuit level, which provides a basis for the follow-up GaN-based circuit design.

Challenges and advancements in p-GaN gate based high electron mobility transistors (HEMTs) on silicon substrates

This review highlights the challenges and advancements in p-GaN gate HEMTs on silicon substrates. It also discusses several attempts to enhance device performance and explores the future developments of p-GaN gate HEMT.

Review on Main Gate Characteristics of P-Type GaN Gate High-Electron-Mobility Transistors.

As wide bandgap semiconductors, gallium nitride (GaN) lateral high-electron-mobility transistors (HEMTs) possess high breakdown voltage, low resistance and high frequency performance. PGaN gate HEMTs are promising candidates for high-voltage, high-power applications due to the normally off operation and robust gate reliability. However, the threshold and gate-breakdown voltages are relatively low compared with Si-based and SiC-based power MOSFETs. The epitaxial layers and device structures were optimized to enhance the main characteristics of pGaN HEMTs. In this work, various methods to improve threshold and gate-breakdown voltages are presented, such as the top-layer optimization of the pGaN cap, hole-concentration enhancement, the low-work-function gate electrode, and the MIS-type pGaN gate. The discussion of the main gate characteristic enhancement of p-type GaN gate HEMTs would accelerate the development of GaN power electronics to some extent.

High-performance normally off AlGaN/GaN high electron mobility transistor with p-type h-BN cap layer

Normally off AlGaN/GaN high electron mobility transistors (HEMTs) with p-type gates are attracting increasing attention due to their high safety and low power loss in the field of power switching. In this work, to solve the Mg difficult activating problem of the conventional p-GaN gate AlGaN/GaN HEMTs, we propose an advanced design for the normally off AlGaN/GaN HEMT with a p-type hexagonal boron nitride (h-BN) gate cap layer to effectively manipulate the channel transport of the device. The simulation results demonstrate that the p-hBN gate cap HEMTs yield superior performance over conventional p-GaN gate HEMTs in terms of output current and breakdown voltage, which can be attributed to the deeper potential well formation at the AlGaN/GaN interface and more accumulation of holes located at the p-hBN/AlGaN interface. Moreover, we investigate the effect of bandgap variation on device performance, taking into account that the exact bandgap of h-BN remains under debate. Herein, valuable insights into h-BN cap-gate E-mode AlGaN/GaN HEMT devices are provided, which could serve as a useful reference for the future development of robust III-nitride material power electronic devices.

Breakdown enhancement and hot electrons mitigation for p-GaN gate HEMTs by electric field modulation

In this article, an enhancement mode (E-mode) p-GaN gate AlGaN/GaN high electron mobility transistor (HEMT) with the novel strain technology (NST) has been proposed. The NST consists of GaN/AlGaN/GaN and AlN/AlGaN/GaN heterojunctions laterally from the gate to drain side. By utilizing the different polarization effect of these two heterojunctions, it laterally forms different density of two-dimensional electron gas (2DEG). Accordingly, it decreases the electric field around the gate and introduces an extra electric field peak far away from the gate edge to improve the breakdown voltage (BV) effectively. The experimental BV of the proposed NST-HEMT is increased by 52 % to 1185 V from 780 V of the conventional HEMT. Meanwhile, the output current of NST-HEMT is almost consistent with the conventional HEMT. Moreover, the NST-HEMT realizes better hot electrons mitigation than conventional HMET, and its Vth and Ron degradations are only 1.38 % and 10.72 % after 8 h stress time.

Evaluation of Trapping Behaviors in Forward Biased Schottky-Type p-GaN Gate HEMTs

In this work, we investigated the trapping behaviors in the Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) under positive gate bias using the current-transient method. By excluding the trapping effect introduced by the measurement voltages, the actual recovery curves of drain transient current under different gate filling voltages and temperatures were extracted. The impacts of electron trapping, hole injection, and electron–hole recombination on the threshold voltage instability can be effectively distinguished according to the results of drain current variations under different gate stresses. In addition, the dynamic drain leakage current was monitored to confirm the electron–hole recombination and optical pumping of trapped electrons. The properties of three electron traps can be obtained based on the time constant spectrum (TCS), and a database of the gate-trapping behaviors in the GaN-based devices was constructed. The combined results may provide a basis for a better understanding of the threshold voltage instability under positive gate stress in the p-GaN gate HEMTs.

Revealing the Mechanism of the Bias Temperature Instability Effect of p-GaN Gate HEMTs by Time-Dependent Gate Breakdown Stress and Fast Sweeping Characterization.

The bias temperature instability (BTI) effect of p-GaN gate high-electron-mobility transistors (HEMTs) is a serious problem for reliability. To uncover the essential cause of this effect, in this paper, we precisely monitored the shifting process of the threshold voltage (VTH) of HEMTs under BTI stress by fast sweeping characterizations. The HEMTs without time-dependent gate breakdown (TDGB) stress featured a high VTH shift of 0.62 V. In contrast, the HEMT that underwent 424 s of TDGB stress clearly saw a limited VTH shift of 0.16 V. The mechanism is that the TDGB stress can induce a Schottky barrier lowering effect on the metal/p-GaN junction, thus boosting the hole injection from the gate metal to the p-GaN layer. This hole injection eventually improves the VTH stability by replenishing the holes lost under BTI stress. It is the first time that we experimentally proved that the BTI effect of p-GaN gate HEMTs was directly dominated by the gate Schottky barrier that impeded the hole supply to the p-GaN layer.

Investigation of the Gate Degradation Induced by Forward Gate Voltage Stress in p-GaN Gate High Electron Mobility Transistors.

In this work, we investigated the degradation of the p-GaN gate stack induced by the forward gate voltage stress in normally off AlGaN/GaN high electron mobility transistors (HEMTs) with Schottky-type p-GaN gate. The gate stack degradations of p-GaN gate HEMTs were investigated by performing the gate step voltage stress and the gate constant voltage stress measurements. In the gate step voltage stress test, the positive and negative shifts of threshold voltage (VTH) depended on the range of the gate stress voltage (VG.stress) at room temperature. However, the positive shift of VTH in the small gate stress voltage was not observed at 75 and 100 °C and the negative shift of VTH was started from a lower gate voltage at a high temperature compared to room temperature. In the gate constant voltage stress test, the gate leakage current increased with three steps in the off-state current characteristics as the degradation progressed. To investigate the detailed breakdown mechanism, we measured the two terminal currents (IGD and IGS) before and after the stress test. The difference between the gate-source current and the gate-drain current in the reverse gate bias indicated that the increase of the leakage current was attributed to the degradation between the gate and the source while the drain side was not affected.

Recent Developments and Prospects of Fully Recessed MIS Gate Structures for GaN on Si Power Transistors

For high electron mobility transistors (HEMTs) power transistors based on AlGaN/GaN heterojunction, p-GaN gate has been the gate topology commonly used to deplete the two dimensional electron gas (2-DEG) and achieve a normally-OFF behavior. But fully recessed MIS gate GaN power transistors or MOSc-HEMTs have gained interest as normally-OFF HEMTs thanks to the wider voltage swing and reduced gate leakage current when compared to p-GaN gate HEMTs. However the mandatory AlGaN barrier etching to deplete the 2-DEG combined with the nature of the dielectric/GaN interface generates etching-related defects, traps, and roughness. As a consequence, the threshold voltage (VTH) can be unstable, and the electron mobility is reduced, which presents a challenge for the integration of a fully recessed MIS gate. Recent developments have been studied to solve this challenge. In this paper, we discuss developments in gate recess with low impact etching and atomic layer etching (ALE) alongside surface treatments such as wet cleaning, thermal or plasma treatment, all in the scope of having a surface close to pristine. Finally, different interfacial layers, such as AlN, and alternative dielectrics investigated to optimize the dielectric/GaN interface are presented.

Investigation of trapping effects in Schottky lightly doped P-GaN gate stack under γ-ray irradiation

In this Letter, trapping effects of a Schottky lightly Mg-doped p-GaN gate stack for low-power applications have been investigated, and further analysis focusing on AlGaN/GaN interface traps under γ-ray irradiation has been carried out. A negligible shift in the flatband voltage with γ-ray irradiation dose up to 800 krad indicates the superior radiation tolerance of the p-GaN gate structure. The difference between capacitance dispersion at the measurement frequency below and above 500 kHz is observed, which is attributed to trapping effects in different locations with varying gate voltage. Moreover, the frequency-dependent conductance method is put forward to assess the effects of different doses of γ-ray irradiation on the AlGaN/GaN interface traps. Based on that method, aside from the shallow trap states [the trap activation energy (ET) is about 0.334–0.338 eV] previously found in the traditional normally on high electron mobility transistor (HEMT), another type of deeper trap states at the AlGaN/GaN interface (ET is about 0.467–0.485 eV) is detected. It is observed that the ET of shallow trap states distributes at a deeper and broader range as the irradiation dose increases. Additionally, the trap density decreased after 600 krad doses irradiation but increased after 800 krad doses irradiation for both deep and shallow ET. Transmission electron microscopy and atomic force microscopy are used to demonstrate the smooth AlGaN/GaN interface morphology, which will not be greatly damaged after 800 krad doses of γ-ray irradiation. This work can provide a further understanding of radiation tolerance and trapping effects of p-GaN gate HEMTs for low-voltage applications.

Extraction of Dynamic Threshold Voltage in Resistive Load Hard Switching Operation of Schottky-Type p-GaN Gate HEMT

Threshold voltage (VTh) drift of Schottky-type p-GaN gate high-electron mobility transistor (HEMT) was analyzed under high-voltage and hard switching conditions with a resistive load (R-Load). To overcome the distortion in the drain current (ID) – gate voltage (VG) curve caused by the internal drain capacitance (IDisp) charging current during the switching transients, a method is presented to accurately measure dynamic VTh through appropriate correction of IDisp. The dynamic variation of VTh was tracked with a gate-drive rise/fall times of 200 ns. During the switching operation, VTh increases rapidly at the beginning and then saturates at a stable value. This is attributed to the gate forward current during turn-on that increases the hole depletion of the p-GaN gate through the AlGaN barrier. The dynamic VTh increases linearly at a rate of 40% with the increase of gate turn-on voltage. VTh is independent of duty cycle but minorly increases with frequency at high voltages, suggesting that channel hot electrons be injected into the AlGaN barrier and p-GaN.

Identification of Traps in p-GaN Gate HEMTs During OFF-State Stress by Current Transient Method

In this work, the current transient method was conducted for trap analysis in the p-GaN gate high-electron-mobility transistors (HEMTs) in the OFF-state. Based on the traditional detrapping transient measurements, the pure recovery transients can be isolated by subtracting the undetected part caused by the measurement conditions. A comparison of the measured and actual recovery transients under different drain filling voltages was presented. It suggested that this method can be effective to analyze the unregular transient curves and distinguish the charge trapping type preliminarily. In addition, three traps were identified based on the time constant spectra and the hidden absolute amplitudes of traps can be corrected using the differential amplitude spectra. The information of trap levels in the buffer layer and AlGaN barrier layer was revealed, consisting of three electron traps with energy levels of 0.313, 0.265, and 0.467 eV. The identification of the traps may provide a physical foundation for better understanding of the drain-induced trapping effect during the OFF-state in p-GaN HEMTs.

High-Performance Normally-Off Operation p-GaN Gate HEMT on Free-Standing GaN Substrate

A normally- OFF AlGaN/GaN high-electron-mobility transistor (HEMT) with p-GaN gate was fabricated on free-standing GaN substrate. The self-terminated etching technology was achieved by combining with AlN stop layer and SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> -based etching gas. Compared with HEMT on Si substrate (Si-HEMT), the HEMT on GaN substrate (GaN-HEMT) demonstrated the higher current density, lower subthreshold swing (SS), lower drain leakage current, and lower static and dynamic ON-resistance that were ascribed to the lower dislocation and less defect on free-standing GaN substrate. Meanwhile, the excellent <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\mathrm{th}}$ </tex-math></inline-formula> stability up to 175 °C and uniformity was demonstrated. Also, higher breakdown voltage (BV) of 683 V was measured, which was higher than 507 V for Si-HEMT. Hence, a normally- OFF AlGaN/GaN HEMT on free-standing GaN substrate shows good potential in power application.

High Voltage Normally-Off p-GaN Gate HEMT with the Compatible High Threshold and Drain Current

In this paper, we demonstrate a high voltage normally-off p-GaN gate high-electron-mobility-transistor (HEMT) to realize the compatible high threshold voltage (V TH) and high drain current (I D) performance. With the optimization of the epitaxial structure, the presented device shows a significantly improved V TH. Meanwhile, by using the high-quality ALD-Al2O3 passivation layer, the high I D is also realized in the device because of the access region resistance reduction. Supported by the device fabrication, the p-GaN gate HEMT delivers a V TH = 3.2 V measured by linear extrapolation, a relatively large saturation I D (I D_SAT) of 246 mA mm−1, and a high breakdown voltage (BV) of 1830 V at 1 mA mm−1. Among various p-GaN gate HEMTs with the I D_SAT over 200 mA mm−1, the fabricated p-GaN gate HEMT has a competitive V TH. The results suggest that the proposed device could be a promising candidate in high V TH and I D power electronics.

Influence of Mg doping level at the initial growth stage on the gate reliability of p-GaN gate HEMTs

This letter has studied the gate reliability of p-GaN high electron mobility transistors (HEMTs) influenced by the Mg doping level at the initial growth stage of p-GaN layer. Normally-off HEMTs with p-GaN gate fabricated with relatively low and high Mg doping concentration have been analyzed and compared based on their performances at various statuses of as-fabricated, forward step-stressed, reverse step-stressed and long-term reverse stressed. It reveals that Mg over-doping has a detrimental effect on the p-GaN gate reliability through degrading the PIN diode formed by p-GaN/AlGaN/GaN structure. Severe drain current reduction, threshold voltage instability and gate leakage increase have been observed after being negatively stressed due to the high-density defects acting as apparent acceptor-like traps induced by Mg over-doping. The detailed studies on the p-GaN gate performance with various Mg concentrations give a greater depth of understanding to realize high gate reliability of p-GaN gate HEMTs.

Charge Control in Schottky-Type p-GaN Gate HEMTs With Partially and Fully Depleted p-GaN Conditions

The Schotty-type p-GaN gate high-electron-mobility transistors (HEMT) feature a unique gate structure. A comprehensive understanding of the charge control mechanism in the p-GaN gate region is a fundamental step for the optimization of this technology. In this work, a physics-based analytical model is presented which takes into consideration all the capacitive effects from gate metal deep into the GaN buffer. According to our analysis, the p-GaN layer can be either partially depleted by the metal/p-GaN Schottky junction or fully depleted, depending on the doping concentration and thickness of the p-GaN layer. Our model accurately captures the charge control properties under both conditions and is validated against TCAD numerical simulations. For a certain p-GaN thickness, a lightly doped p-GaN leads to a full-depletion condition, such that the acceptor concentration directly affects the band diagram at AlGaN/GaN interface. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> of the HEMT increases quickly with acceptor concentration in p-GaN. With sufficiently high acceptor concentration in p-GaN, the device reaches the partial-depletion condition, the acceptor concentration loses its influence over the band diagram at the location of the AlGaN/GaN interface, since the Fermi-level at the AlGaN surface is pinned near the valence band of p-GaN. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> starts to decrease with acceptor concentration, but at a relatively slow rate. The maximum <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> is obtained near the boundary between partial-and full-depletion conditions. In consideration of the process margin, the device designed with a partially depleted p-GaN is preferable, since it ameliorated the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> sensibility against acceptor concentration.

N2O plasma treatment effect on reliability of p-GaN gate AlGaN/GaN HEMTs

This work investigates the effect of N2O plasma treatment on the reliability of p-GaN gate AlGaN/GaN high-electron-mobility transistors (HEMTs), specifically in the AlGaN drift region. The formation of a GaON/AlON compound layer on the AlGaN surface after N2O plasma treatment was confirmed by energy-dispersive x-ray spectroscopy mapping and x-ray photoelectron spectroscopy analysis. When a device is under highly stressed conditions, the compound layer reduces the number of negatively charged interface traps and protects the AlGaN surface by hindering the Ga-out diffusion. The high temperature reverse bias reliability test demonstrated that the N2O plasma treatment enhanced the reliability of p-GaN gate HEMTs by suppressing the degradation of the on-resistance from 18.7% to 9.0%, after being subjected to a high drain bias (VDS = 700 V) at 200 °C for 1000 s.

Gate-geometry dependence of electrical characteristics of p-GaN gate HEMTs

In this Letter, we experimentally investigate the impact of gate geometry on forward operation of Schottky-gate p-GaN high electron mobility transistors (HEMTs). In particular, we analyze devices with changing gate-metal/p-GaN junction area and p-GaN/AlGaN/GaN heterostructure area in the linear regime. These devices exhibit unique threshold voltage and subthreshold swing scaling dependence with gate geometry that is in contrast with classic field-effect transistors. On the other hand, peak transconductance and ON resistance are found to scale classically. We find that these results arise from the fact that with a Schottky contact to the p-GaN layer, under steady-state conditions, the p-GaN layer voltage is set by current continuity across the gate stack. Furthermore, a detailed scaling study of the gate current reveals that current flow across the p-GaN/AlGaN/GaN heterostructure is not uniform—instead, it preferentially flows through the ungated portion of the p-GaN layer. Our study concludes that in Schottky-type p-GaN gate HEMTs, the respective areas of two junctions constitute an additional design degree of freedom to fine-tune device performance.

I–V Characteristics of E-mode GaN-based transistors under gate floating

This study investigates the I–V behaviors of various E-mode GaN-based transistors under gate floating and zero gate bias. The p-GaN gate high electron mobility transistor (HEMTs), gate injection transistors, and Cascode GaN FETs have been adopted and compared. The high off-state drain current is observed under gate floating except for Cascode GaN FETs based on the measured I–V characteristics. The off-state drain current of p-GaN gate HEMT is up to 0.8 mA under gate floating at a drain bias of 6 V, which is about 107 times larger than zero gate bias. The devices will induce false-turn-on and reverse conduction loss during switching under gate floating due to the capacitance charging effect between the drain and the gate electrodes. The mechanism of the capacitance charging effect is discussed using the equivalent circuit of p-GaN gate HEMTs and confirmed by Silvaco TCAD simulation.