P-channel MOSFETs Research Articles

(Invited) Development of CMOS-MEMS Cointegrated Pressure Sensor Using Minimal Fab Process

PVD-TiN metal gate PMOSFETs and CMOS ring oscillators have successfully been fabricated on circular diaphragms using the developed Minimal Fab CMOS-MEMS cointegrated gate-last process, and their electrical characteristics have systematically been investigated by changing applied pressures to the diaphragms. It was found that the drain current variation (dId) in the <110> channel PMOSFETs is larger than that in the <100> channel ones. The origin of dId is the mechanical stress-induced mobility change. It was also confirmed that the oscillation frequency of the fabricated CMOS ring oscillator on a circular diaphragm changes from 372 to 405 kHz at different pressures of -30 and +30 kPa. This result implies that the fabricated CMOS-MEMS cointegrated sensor chip is operated as a pressure sensor. The developed CMOS-MEMS cointegrated pressure sensor is suitable for the application to the battery drive IoT sensor systems because the all CMOS integration of the sensor has a low-power consumption.

On Border Traps in Back-Side-Illuminated CMOS Image Sensor Oxides

CMOS image sensors (CISs) in back-side-illuminated configuration consist of photodiode arrays having metal lines and drive electronics beneath the active region with respect to the device/air interface so that the light reaches the photodiode active region directly. This enhances sensor quantum efficiency but reduces the electrical performance and reliability. The back-side configuration is realized by flipping the wafer upside down, bonding it to a handling wafer, mechanically thinning it, and opening a through-silicon via with a long plasma etch. As a result, gate oxides in back-side CISs show an increased density of donor-like border traps with respect to the conventional front-side-illuminated sensors. In this article, we try to add some information toward the comprehension of the origin and the electrical nature of those traps in back-side gate oxides. To this aim, we performed negative bias temperature instability stress on p-channel MOSFETs during which the traps were filled by holes tunneling from the substrate and then studied the relaxation transients of the drain current after the stress was removed. The characteristic emission times of a few specific levels were obtained at different temperatures. This allowed us to extract values of the trap activation energies, which resulted coherent with hole-capturing ${E}\,^{\prime }$ donor-like centers (trivalent silicon dangling bonds) commonly attributed to ionizing radiation.

Channel-length dependence of the generation of interface states and oxide-trapped charges on drain avalanche hot carrier degradation of HfSiON/SiO2 p-channel MOSFETs with strained Si/SiGe channel

This paper evaluates how channel length L affects the drain avalanche hot carrier degradation (DAHC) degradation mechanism of HfSiON/SiO2 pMOSFETs that have strained Si/SiGe channel. DAHC degradation occurred as L was to reduced < 70 nm, and the amount of degradation increased as L decreased. In the early stage of stress, DAHC degradation increased positively due to generation of negative oxide charges –Qox, but gradually-generated interface states Nit neutralize –Qox, so a transition point occurs and eventually DAHC increases negatively after sufficient stress time ts. The distribution of DAHC degradation was also analyzed after ts = 4000, 40000 s. The effects of additional generation of –Qox and Nit on DAHC degradation contribute more near the drain edge than to the center region, and increase as L decreases. Therefore, further research on the DAHC degradation mechanism should be conducted to predict the reliability of HfSiON/SiO2 pMOSFETs with mechanical strain engineering.

Simulation of High-Speed and Low-Power CMOS Binary Image Sensor Based on Gate/Body-Tied PMOSFET-Type Photodetector Using Double-Tail Comparator

In this paper, we propose a complementary metal-oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector using a double-tail comparator for highspeed and low-power operations. The GBT photodetector is based on a PMOSFET tied with a floating gate (n+ polysilicon) and a body that amplifies the photocurrent generated by incident light. A double-tail comparator compares an input signal with a reference voltage and returns the output signal as either 0 or 1. The signal processing speed and power consumption of a double-tail comparator are superior over those of conventional comparator. Further, the use of a double-sampling circuit reduces the standard deviation of the output voltages. Therefore, the proposed CMOS binary image sensor using a double-tail comparator might have advantages, such as low power consumption and high signal processing speed. The proposed CMOS binary image sensor is designed and simulated using the standard 0.18 μm CMOS process.

Comparison of the MOSFET Response at Exposed of the X-Ray and Gamma Radiation

Introduction. Electromagnetic or ionizing radiation (IO) has great influence for radiation resistance of MOSFETs (metal–oxide–semiconductor field-effect transistors) and integrated circuits. Oxide, for the studied samples, is silicon dioxide, which acts as a dielectric in MOS structure. Currently, in literature there is no unambiguous idea of complete radiation response of MOSFETs to various types of ionizing radiation.Aim. To study radiation response of MOSFETs under influence of gamma and X-ray irradiation; to study effect of applied external potential of a gate substrate.Materials and methods. A total dose effect of gamma and X-ray radiation on the threshold voltage of MOSFET with a polysilicon gate and a gate oxide thickness of 120 nm with an applied external potential (-3, -2, 0, 3, 5, 10) V was studied. For gamma irradiation radionuclides cesium-137 with an energy of gamma quanta of 662 keV were used. X-ray tube with tungsten-rhenium cathode operated in modes 40 keV and 90 mkA was used as a source of X-ray radiation. Dose and time dependences of the change in the threshold voltage of n- and pchannel MOSFET were analyzed. It was performed that the influence of gamma and X-ray radiation led to the same effects in the studied structures. The maximum radiation response of MOSFETs was observed at high positive gate-substrate potentials. The approximation parameters associated with the concentration and capture cross sections of traps responsible for the formation of charges in the dielectric gate through irradiation were determined.Results. Strong influence of gamma and X-ray radiation led to the same effects in the studied structures. The applied voltage to the MOS structure during X-ray irradiation had a strong effect on their radiation response. The maximum radiation response of MOSFET at high positive gate-substrate potentials was observed. Proportionality coefficients to ensure the coincidence of the initial sections of the dose dependences for various applied gate-substrate potentials during irradiation were introduced. The coefficients allowed one to compare active and passive modes of operation of the X-ray emitter. Correction factors depended on the polarity of the applied gate-substrate potential. For negative potential, the proportionality coefficient value was 38.5. For the case of positive polarity the coefficient did not depend on the applied potential and the value was 120.Conclusion. The study allows one to determine the coefficients for dose dependences of threshold voltage changes. For the first time, to establish a numerical relations between the effects of various types of radiation sources at irradiation doses up to 1.9 · 104 Rad and proportionality coefficients becomes possible. It allows one to take into account the influence of applied potentials during irradiation on the radiation response of MOS structures.

Comparison of Hafnium Dioxide and Zirconium Dioxide Grown by Plasma-Enhanced Atomic Layer Deposition for the Application of Electronic Materials

We report the growth of nanoscale hafnium dioxide (HfO2) and zirconium dioxide (ZrO2) thin films using remote plasma-enhanced atomic layer deposition (PE-ALD), and the fabrication of complementary metal-oxide semiconductor (CMOS) integrated circuits using the HfO2 and ZrO2 thin films as the gate oxide. Tetrakis (dimethylamino) hafnium (Hf[N(CH3)2]4) and tetrakis (dimethylamino) zirconium (IV) (Zr[N(CH3)2]4) were used as the precursors, while O2 gas was used as the reactive gas. The PE-ALD-grown HfO2 and ZrO2 thin films were analyzed using X-ray photoelectron spectroscopy (XPS), X-ray diffraction (XRD), and high-resolution transmission electron microscopy (HRTEM). The XPS measurements show that the ZrO2 film has the atomic concentrations of 34% Zr, 2% C, and 64% O while the HfO2 film has the atomic concentrations of 29% Hf, 11% C, and 60% O. The HRTEM and XRD measurements show both HfO2 and ZrO2 films have polycrystalline structures. n-channel and p-channel metal-oxide semiconductor field-effect transistors (nFETs and pFETs), CMOS inverters, and CMOS ring oscillators were fabricated to test the quality of the HfO2 and ZrO2 thin films as the gate oxide. Current-voltage (IV) curves, transfer characteristics, and oscillation waveforms were measured from the fabricated transistors, inverters, and oscillators, respectively. The experimental results measured from the HfO2 and ZrO2 thin films were compared.

Study on the effects of Si implantation on the interface of 4H-SiC lateral MOSFETs

In this study, Si implantation was used to improve the interface properties of SiC/SiO2 in 4H-SiC lateral MOSFETs. In lateral n-channel MOSFETs, a 4%–6% improvement on the linear and saturation current was observed with Si implantation. From high/low-frequency CV measurements, the Si-implanted n-type MOS capacitor showed a 20% lower interface state density than the non-implanted ones at an energy level of EC − E = 0.2 eV, without degrading oxide integrity. Lateral p-channel MOSFETs, on the other hand, showed a 36.5% reduction in the linear current and a 16.6% reduction in the saturation current with Si implantation. Furthermore, the temperature coefficients of lateral and vertical MOSFETs implanted by Si were monitored up to 175 °C. The temperature coefficients of the Si-implanted n-channel and p-channel lateral MOSFETs were nearly identical to those of their non-implanted counterparts.

4H-SiC CMOS Transimpedance Amplifier of Gamma-Irradiation Resistance Over 1 MGy

A transimpedance amplifier (TIA)—with gamma-irradiation resistance of over 1 MGy—based on a novel 4H-SiC complementary MOS (CMOS) technology was fabricated. This TIA is robust enough to be applied in measuring instruments installed in nuclear power plants or other harshly irradiated environments. The SiC CMOS transistors comprising the TIA feature a thin (8-nm-thick) gate oxide to reduce the threshold-voltage shift ( ${V}_{{\text {th}}}$ ) due to irradiation by more than 90% compared with that of the conventional transistors. Oxynitride protection formed at the SiC–SiO2 interface in the thin gate-oxide region suppresses the deterioration of mobility by interface traps generated by the gamma radiation. The TIA consisting of these SiC-CMOS transistors operated properly up to at least 1.2 MGy without an increase in the offset voltage, although its open-loop gain was degraded due to deteriorated mobility of the p-channel metal–oxide–semiconductor field-effect transistor (MOSFET). On the other hand, increasing the drain leakage current in the nonactive region impeded further improvement of the SiC TIA under a high integral dose. To decrease the drain leakage current, a structure with a high doping concentration layer between the source and the drain in the nonactive region was fabricated. The structure stops the parasitic transistor turning on and the trap-assisted current increasing. The leakage current of the improved structure is about 42% lower than that of a conventional structure.

A High-Voltage DC–DC Buck Converter With Dynamic Level Shifter for Bootstrapped High-Side Gate Driver and Diode Emulator

Considering the propagation delay, dVSW/dt immunity, and power dissipation issues in the bootstrapped high-side gate driver design, a monolithic high-voltage dc-dc buck converter with a high-speed dynamic level shifter and improved gate drive buffer is presented in this article. With the introduction of instantaneous dynamic current, the propagation delay of the level shifter is reduced to 1.13 ns for the high-side switch. The dVSW/dt immunity is enhanced by a dynamic current compensation during positive slewing and a diode voltage clamp during negative slewing. The average current consumption of the level shifter is only 8.45 μA at a switching frequency of 1 MHz. The proposed gate drive buffer eliminates the shoot-through current with the use of dead-time control. The compact level shifter and buffer are also used to drive an integrated p-channel mosfet transistor serving as a bootstrap diode emulator. Experimental results show that the fabricated converter with the proposed scheme regulates well with an 18 V input, 1.05 V output, and 2 A load current. Also, high efficiency of up to 93% is achieved.

Structure and energetics of carbon defects in SiC (0001)/SiO2 systems at realistic temperatures: Defects in SiC, SiO2, and at their interface

We report systematic first-principles calculations that reveal the atomic configurations, stability, and energy levels of carbon defects in SiC (0001)/SiO2 systems. We clarify the stable position (i.e., in SiC, SiO2, or at SiC/SiO2 interfaces) of defects depending on the oxidation environment (an oxygen-rich or -poor condition). At finite temperatures, the chemical potential of atomic species was corrected referring to thermochemical tables in order to obtain the temperature-dependent defect formation energies. Under an oxygen-rich condition, we found that the dicarbon antisite [(C2)Si] in SiC is one of the favorable defects at a typical oxidation temperature of 1600 K and it creates a localized level near the conduction band edge of SiC, being a critical defect for n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). A variety of carbon-dimer defects at a SiC/SiO2 interface, such as Si—CO—CO2, Si—CO—CO—Si, and Si—(CO)—CO2, are stable under the oxygen-rich condition at 1600 K, and they create localized levels relatively close to the valence band edge of SiC, thus being critical defects for p-channel MOSFETs. In the viewpoint of static energetics, our results suggest that the oxidation of SiC under a high-temperature oxygen-poor condition is effective in suppressing the generation of carbon defects.

DC Modeling and Geometry Scaling of SiC Low-Voltage MOSFETs for Integrated Circuit Design

This paper presents the SPICE model development of the static characteristics of silicon carbide (SiC) lateral n-channel and p-channel MOSFETs based on the widely used BSIM4 compact model. The methodology for length and width scaling of the MOSFETs is demonstrated. The transfer ( $I_{\text{D}}$ – $V_{\text{G}}$ ) and output ( $I_{\text{D}}$ – $V_{\text{D}}$ ) characteristics of the SiC low-voltage MOSFETs are significantly different from their Si counterparts mainly due to the presence of the interface trapped charge, and proper modifications of the dc equations are required to accurately model the characteristics. The relatively poorer quality of the oxide-semiconductor interface in a SiC MOSFET compared to Si gives rise to valid energy states inside the bandgap. The trapped charges in these interface states are responsible for mobility degradation, higher subthreshold slope (SS), soft saturation, increase in the flat band and threshold voltage, and exaggerated body effects. In this paper, the effects of the interface trapped charge on the static characteristics of the SiC MOSFETs are intensively studied and accurate compact models are developed and incorporated in the core BSIM4 dc current equations to accurately model the SiC MOSFET ${I}$ – ${V}$ behavior. A new parameter extraction sequence is also proposed to optimize the model and the simulated characteristics are matched with the measured characteristics of SiC MOSFET devices.

Improved Offset Voltage Stability of 4H-SiC CMOS Operational Amplifier by Increasing Gamma Irradiation Resistance

We modified the active layout of an operational amplifier (op-amp) to exhibit high gamma irradiation resistance of over 100-kGy using our 4H-SiC complementary MOS technology, which can be applied for measuring instruments installed in nuclear power plants. The op-amp with the modified active layout features both a thin gate oxide and newly developed gate-electrode structure for suppressing the leakage current. From an experiment we conducted, the leakage current of the p-channel MOSFET with modified active layout remained unchanged from the initial value after irradiation, although that of it with the conventional layout we previously evaluated increased by about two orders of magnitude. The offset voltage of the improved op-amp was maintained below 2.8 mV up to 100-kGy irradiation. The improved op-amp also showed a healthy amplification characteristic without distortion.

Design and analysis of logic inverter using antimonide-based compound semiconductor junctionless transistor

In this paper, the optimization of gallium antimonide (GaSb) junctionless field-effect transistor (JLFETs) and logic inverter characteristics are analyzed. The hole mobility of GaSb is much higher than that of Si, which warrants high-performance p-channel transistor and low-power operation capability, and also, the mismatch between electron and hole mobilities is much lessened. Consequently, the dimension of p-channel MOSFET based on GaSb can be significantly reduced compared with the Si case. For these reasons and the potential application of GaSb to wide variety of III–V compound semiconductors towards electronics and photonics integration, and components under the extreme conditions, GaSb JLFET is studied in depth in this work. The proposed GaSb JLFET has the Al2O3 buffer between the channel and the Si substrate, which releases the lattice mismatch and suppresses leakage current effectively. The proposed n-channel JLFET has an Ion of 472 µA/µm and, SS of 76.2 mV/dec. The p-channel JLFET has an Ion of 541 µA/µm and SS of 73.4 mV/dec. The inverter using GaSb JLFETs shows excellent performances including NML = 0.28 V, NMH = 0.29 V, τPHL of 1.8 ps, and τPLH of 6.8 ps at an operating voltage as low as VDD = 0.7 V.

Unified Quantum and Reliability Model for Ultra-Thin Double-Gate MOSFETs

This paper presents a unified two-dimensional (2D) threshold voltage model for lightly doped symmetrical double-gate p-channel MOSFETs including quantum confinement effects and negative bias temperature instability (NBTI). The proposed model has been derived by solving the two-dimensional Poisson equation to obtain the NBTI potential model and the one-dimensional Schrodinger equation together with the 2D Poisson equation to obtain the quantum confinement model. The quantum expression was subsequently embedded in the NBTI solution to reach a unified model for both quantum confinement and NBTI. The model is simple and continuous, thereby ensuring compatibility for insertion in Verilog-A based device simulators. The effect of stress time on the degradation of the threshold voltage has been measured over a 10 year period. The accuracy of the model has been validated through comparisons with both 2D numerical simulations and experimental data. The results show matching within ±3% for channel lengths down to 7 nm and silicon thicknesses of 5 nm at 1 GHz operation after 10 years.

Subthreshold modeling of nanoscale germanium-tin (GeSn)-on-insulator MOSFETs including quantum effects

Although germanium-tin (GeSn) channel p-MOSFETs exhibit outstanding performance compared to other p-MOS transistors, their accurate analytical model has not yet been reported. In this paper, we present, for the first time, a 2-D surface-potential-based sub-threshold model for GeSn-on-insulator (GeSnOI) MOSFETs taking into account the interface-trapped and fixed-oxide charge densities, and also quantum effects. Unlike most of the earlier models applied to elementary and undoped semiconductor channels, the present model embraces variations in the alloy composition as well as doping concentration in the channel. Furthermore the model neither supports iterations nor involves any fitting parameters throughout the derivation, and hence it is physical, predictive, and applicable to circuit simulators like SPICE. We calculate various device parameters such as threshold voltage Vth, threshold voltage roll-up, drain induced barrier lowering DIBL and subthreshold slope SS related to short channel effects (SCEs) of GeSnOI p-MOSFETs for Sn contents ranging 0–6% and channel thickness from 5 to 10 nm. The obtained results show that the GeSnOI MOSFET with channel thickness of 5 nm yields the lowest value of Vth, DIBL, SS and Vth-shift indicating suppression of SCEs. Our model is verified by comparing analytical results for various device parameters with corresponding numerical simulation results and also with limited experimental data available in the literature.

A Novel Infrared Temperature Measurement with Dual Mode Modulation of Thermopile Sensor.

Superior to the traditional infrared temperature sensing architecture including infrared sensor and thermistor, we propose a novel sensing approach based on a single thermopile sensor with dual modes modulation. A switching and sensing circuit is proposed and realized with a chopper amplifier AD8551 and p-channel MOSFET (PMOS) for switching between detection of thermal radiation and the target and the ambient temperature for compensation. The error of target temperature after temperature compensation is estimated at less than 0.14 °C.

Monitoring of FinFET Characteristics Using $\Delta V_{\text{DIBLSS}}/(I_{\text{on}}/I_{\text{off}})$ and $\Delta V_{\text{DIBL}}/(I_{\text{on}}/I_{\text{off}})$

In this paper, we present a descriptive analysis of a performance index, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta V_{\mathrm{ DIBLSS}}/(I_{\mathrm{ on}}/I_{\mathrm{ off}})$ </tex-math></inline-formula> , used for performance monitoring. Scaled n- and p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) (planar and FinFET devices) are included for comparison of performance trends. Also, the simplified <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta V_{\mathrm{ DIBL}}/(I_{\mathrm{ on}}/I_{\mathrm{ off}})$ </tex-math></inline-formula> for monitoring the electrical characteristics of MOSFET devices is proposed due to the “quick measurements” required in the last step of the semiconductor manufacturing process. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta V_{\mathrm{ DIBL}}/(I_{\mathrm{ on}}/I_{\mathrm{ off}})$ </tex-math></inline-formula> only accounts for drain-induced barrier lowering in its numerator and on/off current ratio in its denominator. The calculation process for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta V_{\mathrm{ DIBL}}/(I_{\mathrm{ on}}/I_{\mathrm{ off}})$ </tex-math></inline-formula> is much quicker than for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta V_{\mathrm{ DIBLSS}}/(I_{\mathrm{ on}}/I_{\mathrm{ off}})$ </tex-math></inline-formula> , where we need to make an extra measurement of the value of the subthreshold swing. Performance metrics, such as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm{ on}}/I_{\mathrm{ off}}$ </tex-math></inline-formula> and intrinsic gain, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_{m} \times r_{o}$ </tex-math></inline-formula> , are reported using <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta V_{\mathrm{ DIBLSS}}/(I_{\mathrm{ on}}/I_{\mathrm{ off}})$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta V_{\mathrm{ DIBL}}/(I_{\mathrm{ on}}/I_{\mathrm{ off}})$ </tex-math></inline-formula> . <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta V_{\mathrm{ DIBLSS}}$ </tex-math></inline-formula> of about 100 mV in scaled MOSFETs is required to ensure that the gate control is strong. Since <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm{ on}}/I_{\mathrm{ off}}$ </tex-math></inline-formula> is a sensitive function of threshold voltage, the estimates of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta V_{\mathrm{ DIBLSS}}/(I_{\mathrm{ on}}/I_{\mathrm{ off}})$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta V_{\mathrm{ DIBL}}/(I_{\mathrm{ on}}/I_{\mathrm{ off}})$ </tex-math></inline-formula> are therefore dependent on the design of threshold voltage. In planar MOSFETs, small values of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta V_{\mathrm{ DIBLSS}}/(I_{\mathrm{ on}}/I_{\mathrm{ off}})$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta V_{\mathrm{ DIBL}}/(I_{\mathrm{ on}}/I_{\mathrm{ off}})$ </tex-math></inline-formula> are hard to achieve. However, in FinFETs, it is easy to achieve the performance requirements due to its tri-gate structure.

The Performance of Operational Amplifiers Consisting of 4H-SiC CMOS After Gamma Irradiation

The operational amplifier was fabricated by 4H-SiC complementary MOS on the same die for sensors installed in nuclear power plants, and it showed over $100\times $ the radiation resistance compared with Si bipolar junction transistors. The closed-loop gain at 50 kGy was 11% lower than it of preirradiation because the allowable output voltage range became small by the threshold voltage degradation of p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs), and the offset voltage became unstable when the gamma integral dose was beyond 30 kGy. To reduce the influence of gamma irradiation, we propose a MOSFETs structure which features both thin gate oxide and field plate electrodes connected to an isolation layer. We evaluated the proposed isolation structure using the single device, and our experiments confirmed that the proposed isolation structure has potential of gamma irradiation resistance of 100 kGy.

Reliability studies on biaxially tensile strained-Si channel p-MOSFETs

Reliability studies on biaxially tensile strained-Si channel p-MOSFETs

Reliability studies on biaxially tensile strained-Si channel p-MOSFETs

An integrated technology computer aided simulation framework is used for the first time to predict the reliability (degradation) of substrate-induced strained-Si channel heterojunction field effect transistors on relaxed Silicon-Germanium buffer layer with ultra-thin SiO2 and high-k gate stacks. State-of-the-art four-state nonradiative multiphonon model is used for the degradation studies. Single defects and trap studies have been taken up on devices subjected to negative voltage stressing at an elevated temperature. Threshold voltage shift (due to charge capture and emission processes) in virtually fabricated devices has been studied in detail. For the first time, non radiative multiphonon model is used to explain the degradation mechanisms (oxide defects dominating the partial recovery of threshold voltage after stressing) in strained-Si channel heterojunction field effect transistors. It is shown that degradation in strained-Si channel device on relaxed-SiGe buffer is more compared to its Si-channel counterpart.