Oxynitride Dielectrics Research Articles

AlN and Al oxy-nitride gate dielectrics for reliable gate stacks on Ge and InGaAs channels

AlN and Al oxy-nitride dielectric layers are proposed instead of Al2O3 as a component of the gate dielectric stacks on higher mobility channels in metal oxide field effect transistors to improve their positive bias stress instability reliability. It is calculated that the gap states of nitrogen vacancies in AlN lie further away in energy from the semiconductor band gap than those of oxygen vacancies in Al2O3, and thus AlN might be less susceptible to charge trapping and have a better reliability performance. The unfavourable defect energy level distribution in amorphous Al2O3 is attributed to its larger coordination disorder compared to the more symmetrically bonded AlN. Al oxy-nitride is also predicted to have less tendency for charge trapping.

Improved bias-temperature instability characteristics in SiC metal-oxide-semiconductor devices with aluminum oxynitride dielectrics

Significant improvement of bias-temperature instability characteristics in SiC-based metal-oxide-semiconductor (MOS) devices was demonstrated with high-permittivity aluminum oxynitride (AlON) dielectrics deposited on thin thermal oxides. AlON/SiO2 stacked dielectrics were found to be beneficial not only for reducing gate leakage current but also for suppressing diffusion of positively charged ions, leading to stable SiC-MOS characteristics even under strong electric fields and high temperatures. Unlike the prompt electric-field-induced ion migration in thermally grown and sputter-deposited SiO2 dielectrics, the ion drift for the stacked gate dielectrics was confined within the thin SiO2 underlayers owing to low ion diffusivity in AlON layers. Impacts of mobile ions on interface properties of SiC-MOS devices and effects of intentional ion trapping within the AlON layers were also systematically investigated.

Gate stack technology for advanced high-mobility Ge-channel metal-oxide-semiconductor devices – Fundamental aspects of germanium oxides and application of plasma nitridation technique for fabrication of scalable oxynitride dielectrics

Germanium (Ge)-based high-mobility metal-oxide-semiconductor field-effect transistors (MOSFETs) have gained considerable attention because they perform better than common Si-based devices. Although degraded electrical property of germanium oxide (GeO2) gate insulators is considered the most serious obstacle for implementing Ge-channel for future MOSFETs, remarkable progress has been made recently. This article overviews both fundamental and technological aspects of thermally grown GeO2, and discusses strategies for achieving ultrathin gate insulators for high-performance Ge-based MOSFETs. Our experimental and theoretical studies revealed that, despite excellent electrical property of GeO2/Ge interface, its poor stability is a big concern, especially for ultrathin dielectrics. To overcome this problem, we investigated the impact of plasma nitridation of Ge and GeO2 surfaces, in terms of surface cleaning, stability, and electrical properties of the nitrides. On the basis of the experimental findings, we have proposed high-quality Ge oxynitride (GeON) gate dielectrics, which consist of stable nitrogen-rich capping layers on ultrathin oxides. We implemented the GeON gate dielectrics into Ge-channel pMOSFETs and successfully demonstrated hole mobility that was 2.4 times higher than Si universal mobility.

A New Model for Two-Dimensional Electrical-Field-Dependent $V_{\rm th}$ Instability of pMOSFETs With Ultrathin DPN Gate Dielectrics

The 2-D electrical-field-dependent hot-hole-related negative-bias temperature instability (HH-NBTI) behaviors of pMOSFETs with 1.7-nm decoupled-plasma-nitridation oxynitride dielectrics are investigated. The lateral-channel electric-field-induced turnaround HH-NBTI degradation that is associated with the enhanced breaking effect of the interfacial Si-H bonds at the Si interface is demonstrated. For the first time, the lateral-electric-field-dependent activation energy of ≡ Si- H bond dissociation is presented. A new model taking into account the 2-D electric field effects is proposed to depict the HH-NBTI behaviors related to the lateral- and vertical-channel electric fields. The proposed model is verified by the experimental data.

45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications

The 45-nm technology, called 12S and developed for IBM POWER7®, is an extremely robust and versatile technology platform that allows for a rich set of features that include embedded dynamic random access memory (DRAM), performance and dense static RAM (SRAM), a trench-based decoupling capacitor, a comprehensive device menu, and a high-performance hierarchical back-end interconnect scheme, all built on a silicon-on-insulator (SOI) substrate. Embedded DRAM was implemented for production in high-performance SOI for the first time and allowed us to leapfrog two generations of conventional SRAM densities. Immersion lithography was also employed for the first time in 45-nm IBM products. Our 45-nm design point represents a judicious leverage of silicon oxynitride dielectrics, scaled device technology, and rich features to yield chip-level performance enhancement of more than 50%, compared with our 65-nm node at comparable or less power. This paper describes the salient features of this technology node, the process architecture, the device design rationale, and the process design interactions.

Current Understanding of the Transport Behavior of Hydrogen Species in MOS Stacks and Their Relation to Reliability Degradation

We review recent experiments that suggest a comprehensive model for the reversible hydrogen (H) transport between the poly-Si interface and the oxide/Si interface of MOS stacks. The H diffusion in intact model MOS structures is probed by H depth profiling via resonant 15N-H nuclear reaction analysis (NRA). It is demonstrated that MOS device degradation correlates with H accumulation in the oxide/Si interface region. A specific ultra-thin oxynitride is discovered in the poly-Si/oxynitride interface as well as in the near-surface region of N2-annealed nitride films and shown to function as a potential H-storage layer. The interfacial storage layer between the poly-Si gate and the oxynitride dielectric of MOS transistors is found to contain two kinds of H species, which are mobile and stable, respectively, versus irradiation-induced relocation. The mobile H, if stimulated by energetic carriers, migrates across the gate films and relocates to the SiO2/Si interface, causing device instabilities. Understanding this basic hydrogen transport behavior allows conceiving fabrication countermeasures to improve the device reliability.

High-κ/Metal Gate Science and Technology

High-κ/metal gate technology is on the verge of replacing conventional oxynitride dielectrics in state-of-the-art transistors for both high-performance and low-power applications. In this review we discuss some of the key materials issues that complicated the introduction of high-κ dielectrics, including reduced electron mobility, oxygen-based thermal instabilities, and the absence of thermally stable dual-metal electrodes. We show that through a combination of materials innovations and engineering ingenuity these issues were successfully overcome, thereby paving the way for high-κ/metal gate implementation.

Aluminum oxynitride dielectrics for multilayer capacitors with higher energy density and wide temperature properties

Amorphous aluminum oxynitride (AlON) possesses unique properties of high dielectric strength, high resistivity, low loss, high decomposition temperature, chemical inertness, and high thermal conductivity. These properties make it a candidate for a next generation capacitor dielectric. DC pulsed magnetron reactive sputtering is used to produce amorphous AlON films on various substrates. Dielectric properties are optimized by adjusting DC power, pulse frequency, total pressure, substrate temperature, and gas ratio. Simple parallel plate structures are utilized to characterize the dielectric properties. Clearable electrodes are evaluated in device performance. Defects cleared without significant loss of capacitance. Temperature dependent dielectric properties were evaluated from − 200 °C to + 400 °C. Stacked multilayer capacitor device is developed for high energy density and wide temperature applications.

Defect states in HfO 2 on deposited on Ge(1 1 1) and Ge(1 0 0) substrates

There is considerable interest in the direct bonding between Si and Ge substrates and high-K nano-crystalline transition metal elemental and complex oxides. Implicit in this is the elimination of lower-K interfacial transition regions (ITRs) in gate stacks which limit device down-scaling of advanced devices to meet roadmap targets. A novel approach is presented in this article for (i) deposition of HfO 2 onto N-passivated Ge(1 1 1) and Ge(1 0 0) substrates, a process that also prevents subcutaneous oxidation of the Ge substrate during the deposition of nano-crystalline HfO 2 and non-crystalline Hf Si oxynitride dielectrics as well, and (ii) the effective removal of Ge–N, during an 800 °C rapid thermal annealing. Removal of Ge–N bonding has been confirmed by X-ray absorption N K 1 spectra (XAS). However, even though X-ray photoelectron spectroscopy (XPS) studies has indicated no detectable Ge–O bonding at the Ge-dielectric interfaces as-deposited, a significant amount of Ge–O bonding throughout the entire HfO 2 film is detected by XPS and XAS after the 800 °C anneal. Current–voltage measurements indicate significantly higher leakage for HfO 2 films on Ge(1 1 1) compared with Ge(1 0 0). These correlate with differences in band edge defect state densities obtained from spectroscopic measurements, and are consistent with a more columnar, bonding morphology for direct bonding of HfO 2 on Ge(1 1 1) than for Ge(1 0 0).

Low-power dihexylquaterthiophene-based thin film transistors for analog applications

We have optimized dihexylquaterthiophene-based thin film transistors for low-power consumption and have studied their characteristics for potential introduction in analog circuits. Bottom-gate devices with Pd source and drain electrodes have been fabricated by employing different gate dielectrics. Transistors with very thin (<10nm) silicon oxynitride dielectrics display subthreshold swing values below 100mV/decade, cutoff frequencies approaching the kilohertz range and intrinsic gain around 45dB, suggesting that they are promising candidates for low-power analog integration.

Reduction of the anomalous VT behavior in MOSFETs with high- κ/metal gate stacks

This study investigates the impact of different nitridation processes on hafnium silicon oxynitride (HfSiON) dielectrics. It is demonstrated that the threshold voltage ( V T vs. L g) behavior at short gate lengths is strongly impacted by the nitridation process, depending on the Hf/(Hf+Si) ratio and the HfSiON thickness. A Plasma nitridation in oxidizing ambient results in a modification of the dielectric that can explain the anomalous V T behavior in devices integrated with hafnium-based dielectrics and metal gate. Reduction in anomalous V T behavior and limited gate leakage is achieved by applying a thermal nitridation in a NH 3 ambient on Hf-rich silicon oxynitride.

Effect of nitrogen incorporation on the thermal stability of sputter deposited lanthanum aluminate dielectrics on Si (100)

The thermal stability of sputter deposited LaAlOx and lanthanum aluminum oxynitride (LaAlON) dielectrics on top of Si (100) was evaluated after 1000°C rapid thermal annealing (RTA). A nitrogen concentration of ∼3at.% in the bulk LaAlON film was found to suppress crystallization as well as metal (lanthanum and aluminum) outdiffusion into the Si (100) substrate after the RTA treatment. These results suggest that film microstructure should be carefully controlled to inhibit impurity diffusion in the conventional gate stack fabrication process.

Nanoscale germanium MOS Dielectrics-part I: germanium oxynitrides

In this paper, nanoscale germanium (Ge) oxynitride dielectrics are investigated for Ge MOS device applications. The synthesizing methodology and physical properties of these oxynitride films have been examined first. Basic electrical characteristics have been acquired on metal-gated MOS capacitors with Ge oxynitride dielectric on substrates with different dopant types and crystal orientations. Using an optimized oxidation and nitridation recipe, high-quality Ge MOS capacitors with a minimal frequency dispersion and capacitance-voltage hysteresis have been demonstrated. In addition, the Ge oxynitride dielectric-substrate interface has also been analyzed with the combined low-frequency-high-frequency capacitance method that revealed a substantial reduction of interface trap density after the forming gas anneal. An asymmetric interface trap density distribution within the Ge bandgap has been mapped out, which might explain the inferior n-channel Ge MOSFETs with oxynitride dielectric. An abnormality in the general gate leakage behavior has been observed and found to originate from a transient charge-trapping effect.

Ultra low energy SIMS depth profiling of sub-1.5 nm silicon oxynitride films

Silicon oxynitride is one of the most researched silicon-based dielectric currently used in IC fabrication. Properties of the oxynitride films can be modified to achieve desirable functions by specific engineering of thickness and stoichiometry. In the case of gate stacks, considerable progress has been made in optimising the properties of oxynitride dielectrics in order to reduce boron penetration and dielectric leakage with respect to pure SiO 2, allowing sub-2 nm dielectrics. In this study ultra low energy (ULE) secondary ion mass spectrometry (SIMS) has been used to assess a range of ultra thin (<1.5 nm) silicon oxynitride films containing varied amounts of nitrogen (up to 18 at.%) and the results have been compared with shallow angle surface X-ray photoelectron spectroscopy (XPS). Despite the limited number of atomic layers available for probing, this investigation indicates that both techniques are capable of extracting useful and reliable chemical and physical information from these oxynitride films. Critical parameters such as stoichiometry and film thickness have been evaluated, whilst consistency between the two techniques is also addressed.

Scalability and Electrical Properties of Germanium Oxynitride MOS Dielectrics

In this letter, we present a fundamental study on the scalability and electrical properties of germanium oxynitride dielectrics for metal-oxide-semiconductor device applications. The nitrogen depth profile within the oxynitride dielectric layers was first monitored using angle-resolved x-ray photoemission spectroscopy and the dielectric permittivity variation was therefore identified. After thinning down the lower permittivity portion of these dielectrics, we successfully scaled down the capacitance-based equivalent SiO/sub 2/ thickness, in Ge MOS capacitors, to 1.9 nm without suffering from gate leakage. We have also investigated the effects of thermal annealing on various capacitor electrical properties. For instance, we measured a flat-band voltage shift of as much as -0.8 V from the ideal value on as-deposited capacitors and the recovery of the theoretical value, with acceptably small amount of oxide fixed charge, after subsequent thermal annealing. Lastly, we have benchmarked the performance of these oxynitride insulators with the advanced high-/spl kappa/ dielectrics on Ge and discussed the impacts on future scaling.

1.0 nm Oxynitride Dielectrics Prepared by RTP in Mixtures of N[sub 2] and O[sub 2] Ambient

This work presents a reliable method of growing aggressively scaled, 1.0 nm thick, gate dielectric in mixtures of and ambient at 900°C for 15 s by rapid thermal processing (RTP). These oxynitride films have excellent interface properties, 100 times lower leakage current density, and better charge trapping properties than rapid thermal oxidation of identical thickness prepared in pure ambient. The effect of interfacial nitrogen concentration on the device characteristics with gate oxynitride films grown in various gas flow ratios was also investigated. The results demonstrate that the uniform nitrogen content increases with the gas flow ratio and that high-quality oxynitride films can be obtained by RTP in an optimum gas flow ratio of © 2004 The Electrochemical Society. All rights reserved.

High Reliability Ultrathin Interpolyoxynitride Dielectrics Prepared by N 2 O Plasma Annealing

This work addresses the preparation of ultrathin (effective oxide thickness, 42 Å) interpoly-oxynitride films by annealing thin nitride films with high density plasma and rapid thermal annealing. The proposed oxynitride dielectrics formed using plasma annealing exhibited low gate leakage current, high breakdown electric field, long ten-year lifetime, and large effective barrier height. These superior properties can be attributed to the high concentration of oxygen incorporated in the poly-II/nitride interface and a reduction of the trap density of the interpoly-oxynitride films. The dielectric is a suitable substitute for the inter-polyoxide of electrically-erasable programmable read only memory. © 2003 The Electrochemical Society. All rights reserved.

Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go?

The vertical scaling requirements for gate stacks and for shallow extension junctions are reviewed. For gate stacks, considerable progress has been made in optimizing oxide/nitride and oxynitride dielectrics to reduce boron penetration and dielectric leakage compared to pure SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> in order to allow sub-2-nm dielectrics. Several promising alternative material candidates exist for 1-nm equivalent oxide thickness (EOT)—for example, HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> , ZrO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> , and their silicates. Nevertheless, considerable challenges lie ahead if we are to achieve an EOT of less than 0.5 nm. If only a single molecular interface layer of oxide is needed to preserve high channel mobility, it seems likely that an EOT of 0.4–0.5 nm would represent the physical limit of dielectric scaling, but even then with a very high leakage (∼10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ). For junctions, the main challenge lies in providing low parasitic series resistance as depths are scaled in order to reduce short-channel effects. Because contacts are ultimately expected to dominate the parasitic resistance, low-barrier-height contacts and/or very heavily doped junctions will be required. While ion implantation and annealing processes can certainly be extended to meet the junction-depth and series-resistance requirements for additional generations, alternative low-temperature deposition processes that produce either metastably or extraordinarily activated, abruptly doped regions seem better suited to solve the contact resistance problem.

Degradation and SILC Effects of RPECVD sub-2.0nm Oxide/Nitride and Oxynitride Dielectrics Under Constant Current Stress

AbstractConstant current stress (CCS) has been used to investigate the Stress-Induced Leakage Current (SILC) to clarify the influence of boron penetration and nitrogen incorporation on the breakdown of p-channel devices with sub-2.0 nm Oxide/Nitride (O/N) and oxynitride dielectrics prepared by remote plasma enhanced CVD (RPECVD). Degradation of MOSFET characteristics correlated with soft breakdown (SBD) and hard breakdown (HBD), and attributed to the increased gate leakage current are studied. Gate voltages were gradually decreased during SBD, and a continuous increase in SILC at low gate voltages between each stress interval, is shown to be due to the generation of positive traps which are enhanced by boron penetration. Compared to thermal oxides, stacked O/N and oxynitride dielectrics with interface nitridation show reduced SILC due to the suppression of boron penetration and associated positive trap generation. Devices stressed under substrate injection show harder breakdown and more severe degradation, implying a greater amount of the stress-induced defects at SiO2/substrate interface. Stacked O/N and oxynitride devices also show less degradation in electrical performance compared to thermal oxide devices due to an improved Si/SiO2 interface, and reduced gate-to-drain overlap region.

X-Ray Reflectivity Study Of Exotic Materials For Electronic Applications

AbstractAs device size continues to decrease, new challenges arise regarding shrinking dimensions, creating the need for thin, high-k dielectric materials, low-k dielectrics and other exotic materials. These new materials in turn create characterization issues, which cannot be resolved with traditional metrology tools. Critical structural parameters such as thickness, density, and interface roughness of a layer can be measured and monitored with X-ray reflectivity. A quick and reliable method of study regarding these materials is to base work on simulations using a very robust fitting program. This work incorporates a largely theoretical study of exotic materials of interest, including silicon oxynitride (SiOxNy), low-k (porous films) and high-k dielectrics (Ta2O5, HfO2), with a few selected experimental results.