Oxide Thickness Uniformity Research Articles

Deposition uniformity inspection in IC wafer surface

This paper focuses on the task of automatic visual inspection of color uniformity on the surface of integrated circuits (IC) wafers arising from the layering process. The oxide thickness uniformity within a given wafer with a desired target thickness is of great importance for modern semiconductor circuits with small oxide thickness. The non-uniform chemical vapor deposition (CVD) on a wafer surface will proceed to fail testing in Wafer Acceptance Test (WAT). Early detection of non-uniform deposition in a wafer surface can reduce material waste and improve production yields. The fastest and most low-priced inspection method is a machine vision-based inspection system. In this paper, the proposed visual inspection system is based on the color representations which were reflected from wafer surface. The regions of non-uniform deposition present different colors from the uniform background in a wafer surface. The proposed inspection technique first learns the color data via color space transformation from uniform deposition of normal wafer surfaces. The individual small region statistical comparison scheme then proceeds to the testing wafers. Experimental results show that the proposed method can effectively detect the non-uniform deposition regions on the wafer surface. The inspection time of the deposited wafers is quite compatible with the atmospheric pressure CVD time.

A novel trench gate MOSFET with a multiple-layered gate oxide for high-reliability operation

Gate dielectrics in trench structures for trench gate metal oxide semiconductor field-effect transistor (MOSFET) power devices are very important to realize excellent characteristics. In this paper we describe multiple-layer gate dielectrics for trench gate MOSFETs with both thermal and chemical vapor deposition (CVD) gate oxides that exhibit excellent gate oxide properties and surface roughness. Through various trench etching experiments for better surface conditions in the trench, the optimum etching gas chemistry and etch conditions were found. The destruction of gate dielectric in trench gate MOSFET occurs at the top and the bottom trench corner edges. The structure of the gate electrode is pulled out with the polysilicon layer which is buried in the trench. Thus, high electric field operation is inevitable at the gate between source diffusion and the gate polysilicon. Moreover, the trench corner oxide suffers from the high electric field. We propose a multiple-gate dielectric structure of a thermal oxide and CVD oxide for highly reliable operation of the device. This enables trench surface smoothing and low thermal stress at the trench corners and provides the oxide thickness uniformity, giving superior device characteristics of high breakdown voltage and low leakage current. These improvements are caused by the excellent quality of the gate oxide and the good thickness uniformity that is formed at the inner trench with a specific geometrical factor.

(Invited) Scanning Probe Analysis of Dielectrics on High Mobility Substrates

In this work we employ electrical scanning probe techniques to evaluate on a nanoscale the influence of semiconductor surface morphology on the electrical properties of dielectrics. Gate leakage, reliability and oxide thickness uniformity are assessed by conductive atomic force microscopy (C-AFM). Interface traps are analyzed by scanning capacitance microscopy (SCM). A correlation between nanoscale and macroscale trends is established following reverse processing of the devices. The impact of surface morphology on localized dielectric properties is evaluated by studying MOSFETs having the same silicon channel strain but different dielectric/substrate interface roughness. The correlation between surface morphology, leakage and SCM signal suggests that for dielectrics on high mobility substrates prone to surface roughening, the morphology as well as the dielectric itself play a role in the final dielectric quality. Optimized epitaxial growth will therefore enable improved device performance, reliability and variability. The results have implications for all technologies which employ relaxed SiGe templates.

Analysis of InP Regrowth on Deep-Etched Mesas and Structural Characterization for Buried-Heterostructure Quantum Cascade Lasers

We investigated the effect of deep-etched mesa sidewall profile and oxide overhang length on the regrowth structural characteristics for buried- heterostructure (BH) quantum cascade lasers (QCLs) grown by metalorganic chemical vapor deposition (MOCVD). The relationship between etched mesa sidewall geometry, oxide overhang length, oxide thickness, and growth uniformity was examined and is extensively discussed. In particular, anomalous growth in the vicinity of the oxide edge resulting from insufficient oxide overhang length was identified and studied. An ideal ratio of mesa height to oxide overhang length between 2.5 and 3.0 is proposed and experimentally justified to yield satisfactory planar regrowths without anomalous growth. Mesas in the \( [ 0 1\overline{ 1} ] \) direction with smoothly etched entrant profile yield a higher degree of growth uniformity than mesas in the [011] direction with the re-entrant profile.

Nitrogen profile engineering in the interfacial SiON in a HfAlO/SiON gate dielectric by NO Re-oxidation

The effects of the nitrogen profile in the SiON-interfacial layer (IL) on the mobility in FETs employing a HfAlO/SiON gate dielectric have been investigated. In order to suppress the interdiffusion between HfAlO and SiON, the nitrogen concentration in SiON should be higher than 15 at%, while the substrate interface should be oxygen-rich in order to suppress the mobility reduction. By using an NO reoxidation of NH/sub 3/ formed 0.4-nm-thick silicon nitride, the mobility reduction due to the SiON-IL was successfully suppressed, and electron and hole mobility of 92% and 88% of those for SiO/sub 2/ at V/sub g/=1.1 V were obtained for HfAlO/SiON with equivalent oxide thickness (EOT) of 1.1 nm. By using nitrogen profile engineered SiON-IL, good equvalent oxide thickness (EOT) uniformity, low EOT, low gate leakage current, low defect density, and symmetrical threshold voltage were all achieved, indicating that a poly-Si/HfAlO/SiON gate stack would be a candidate as an alternative gate structure for low standby power FETs of half-pitch (hp)65 and hp45 technology nodes.

Improvement of oxide thickness uniformity by high then low O2 pressure oxidation in rapid thermal processing

This article presents the growth of thin oxides by rapid thermal processing (RTP) under different O2 pressures, indicating that high pressure oxidation tends to make oxide thickness less uniform as oxidation time increases. However, oxide under low pressure oxidation tends to saturate in thickness and a “self-compensating” phenomenon occurs. Thus in order to grow ultrathin gate oxide in a desired thickness regime with good thickness uniformity, we developed a technology called high then low pressure oxidation. The experimental results show that in thickness and electrical properties the uniformity of oxide obtained by oxidation under high then low pressure would indeed be improved.

Improvement in oxide thickness uniformity by repeated spike oxidation

A new repeated spike oxidation (RSO) method used in a rapid thermal processing system was proposed in this work. Simulation results predict the temperature distribution on the wafer would be improved by this RSO method. We proposed that the improvement in wafer temperature uniformity is mainly caused by self-compensation in radiation heat absorption rate. Experimental data pointed out that the new method can produce more uniform oxide thickness than the conventional one under an intentionally created nonuniform heating environment.

Can macroscopic oxide thickness uniformity improve oxide reliability?

In this work, we investigated both experimentally and numerically the impact of macroscopic oxide thickness uniformity on Weibull breakdown characteristics for both Weibull parameters, namely, the characteristics times (T/sub 63/) and Weibull slopes (/spl beta/) over a wide range of oxide thickness. A detailed full-scale Monte Carlo analysis is used to examine the breakdown characteristics at low-percentile and its sensitivity to variation of thickness dependence of time-to-breakdown and Weibull slopes. We show that for thinner oxides with very shallow Weibull slopes the impact of thickness variation is drastically reduced as compared to thicker oxides for the same parameters.

Weibull breakdown characteristics and oxide thickness uniformity

In this work, we investigated both experimentally and numerically the impact of macroscopic oxide thickness uniformity on Weibull breakdown characteristics for both Weibull parameters, namely, the characteristic times and Weibull slopes over a wide range of oxide thicknesses. We report the abnormal characteristics of the Weibull time-to-breakdown distributions and non-Poisson area scaling behavior observed on ultrathin oxides. Two numerical methods using the parameters obtained from two independent sets of experimental results are developed to quantitatively explain these effects in the context of current modulation due to oxide thickness variation. The relationship between time-to-breakdown and charge-to-breakdown distributions has been clarified and established. It is found that without proper treatment of these effects, the use of Weibull slopes at higher failure percentiles can lead to erroneous and pessimistic reliability projection. Furthermore, me perform a detailed full-scale Monte Carlo analysis to evaluate the impact of thickness variation on low-percentile breakdown distributions and their sensitivity to the thickness dependence of the times-to-breakdown and Weibull slopes.

Electrical characteristics of high-quality sub-25-/spl Aring/ oxides grown by ultraviolet ozone exposure at low temperature

We have developed a method for controllably and reproducibly growing self-limiting ultrathin oxides with excellent electrical properties in the range /spl sim/10-25 /spl Aring/ thick at temperatures ranging from 25 to 600/spl deg/C, respectively, using an ultraviolet ozone (UVO/sub 3/) oxidation process. The self-limiting thickness depends primarily on the substrate temperature, allowing ultrathin oxide growth with precision and reproducibility using this UVO/sub 3/ process. Oxides grown by this method are comparable in electrical quality to thermal oxides, with similar leakage current densities and breakdown fields E/sub BD/>10 MV/cm. Current-voltage (I-V) analysis shows oxide thickness uniformity to within 1% from center to edge of a 4-in wafer. Capacitance-voltage (C-V) characterization of /spl sim/25 /spl Aring/ oxides shows excellent saturation behaviour, with low midgap interface trap densities and no hysteresis or dispersion.

The effect of patterned susceptor on the thickness uniformity of rapid thermal oxides

A temperature compensation concept suitable for rapid thermal processing (RTP) with a nonuniform wafer temperature distribution is proposed in this work. Concentric Si rings with different diameters are placed on planar quartz or Si susceptors and are regarded as patterned susceptors for temperature compensation. We put monitor wafers on the patterned susceptor and see the effect of the patterned susceptor on the oxide thickness uniformity of the monitor wafers. The Si rings work as radiation barriers when placed on the quartz susceptor, but as heat conduction media when placed on the Si susceptor. By properly arranging the Si rings on the planar susceptors, the monitor wafers' oxide thickness uniformity can be improved.

Process Definition for Obtaining Ultra-Thin Silicon Oxides Using Full-Wafer Electrical and Optical Measurements

ABSTRACTThe objective of this research was to establish a new baseline process for obtaining ultra-thin silicon-oxide gate material in a prototype vertical furnace. Of particular concern was the optimization of a process sequence whereby unpatterned 150 mm diameter wafers ‘see’ the same processing steps prior to gate oxidation as patterned device wafers ‘see’. The figures-of-merit for evaluating process optimization include: i) full-wafer current-voltage (I-V) maps using Hg-gate capacitors; ii) the variation in the current or current density at a given bias voltage, extracted from an I-V map; iii) the variation in electrical oxide thickness that is extracted from full-wafer capacitance-voltage measurements using Hg-gate capacitors; and iv) the variation in optical oxide thickness that is extracted from full-wafer spectroscopic ellipsometry measurements. The results from this research demonstrate that: i) the addition of 1% O2 to the usual N2 gas during the ramp-up cycle in the vertical furnace is necessary to achieve acceptable across-the-wafer oxide-thickness uniformity as determined from both electrical and optical figures-of-merit; and ii) a full-wafer response surface of the current at a given bias voltage is a powerful finger print for process development when the question of variation in as-grown silicon-oxide thickness is at issue.

Effects of dc bias on the kinetics and electrical properties of silicon dioxide grown in an electron cyclotron resonance plasma

Thin (3–300-nm) oxides were grown on single-crystal silicon substrates at temperatures from 523 to 673 K in a low-pressure electron cyclotron resonance (ECR) oxygen plasma. Oxides were grown under floating, anodic or cathodic bias conditions, although only the oxides grown under floating or anodic bias conditions are acceptable for use as gate dielectrics in metal-oxide-semiconductor technology. Oxide thickness uniformity as measured by ellipsometry decreased with increasing oxidation time for all bias conditions. Oxidation kinetics under anodic conditions can be explained by negatively charged atomic oxygen, O−, transport limited growth. Constant current anodizations yielded three regions of growth: (1) a concentration gradient dominated regime for oxides thinner than 10 nm, (2) a field dominated regime with ohmic charged oxidant transport for oxide thickness in the range of 10 nm to approximately 100 nm, and (3) a space-charge limited regime for films thicker than approximately 100 nm. The relationship between oxide thickness (xox), overall potential drop (Vox) and ion current (ji) in the space-charge limited transport region was of the form: ji ∝ V2ox/x3ox. Transmission electron microscopy analysis of 5–60-nm-thick anodized films indicated that the silicon-silicon dioxide interface was indistinguishable from that of thermal oxides grown at 1123 K. High-frequency capacitance-voltage (C-V) and ramped bias current-voltage (I-V) studies performed on 5.4–30-nm gate thickness capacitors indicated that the as-grown ECR films had high levels of fixed oxide charge (≳1011 cm−2) and interface traps (≳1012 cm−2 eV−1). The fixed charge level could be reduced to ≊4×1010 cm−2 by a 20 min polysilicon gate activation anneal at 1123 K in nitrogen; the interface trap density at mid-band gap decreased to ≊(1–2)×1011 cm−2 eV−1 after this process. The mean breakdown strength for anodic oxides grown under optimum conditions was 10.87±0.83 MV cm−1. Electrical properties of the 5.4–8-nm gates compared well with thicker films and control dry thermal oxides of similar thicknesses.

Silicon Gate Oxide Thickness Uniformity during HCl Oxidation

Systematic oxide thickness variations across individual wafer surfaces, as well as from wafer to wafer within quartz boats were observed during oxidation. These variations, namely, a radial oxide thinning toward the wafer center and a wafer spacing dependence of average oxide thickness, were associated with the use of during “dry” gate oxidation. The “bull's eye” thickness profile amounted to a 5% variation in a 25.0 nm gate oxide for densely packed (5 mm spacing) wafers. The radial variation disappeared when wafers were spaced far apart (50 mm). The oxide thickness variation was quantitatively correlated to the amount of chlorine incorporated in the oxide where the chlorine content was found to be linearly proportional to the oxide thickness. This oxidation nonuniformity could be modeled by the radial depletion of an active intermediate, chlorine‐containing species during oxidation. While oxides grown in or , did not exhibit a radial thickness variation, those grown in did exhibit thickness variations similar to oxidations. The absolute enhancement of the oxidation rate due to the additions of , , , or in an otherwise dry oxidation was also studied, with alone and alone producing a large enhancement in growth rate (35% thicker oxide for 2.25% or 4.5% additions). The enhancement due to addition was more modest (15% for 2.5% addition). Transients during the switchover in gases, e.g., from during loading to for oxidation, apparently did not play a major role in causing the observed nonuniformities. The use of thick‐oxide “dummy” wafers, grown in a hydrogen‐ or chlorine‐containing atmosphere, between bare silicon wafers had a profound effect on improving thickness uniformity. The oxide thickness variation was reduced when wafers with 0.4 μm dry oxides were interspersed between growing gate oxides; however, this improved oxide uniformity was attributed to a larger spacing between oxidizing wafers. Surprisingly however, variations completely disappeared when the dummy wafers were grown in steam, dry , or dry , suggesting that these dummy wafers play an active role in enhancing the supply of reactive intermediates to adjacent wafers.

Observation of anomalous high resistance to implanted areas caused by reactive ion etching (RIE)

Oxide etching for contact hole definition and sidewall spacer formation is normally performed using fluorocarbon gas mixtures in a plasma reactor. A significant amount of over-etching must be allowed to compensate for uneven oxide thickness and poor process uniformity. During this time underlying silicon material is subjected to energetic particle bombardment which under severe circumstances can induce polymer deposition and radiation damage. Recent results indicate that contacts made to n + and/or p + areas, defined by reactive ion etching, suffer from high resistance which can lower circuit yield. In view of the foregoing, experiments were performed to investigate this phenomena as well as to find a solution whereby the problem of high contact resistance could be circumvented. Reactive ion etching (RIE) was performed in an hexode etcher using CHF 3, O 2 gas mixture at 50 mtorr. Plasma etching was performed in a single wafer etcher using a gas mixture of CHF 3, C 2F 6 and He at 1.5 torr. The as-etched samples were analysed using spreading resistance profiling (SRP), RBS-channeling measurements, ESCA and 4-point probe techniques. These measurements were used to investigate both the presence and the electrical activity of the implanted dopants. The nuclear reaction 1H( 15N, αγ) 12C at 6.38 MeV was employed to profile the hydrogen depth distribution. Cross sectional TEM was performed in order to characterize the extent of the damage. Contact chains defined by dry processing were used for electrical evaluation. It is shown that the silicon surface can be restored after RIE via an in situ low power etch with NF 3. The effectiveness of such a procedure was verified by contact resistance and thermal wave measurements.

Process and Equipment Issues in Rapid Thermal Oxidation (RTO)

ABSTRACTThin oxides with thicknesses in the range of 150 to 300Å were grown on lOO-mm <100> Si wafers in a commercial RTP reactor. Growth temperatures and times were llO0-1200°C for 60-180 seconds in 100% 02 at 1 atmosphere. Oxide thickness uniformity was measured using ellipsometry; contour maps of thickness uniformity will be presented. The standard deviation wascalculated to be 2-2.5% within 5 mm of the edge using a method which weights the area represented by each of 45 data points per wafer. In order to correct for dynamic changes in temperature uniformity, a new annealing method was developed.Results on wafer-to-wafer uniformity will be presented. Improvements achieved by post-oxidation annealing in N2 and electrical uniformity of films will be discussed.