Oxide-semiconductor Interface Research Articles

Dynamic Bias-Temperature Instability Testing in SiC MOSFETs

For power converter development in mission critical applications, the attractive performances of SiC power MOSFETs are shadowed by reliability concerns, particularly those induced by the defects at the gate dielectric. Charge trapping at the oxide-semiconductor interface can lead to threshold voltage drift, degrading the power converter efficiency and lifetime. The scope of this contribution is to show a testing methodology under development to understand SiC power MOSFET threshold voltage stability under dynamic and accelerated operating conditions. The presented testing methodology relies on switching the device under test at high-voltage and current, simultaneously applying a gate stress and extracting threshold voltage from switching transients. The paper outlines the setup description, its operating modes and intended design of experiment to assess SiC MOSFET threshold voltage stability.

Comparative analysis of working principles and applications of MOSFET and HEMT

Semiconductor materials are currently one of the most core materials in the worlds high-tech industry, and the research and development of semiconductor materials is related to the improvement of human technological level. This paper presents a comparative study of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and High Electron Mobility Transistors (HEMTs), two pivotal components in electrical engineering, each with unique characteristics and functions. Despite structural similarities, MOSFETs and HEMTs differ significantly in operation and conduction methods. MOSFETs rely on an inversion layer formed at the semiconductor-oxide interface, controlled by gate voltage, for electron conduction. Conversely, HEMTs utilize a two-dimensional electron gas (2DEG) at the interface of materials like Gallium Nitride and Aluminum Gallium Nitride, offering high electron mobility crucial for performance. Both share similar I-V characteristics but differ in performance under various conditions. MOSFETs are cost-effective, ideal for mass production and general applications, while HEMTs excel in stability and performance in extreme conditions, suitable for high-performance needs. This study underscores the importance of selecting the right component based on application-specific requirements, highlighting MOSFETs for cost-efficiency and HEMTs for challenging environments. This article will provide some guidance for the research of MOSFET and HEMT.

Analysis of metal and zinc oxide semiconductor interface resistance using transmission line method

The transmission line method (TLM) is modified to analyze the contact resistance between the metal and zinc oxide semiconductor considering interface resistance. TCAD is used to simulate an ideal defect-less state and compare it with experimental result. It is found that the current transfer length can be overestimated in conventional TLM measurement. The importance of interface resistance is shown through interface trap and Schottky contact effect analysis: Resistance comparison between different metal used device, and the activation energy shift measurement after O2 pre-annealing. Based on these, the conventional resistance equation for TLM is corrected by separating channel resistance and non-ideal contact resistance. The mobility and temperature coefficient of resistance (TCR) of ZnO channel are extracted using the suggested method. This shows the importance of metal/semiconductor interface resistance in devices using semiconductor channel.

Effect of Temperature-Dependent Low Oxygen Partial Pressure Annealing on SiC MOS.

Oxygen post annealing is a promising method for improving the quality of the SiC metal oxide semiconductor (MOS) interface without the introduction of foreign atoms. In addition, a low oxygen partial pressure annealing atmosphere would prevent the additional oxidation of SiC, inhibiting the generation of new defects. This work focuses on the effect and mechanism of low oxygen partial pressure annealing at different temperatures (900-1250 °C) in the SiO2/SiC stack. N2 was used as a protective gas to achieve the low oxygen partial pressure annealing atmosphere. X-ray photoelectron spectroscopy (XPS) characterization was carried out to confirm that there are no N atoms at or near the interface. Based on the reduction in interface trap density (Dit) and border trap density (Nbt), low oxygen partial pressure annealing is proven to be an effective method in improving the interface quality. Vacuum annealing results and time of flight secondary ion mass spectrometry (ToF-SIMS) results reveal that the oxygen vacancy (V[O]) filling near the interface is the dominant annealing mechanism. The V[O] near the interface is filled more by O2 in the annealing atmosphere with the increase in temperature.

Influence of silicon characteristics on the parameters of manufactured photonics cells

The paper investigates the influence of the electrophysical characteristics of silicon on the final parameters of photoelectronic elements using p-i-n photodiodes as an example. It has been found that photodiode samples made on the basis of silicon with a higher resistivity are more prone to the formation of inversion channels at the oxide-semiconductor interface. Also, the dark current and responsivity of such photodiodes reach saturation at a lower voltage. It has also been shown that silicon-based photodiodes with a longer lifetime of non-basic charge carriers have lower dark current values. It has been shown that products with crystallographic orientation [111] have a much lower density of surface dislocations after technological operations than in the case of silicon with orientation [100]. It was also found that materials with different crystallographic orientations have different phosphorus diffusion coefficients. It has been experimentally established that a silicon oxide film grows faster on the surface of crystallographic orientation silicon [111] than on the surface of crystallographic orientation silicon [100]. This is due to the difference in the surface density of silicon atoms inherent in different crystallographic planes.

Tuning of SiO2/Si interface by a hybrid plasma process combining oxidation and atom-migration

As a common oxide-semiconductor interface, SiO2/Si plays an important role in silicon-based electronics and optoelectronics. In order to effectively obtain an ultra-smooth and thin SiO2/Si interface, a hybrid tuning process based on inductively coupled plasma (ICP) was proposed, which combined oxidation (plasma-OX) and atom-migration manufacturing (plasma-AMM). In plasma-OX process, a thick oxide film was rapidly prepared on Si wafer surface in 2 min, which included a SiO2 layer on the top and a SiOx (x < 2) layer between the top layer and the bulk crystalline silicon (c-Si). In subsequent plasma-AMM process, ICP steadily delivered energy to the Si wafer surface and induced the migration of unsaturated Si from SiOx layer to c-Si, which enhanced the crystallization of silicon wafer. The roughness of SiO2/Si interface was reduced to Sa 0.171 nm at 620 W in 5 min. However, a 2–3 nm thickness SiOx layer still existed, and several defects causing by residual thermal stress can be observed. Further optimizing plasma-AMM process by setting multi-step slow cooling, the SiOx layer can be almost completely decomposed. The interface roughness Sa was reduced to <0.1 nm and the interface thickness was reduced to 1–2 atom layer. Both OX and AMM process were conducted in the same setup, which is convenient for switching. This study proposed and demonstrated the feasibility of a hybrid plasma tuning process, which provided an efficient tuning technology at atomic level for semiconductor interface.

Quantifying the Impact of Al Deposition Method on Underlying Al2O3/Si Interface Quality

Oxide–semiconductor interface quality has often a direct impact on the electrical properties of devices and on their performance. Traditionally, the properties are characterized through metal–oxide–semiconductor (MOS) structures by depositing a metal layer and measuring the capacitance–voltage (C–V) characteristics. However, metal deposition process itself may have an impact on the oxide and the oxide–semiconductor interface. The impact of magnetron sputtering, e‐beam evaporation, and thermal evaporation on an interface is studied, where atomic layer deposited (ALD) is used, by MOS C–V and corona oxide characterization of semiconductors (COCOS) measurements. The latter allows characterization of the interface also in its original state before metallization. The results show that sputtering induces significant damage at the underlying interface as the measured interface defect density increases from to cm−2 eV. Interestingly, sputtering also generates a high density of positive charges at the interface as the charge changes from to cm. Thermal evaporation is found to be a softer method, with modest impact on and . Finally, Alnealing heals the damage but has also a significant impact on the charge of the film recovering the characteristic negative charge of (∼−4 × 1012 cm).

Simulation of 1/f charge noise affecting a quantum dot in a Si/SiGe structure

Due to presence of magnetic field gradient needed for coherent spin control, dephasing of single-electron spin qubits in silicon quantum dots is often dominated by 1/f charge noise. We investigate theoretically fluctuations of ground state energy of an electron in gated quantum dot in a realistic Si/SiGe structure. We assume that the charge noise is caused by motion of charges trapped at the semiconductor–oxide interface. We consider a realistic range of trapped charge densities, ρ ∼1010 cm−2, and typical lenghtscales of isotropically distributed displacements of these charges, δr≤ 1 nm, and identify pairs (ρ,δr) for which the amplitude and shape of the noise spectrum are in good agreement with spectra reconstructed in recent experiments on similar structures.

Correlations of spin splitting and orbital fluctuations due to 1/f charge noise in the Si/SiGe quantum dot

Fluctuations in electric fields can change the position of a gate-defined quantum dot (QD) in a semiconductor heterostructure. In the presence of magnetic field gradient, these stochastic shifts of electron's wavefunction lead to fluctuations of electron's spin splitting. The resulting spin dephasing due to charge noise limits the coherence times of spin qubits in isotopically purified Si/SiGe quantum dots. We investigate the spin splitting noise caused by such a process due to microscopic motion of charges at the semiconductor-oxide interface. We compare effects of isotropic and planar displacement of the charges and estimate their densities and typical displacement magnitudes that can reproduce experimentally observed spin splitting noise spectra. We predict that for a defect density of 1010 cm−2, visible correlations between noises in spin splitting and in energy of electron's ground state in the quantum dot are expected.

Density-Functional Study of the Si/SiO2 Interfaces in Short-Period Superlattices: Structures and Energies

The oxide-semiconductor interface is a key element of MOS transistors, which are widely used in modern electronics. In silicon electronics, SiO2 is predominantly used. The miniaturization requirement raises a problem regarding the growing of heterostructures with ultrathin oxide layers. Two structural models of interface between crystalline Si and cristobalite SiO2 are studied by using DFT-based computer modelling. The structures of several Si/SiO2 superlattices (SL), with layer thicknesses varied within 0.5–2 nm, were optimized and tested for stability. It was found that in both models the silicon lattice conserves its quasi-cubic structure, whereas the oxide lattice is markedly deformed by rotations of the SiO4 tetrahedra around axes perpendicular to the interface plane. Based on the analysis of the calculated total energy of SLs with different thicknesses of the layers, an assessment of the interface formation energy was obtained. The formation energy is estimated to be approximately 3–5 eV per surface Si atom, which is close to the energies of various defects in silicon. Elastic strains in silicon layers are estimated at 5–10%, and their value rapidly decreases as the layer thickens. The elastic strains in the oxide layer vary widely, in a range of 1–15%, depending on the interface structure.

Phosphorus diffusion and deactivation during SiGe oxidation

Dopant profiles near the semiconductor–oxide interface are critical for microelectronic device performance. As the incorporation of Si1−xGex into transistors continues to increase, it is necessary to understand the behavior of dopants in Si1−xGex. In this paper, the diffusion and electrical activation of phosphorus within a strained, single-crystal Si0.7Ge0.3 layer on Si during oxidation are reported. Both layers were uniformly doped, in situ, with an average phosphorus concentration of 4 × 1019 atoms/cm3. After high-temperature oxidation, secondary ion mass spectrometry measurements revealed that the bulk of the phosphorus diffuses out of only the SiGe layer and segregates at the oxidizing SiGe–SiO2 interface. Hall effect measurements corroborate the observed phosphorus loss and show that the phosphorus diffusing to the oxidizing interface is electrically inactive. Through density functional theory (DFT) calculations, it is shown that phosphorus interstitials prefer sites near the SiGe–SiO2 interface. Finally, based on a combination of experimental data and DFT calculations, we propose that the phosphorus atoms are displaced from their lattice sites by Ge interstitials that are generated during SiGe oxidation. The phosphorus atoms then migrate toward the SiGe–SiO2 interface through a novel mechanism of hopping between Ge sites as P–Ge split interstitials. Once they reach the interface, they are electrically inactive, potentially in the form of interstitial clusters or as part of the reconstructed interface or oxide.

New Insights Into Noise Characteristics of Hot Carrier Induced Defects in Polysilicon Emitter Bipolar Junction Transistors and SiGe HBTs

Low frequency (LF) noise is a powerful and nondestructive technique for evaluating the oxide-semiconductor interface and an effective evaluating tool in characterizing electronic device’s structure and reliability. In this study, we present a systematic analysis of the striking abnormal 1/f noise behavior of the hot carrier induced defects in highspeed polysilicon emitter bipolar transistors (PE-BJTs) and SiGe HBTs. Here, the comparative results before and after hot carrier degradation reveal that low frequency noise spectra are not correlated with the density and distribution of the interfacial defects, which related to Si dangling bonds reside at the SiO2/Si interface in PE-BJTs and SiGe HBTs.

Investigation on performance degradation due to induced interface trapped charges on HSO based FDSOI NCFET and sustaining it through back-gate bias

In this article, a variant of doped HfO2 based ferroelectric capacitor i.e. silicon doped HfO2 (hafnia-silica/HSO) is investigated for analytical feasibility and viability for negative capacitance FET (NCFET) applications. Investigations are carried out extensively using well calibrated and validated numerical simulations to find out the optimum ferroelectric thickness (tf) of HSO thin-film for the NCFET to operate in hysteresis-free regime. The optimized NCFET is then subjected to the variation of back-gate bias (V ) to exploit threshold-voltage () shift phenomena might further improve NCFET performance. In continuance, the optimized NCFET has been introduced with interface trap (+Nit) charges at the oxide–semiconductor interface to emphasize on the reliability deflation caused at process level design. Hence, this has allowed us to concisely observe and analyse performance degradation aspect of the NCFET with numerical simulations. Also, a feasibility to recuperate the degraded performance caused by +Nit with utilizing −V is carried out. The performance metrics used in the numerical simulation for the evaluation of HSO ferroelectric NCFET are: sub-threshold slope, charge variation with gate-voltage and ferro voltage, surface potential, , drain-current and amplification factor.

Drift–diffusion-Poisson- dual phase lag thermal model with phonon scattering in gate all around field effect transistor

• Phonon scattering effect on Self-heating transistor are investigated. • The impact of temperature-dependent properties are discussed. • A reduction of temperature rise is achieved by using jump boundary condition. • A decrease in temperature is obtained using a temperature-dependent parameters. Gate All Around Field Effect Transistor (GAAFET) is a promising alternative for improving channel control, reducing leakage currents, and bringing down the operational voltage and dynamic power. In the present work, we will attempt to address the self-heating effect in (GAAFET) structure. The finite element approach is used to discretize the Dual-Phase Lag (DPL) heat conduction equation coupled with Poisson and drift-diffusion equations for electrons and holes is performed using the finite element method. Numerical solutions are obtained using the technique of nonlinear Newton–Raphson iteration. This study is also aims to analyze the impact of temperature-dependent (TD) parameters such as thermal conductivity, heat flux phase lag, and volumetric heat capacity on temperature distribution. Further, a temperature jump boundary condition is used at the semiconductor-oxide interface to take into account the phonon scattering phenomenon. In comparison to the constant parameters, the obtained results reveal a decrease in the temporal temperature profile as well as the spatial temperature distribution. Also, the addition of jump boundary conditions causes a reduction in the maximum temperature and heat flux. Thus, the DPL model with proposed TD parameters, including jump temperature boundary condition, is recommended for the investigation of the self-heating effect, which can provide some improvement for the development of GAAFET with good reliability in the device.

Impact of unpreventable induced interface trapped charges on HZO based FDSOI NCFET

In this paper, the effect of oxide-semiconductor interface trapped charges on the performance of 22-nm Fully Depleted Silicon on Insulator (FDSOI) Negative Capacitance FET (NCFET) has been systematically investigated. Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) type NCFET with zirconium doped HfO2 (HZO) as the ferroelectric material is considered for this work. The simulation of the underlying Metal-Insulator-Semiconductor (MIS) structure has been carried out in a well-calibrated TCAD environment to extract the gate charge. Which is subsequently used to solve 1D Landau-Khalatnikov (1D-LK) model to find the voltage across ferroelectric capacitor. The presence of trap charges is unavoidable in modern devices, which affects the charge balance equation as well as the performance & reliability of the device. NCFET being one of the potential candidates to be adopted by industry for ultra-low power applications in the future according to the International Roadmap for Devices and Systems (IRDS), investigation of trap charges becomes crucial. Due to its multilayer stacking, the transfer characteristics are analyzed for various ferroelectric thicknesses with exhibition of an intersection point, which is demonstrated for the first time. Simulation of variation of device performance metrics like minimum sub-threshold swing (min. SS), transconductance (gm), off-state drain current (Ioff) & amplification factor (AV) are analyzed and compared for various interface trapped charge densities. It is predicted that the device performance either enhances or degrade depending on the type of trapped charges present.

Valley Splitting in Silicon from the Interference Pattern of Quantum Oscillations.

We determine the energy splitting of the conduction-band valleys in two-dimensional electrons confined in silicon metal oxide semiconductor Hall-bar transistors. These silicon metal oxide semiconductor Hall bars are made by advanced semiconductor manufacturing on 300mm silicon wafers and support a two-dimensional electron gas of high quality with a maximum mobility of 17.6×10^{3} cm^{2}/Vs and minimum percolation density of 3.45×10^{10} cm^{-2}. Because of the low disorder, we observe beatings in the Shubnikov-de Haas oscillations that arise from the energy splitting of the two low-lying conduction band valleys. From the analysis of the oscillations beating patterns up to T=1.7 K, we estimate a maximum valley splitting of ΔE_{VS}=8.2 meV at a density of 6.8×10^{12} cm^{-2}. Furthermore, the valley splitting increases with density at a rate consistent with theoretical predictions for a near-ideal semiconductor-oxide interface.

Parametric investigation and trap sensitivity of n-p-n double gate TFETs

This article reports an architecture of a silicon-on-insulator (SOI) tunnel field effect transistor (TFET) possessing an n-p-n body, where the two p-n junctions serve as the primary tunneling sites. The p-type source region is elevated allowing two gate structures to modulate the bands over the two junctions, thus forming a double gate structure. The architecture is optimized in terms of doping concentration, and geometrical dimensions defined in analogy with the conventional geometry of TFET through calibrated simulations using industrial technology computer aided design (TCAD) tool. The article further incorporates three gate engineering techniques to the n-p-n architecture to improve the electrical performance. The trap sensitivity of the architectures is reported for concentration, and energy positions of acceptor-like and donor-like traps at the semiconductor-oxide interface. Additionally, the impact of trap-assisted tunneling on the device characteristics is examined.

Investigation of AlGaN/GaN HEMT for pH sensing applications and sensitivity optimization

In this work, AlGaN/GaN HEMT pH sensitive response has been presented through extensive simulations demonstrating the effect of pH variation on channel conductance, potential and conduction band profile. The pH solution is defined by an intrinsic semiconductor material whose properties are modified to mimic electrolyte solution and the effect of variation in charged adsorbates is accommodated by adjusting the interface charges density at oxide-semiconductor interface. The effect of AlGaN barrier layer composition (thickness and Aluminum mole fraction) on the sensitivity was analyzed by simulating different device configurations using ATLAS Silvaco device simulation tool. The devices render improved voltage sensitivity (SV = ΔVr/pH) and high output current sensitivity (SI = (ΔIds/pH) = 15 mA/mm-pH). The simulations predict a thinner barrier layer along with smaller mole fraction device is most sensitive to pH changes at the surface for an open gate operation.

Electronically induced defect creation at semiconductor/oxide interface revealed by time-dependent density functional theory

Carrier induced defect creation at the semiconductor-oxide interface has been known as the origin of electronic device degradation for a long time, but how exactly the interface lattice can be damaged by carriers (especially low-energy ones) remains unclear. Here we carry out real-time time-dependent density functional theory simulations on concrete $\mathrm{Si}/\mathrm{Si}{\mathrm{O}}_{2}$ interfaces to study the interaction between excited electrons and interface bonds. We show that the normal interface Si-H bonds are generally resistant to electrons due to the delocalized nature and high energy level of the Si-H antibonding states, and due to the high-energy barrier to break the Si-H bond. However, if an additional hydrogen atom exists by attaching to a nearby oxygen atom (forming a ``Si-H\ifmmode\cdot\else\textperiodcentered\fi{}\ifmmode\cdot\else\textperiodcentered\fi{}\ifmmode\cdot\else\textperiodcentered\fi{}H-O'' complex), the Si-H bond will be greatly weakened, including the reduction of energy barrier for bond breaking, and the lowering of the antibonding state energy level which favors electron injection. Together with the multiple vibrational excitation process, the corresponding Si-H bond can be broken much more easily. Thus we propose that the Si-H\ifmmode\cdot\else\textperiodcentered\fi{}\ifmmode\cdot\else\textperiodcentered\fi{}\ifmmode\cdot\else\textperiodcentered\fi{}H-O complex will be the center for defect creation and device degradation. We also explain why such a center might be relatively easy to form during the hydrogen annealing process.

AlGaN/GaN HEMT pH Sensor Simulation Model and Its Maximum Transconductance Considerations for Improved Sensitivity

In this work, AlGaN/GaN high electron mobility transistor (HEMT) pH sensing simulation model is presented along with the sensitivity analysis to different pH values of an electrolyte by considering charged adsorbates systematically. Investigations were performed by studying the effect of pH values on device transfer characteristics and a smooth operation is observed with good pH resolution. The output current sensitivity is analyzed from both linear and saturation regions highlighting the response obtained at different drain bias. The device intricacies and sensing mechanism is also explained and demonstrated by analyzing the channel conductance, conduction band, potential profile and coupling capacitance along with the charge distribution profile at various interfaces using ATLAS Silvaco device simulation tool. The pH of solution is modelled by incorporating charged adsorbates as interface charge density at oxide-semiconductor interface in HEMT for the first time to best of our knowledge. The voltage sensitivity (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</sub> ) of 110 mV/pH was observed which is ~2 times beyond Nernst limit of sensitivity (59 mV/pH) and the current sensitivity (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</sub> ) is 17 mA/mm/pH which is 3 orders higher than silicon based devices. The effects of region of operation is also reported with a maximum upto 8 times higher sensitivity being observed in terms of maximum transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) considerations and a near zero maximum g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> was found to be optimum condition for higher sensitivity operation in reference electrode free configuration. Therefore high sensitive response along with better biocompatibility of AlGaN/GaN HEMT paves its way in next generation biosensing applications.