Oxide Semiconductor Heterostructure Field Effect Research Articles

Effect of rapid thermal annealing on DC performance of Mg0.30Zn0.70O/Cd0.15Zn0.85O MOSHFET

This study focuses on a cost-effective method for fabrication of a metal oxide semiconductor-heterostructure field effect transistor (MOSHFET) based on MgZnO/CdZnO (MCO) using dual ion beam sputtering (DIBS), in contrast to the more expensive epitaxial growth system. The MOSHFETs developed in this research exhibit notable characteristics, such as a substantial two-dimensional electron gas (2DEG) transconductance (∼2.6 mS), a high ION/IOFF response ratio in the order of 108, and minimal gate leakage current. Furthermore, we explore the impact of rapid thermal annealing (RTA) on the drain current at various temperatures (600 °C and 800 °C). The results indicate a fourfold improvement in drain current compared to unannealed conditions, primarily attributed to reduced contact resistance and no degradation in term of MgZnO/CdZnO structure. Additionally, an analysis of post-RTA treatment under a nitrogen (N2) atmosphere on gate leakage current is presented. The investigation spans temperatures ranging from 400 °C to 800 °C, revealing that above 600 °C (gate leakage at 400 °C–600 °C is around ∼10−9 A), gate leakage in HFET is augmented by one order of magnitude (∼10−8 A) due to a phase change in the dielectric. These findings underscore the feasibility of DIBS-grown MCO MOSHFETs as an economical solution for the mass production of switching devices and sensors.

Temperature Effect on Performance of Enhancement Mode Al0.4Ga0.6n-Channel Moshfets with Hybrid Oxide

The metal oxide semiconductor heterostructure field effect transistors (MOSHFETs) based on AlxGa1-xN materials with the high aluminum composition is a promising choice for high-power, high-temperature harsh environment applications. In the present work the temperature stability of MOSHFETS with high-k ZrO2, Al2O3 gate dielectrics has been studied. Our data show these high-k dielectrics introduce negative fixed charges (Qox) as high as 1-3×1013 cm-2 depleting 2DEG density of 2×1013 cm-2 causing a positive shift of threshold voltage (VTH) compared to that for HFET which is an important feature for realizing enhanced (E-) mode MOSHFET. ZrO2 possesses higher Qox resulting in stronger positive VTH shift in devices, while devices with Al2O3 demonstrate lower gate leakage. To take advantages of both oxides, UWBG Al0.4Ga0.6N channel E-mode MOSHFET has been fabricated. E-mode device was realized using the hybrid oxide (ZrO2/Al2O3) combined with gate recess. To separate effects of dielectric charges and damage from recess process on device performance depletion (D-) mode and E-mode devices were fabricated on the same wafer simultaneously. D-mode devices were protected during gate recess step to avoid additional damage. Thermally induced VTH instability of these MOSHFETs were studied and potential mechanism for this VTH instability is discussed. Experimental: Figure 1(a) shows the pseudomorphic device structure that was grown using metalorganic chemical vapor deposition on AlN/sapphire templates. A graded composition (AlxGa1-xN, x=1-0.4) back barrier reduces internal stress and improves gate control in the devices.[i] , [ii] The top 200 Å thick graded n-AlxGa1-xN (x from 0.6 to 0.3) layer assists with the formation of ohmic contacts resistance as low as 1.7 Ω-mm. The n-doping of this layer compensates the positive charges resulting from the reverse composition grading.[iii] The 2DEG sheet resistance was ~1900 ohm/□. Device processing details published elsewhere.[iv] The fixed gate-length LG ≈ 2.0 μm, source to drain spacing, LSD=6 μm, were used for regular devices with 15 μm channel width, while for precise C(V,T,f) measurements we use a test structure with gate area 200x80 μm2 . Results and discussion: The combination of gate recessing and hybrid oxide resulted in threshold-voltage (VTH) shift of +12.2 V from D to E-mode device (Figure 1(b)). The gate leakage current in both D and E-mode MOSHFETs is ~103 smaller than that of MOSHFETs using singe Al2O3 or ZrO2 layer (Figure 2(a)) which allows us to apply gate voltage as high as +12 V. The peak DC currents for D and E-mode devices were found to be 1.1 A/mm and 0.48 A/mm respectively while in the pulse mode it was 1.3 A/mm and 0.53 A/mm. ON/OFF ratio as high as 3×108 was achieved which is higher than ~2 orders of magnitude than that for Al2O3 or ZrO2. We then performed temperature dependent threshold and gate leakage study of our fabricated MOSHFETs. Figure 2(b) shows the temperature dependent gate leakage characteristics of MOSHFETs of this study. It has been found that, in the D-mode MOSHFET, the VTH experiences positive VTH shift of + 1.7 V from RT to 150 °C; for the E-mode MOSHFET the shift is negative: -2.9 V (Figure 3(a)). The VTH shift for similar device having Schottky gate (no dielectric) (HFET) is significantly smaller, +0.2 V. This shows that the VTH shift is mainly due to the charges in dielectric or at dielectric-barrier interface. In the E-mode devices, the effective channel mobility and VTH was additionally affected by radiative defects introduced during gate-recess step. The mobility (µ) in D-mode devices decreases with temperature while it increases for the E-mode devices. We estimated temperature dependent interface state density (DIT(T)) and Qox (T) using frequency- dependent C-V measurements as shown in Figure 3(b). Our analysis show that in D-mode device, Qox(T) dominates over interface charges. These are fixed negative charges which deplete the channel giving a total VTH shift of +1.7 V from RT to 150°C. The extracted SS value for D and E-mode devices were 99 mV/decade and 134 mV/decade, indicating an increased density of interface traps (DIT) at the recessed interface in the E-mode device. Larger DIT value in E-mode devices caused by a radiation damage from the barrier recessing process and becomes comparable with Qox. Thus the temperature effect on Qox is compensated by DIT changes, increasing SS and making the VTH(T) more negative.[i]) G. Simin et al., Jpn. J. Appl. Phys., 40, L1142 (2001).[ii]) C. Ren et al., J. Semicond. 36, 014008-1 (2015).[iii]) S. Bajaj et al., Appl. Phys. Lett. 109, 133508-1 (2016).[iv]) S. Mollah et al., Appl. Phys. Lett. 117, 232105 (2020). Figure 1

An Extensive Simulation Study of Gate Underlap Influence on Device Performance of Surrounding Gate In0.53Ga0.47As/InP Hetero Field Effect Transistor

Background: This work describes the implementation of In0.53Ga0.47As/InP Surrounding Metal Gate Oxide Semiconductor Heterostructure Field Effect Transistor (SG MOSHFET) with gate underlap on both source and drain end to improve the DC and RF performance. Methods: A comprehensive and methodological investigation of DC and RF performance of III-V semiconductor are made for different underlap length varying from 5nm to 30nm on both sides of the device, which is used to mitigate the short channel issues to improve the device performance. Hydrodynamic model has been taken into consideration for the device simulation and it also includes Auger recombination and the Shockley–Read–Hall (SRH) model. Simulation is performed to analyze the various analog performance of device like drain current, surface potential, transconductance, threshold voltage, drain induced barrier lowering, off current, subthreshold slope, Ion/Ioff ratio, output conductance, intrinsic delay, energy-delay product, transconductance generation factor and radio frequency performance of device, like trans-frequency product and cut-off frequency. Results: From the simulation, it can be observed that an improved analog and RF performance is obtained at the optimum underlap length. Conclusion: This work delivers an idea for extended researchers to investigate different aspects of group III–V underlap MOSFETs.

High‐Temperature Operation of AlxGa1−xN (x > 0.4) Channel Metal Oxide Semiconductor Heterostructure Field Effect Transistors with High‐k Atomic Layer Deposited Gate Oxides

Due to their superior breakdown fields compared with GaN and SiC and high thermal conductivity, AlxGa1−xN (x > 0.4) channel high‐electron‐mobility transistors (HEMTs) will find applications in extreme environments such as power electronics. Herein, the high‐temperature operation of ultrawide‐bandgap (UWBG) Al0.65Ga0.35N/Al0.4Ga0.6N metal oxide semiconductor heterostructure field effect transistors (MOSHFETs) with atomic layer‐deposited (ALD) high‐k gate dielectrics TiO2, Al2O3, and ZrO2 is reported. As compared with similar geometry HFETs, these devices exhibit a simultaneous reduction in gate‐leakage current by ≈104 and a positive shift of the threshold voltage as much as 4 V. This positive threshold shift indicates the introduction of negative charges at the oxide/barrier interface and within the thin oxide, attributed to the pre‐ALD plasma treatment. The gate leakage increases weakly with temperature up to 250 °C, whereas the peak drain currents decrease from ≈0.5 to 0.3 A mm−1. An analysis of the C–V and I–V characteristics reveals that this drain current decrease is due to a reduction in channel electron mobility. The potential mechanisms responsible for this are discussed. Up to the measured temperature of 250 °C, the devices withstand repeated temperature cycles without catastrophic degradation or breakdown, underscoring the promise of these materials.

Effect of barrier recess on transport and electrostatic interface properties of GaN-based normally-off and normally-on metal oxide semiconductor heterostructure field effect transistors

We perform a comprehensive electrical transport and physical characterization of metal oxide semiconductor heterostructure field effect transistors with ZrO2 gate dielectrics, having partially (referred here as MOS-HFET) and fully (here called true-MOS-FET) recessed GaN/AlGaN/GaN barrier, giving normally-on and normally-off behavior, respectively. The mobility of the MOS-HFETs decreases with the proximity of the Coulomb scattering centers, situated at the ZrO2/AlGaN interface. The effect of the etching procedure and ZrO2 deposition on the formation of the interfacial charges, Nint, is evaluated by X-ray Photoelectron Spectroscopy and by fitting the threshold voltage values to numerical model. For the both device types, the extracted value of Nint lies within 15% around 2.8×1013cm−2, which is of the order of polarization charge, showing that our low-damage three step etching procedure does not introduce extra interface states.

ZrO2/InAlN/GaN Metal–Oxide–Semiconductor Heterostructure Field-Effect Transistors with InAlN Barrier of Different Compositions

We report on InAlN/GaN heterostructure metal–oxide–semiconductor field-effect transistors (MOSHFETs) with an InAlN barrier layer of different compositions (xInN = 13, 17, and 21%) and ZrO2 gate-insulator/passivation. Static measurements yielded higher drain currents than those on unpassivated HFET counterparts and the currents increased with decreased xInN. Post deposition annealing of the ZrO2 insulator had less influence on the static performance but remarkable changes were observed on the capacitance–voltage characteristics. The capacitance hysteresis in both channel depletion and barrier accumulation regions was significantly suppressed after annealing. This indicates a reduction of the interfacial trap states and of fixed charge in the oxide. Pulsed current–voltage measurements confirmed this conclusion – the gate lag of only ∼80% was evaluated for 200 ns pulse width, independently on the composition of the InAlN barrier layer. These results support an application of high permittivity ZrO2 gate-insulator/passivation for the preparation of high-performance InAlN/GaN MOSHFETs.

Normally-Off AlGaN/GaN Metal–Oxide–Semiconductor Heterostructure Field-Effect Transistor with Recessed Gate and p-GaN Back-Barrier

Normally-Off AlGaN/GaN Metal–Oxide–Semiconductor Heterostructure Field-Effect Transistor with Recessed Gate and p-GaN Back-Barrier

Normally-Off AlGaN/GaN Metal–Oxide–Semiconductor Heterostructure Field-Effect Transistor with Recessed Gate and p-GaN Back-Barrier

The recessed-gate AlGaN/GaN metal–oxide–semiconductor heterostructure field-effect transistors (MOSHFETs) with a p-GaN back-barrier studied in this work exhibited much lower buffer leakage current than those without the back-barrier. The threshold voltage of the device with the p-GaN back-barrier was controlled by varying the depth of gate recess etching, and a value as high as 2.9 V was obtained with deep gate-recess etching into the channel layer. The device structure has the advantage of both low leakage current and high threshold voltage, which is important for power-switching applications. In contrast, the performance parameters of the device, such as subthreshold slope and field-effect mobility, can be degraded owing to increased plasma damage with increasing recess depth.

Oxidized Al Film as an Insulation Layer in AlGaN/GaN Metal–Oxide–Semiconductor Heterostructure Field Effect Transistors

We report on the technology of a very thin oxidized Al sputtered film used for gate insulation and passivation in Al2O3/AlGaN/GaN metal–oxide–semiconductor heterostructure field-effect transistors (MOSHFETs). Their transport properties are presented. The MOSHFET with the Al2O3 layer had improved static output and transfer characteristics compared with the reference heterostructure field-effect transistors (HFETs): (1) their saturation drain current IDS was ∼600 mA mm-1 at gate voltage VG=1 V (HFETs with 2.5 µm gates had ∼430 mA mm-1); (2) their transconductance was 116–140 mS mm-1 (HFETs had ∼70 mS mm-1).

Si–Ge interdiffusion under oxidizing conditions in epitaxial SiGe heterostructures with high compressive stress

Si–Ge interdiffusion under oxidizing and inert conditions has been studied in epitaxial relaxed Si1−xGex/compressive Si1−yGey/relaxed Si1−xGex heterostructures. The interdiffusion was measured by secondary ion mass spectroscopy (SIMS) and studied using simulations. Within the SIMS accuracy, the measured Ge profiles show that oxidation has a small effect, if any, on the Si–Ge interdiffusion of these structures. These results suggest that oxidation does not accelerate Si–Ge interdiffusion significantly, which lessens process integration constraints for SiGe devices such as high mobility dual channel metal oxide semiconductor field effect transistors and heterostructure tunneling field effect transistors.

Determination of the average channel temperature of GaN MOSHFETs under continuous wave and periodic-pulsed RF operational conditions

We present a method to determine the average device channel temperature of AlGaN/GaN metal–oxide–semiconductor heterostructure field effect transistors (MOSHFETs) in the time domain under continuous wave (CW) and periodic-pulsed RF (radiation frequency) operational conditions. The temporal profiles of microwave output power densities of GaN MOSHFETs were measured at 2GHz under such conditions and used for determination of the average channel temperature. The measurement technique in this work is also being utilized to determine the thermal time constant of the devices. Analytical temporal solutions of temperature profile in MOSHFETs are provided to support the method. The analytical solutions can also apply to generic field effect transistors (FETs) with an arbitrary form of time-dependent heat input at the top surface of the wafer. It is found that the average channel temperature of GaN MOSHFETs on a 300μm sapphire substrate with the output power of 10W/mm can be over 400°C in the CW mode while the average channel temperature of GaN MOSHFETs on a SiC substrate with the same thickness only reaches 50°C under the same condition. The highest average channel temperature in a pulsed RF mode will vary with respect to the duty cycle of the pulse and type of the substrate.

Noise Analysis of Nitride-Based Metal–Oxide–Semiconductor Heterostructure Field Effect Transistors with Photo-Chemical Vapor Deposition SiO2 Gate Oxide in the Linear and Saturation Regions

Low frequency noise of AlGaN/GaN metal–oxide–semiconductor heterostructure field effect transistors (MOS-HFETs) with photo-chemical vapor deposition (photo-CVD) SiO2 gate oxide was investigated as functions of gate bias (from Vgs=-6 to 4 V) both in the linear (Vds=3 V) and saturation (Vds=12 V) regions. In the linear region, it was found the measured noise spectra were fitted well by the 1/ f law up to 1 kHz. The normalized noise power density of the MOS-HFETs was proportional to Vgs-1 when -4<Vgs<0 V, and was independent of the gate voltage when 0<Vgs<4 V. The Hooge's coefficient α was estimated to be around 10-3. In the saturation region, it was found that the measured noise power density decreased monotonically with the increase of gate voltage.

Room temperature photo‐CVD SiO2 layers on AlGaN and AlGaN/GaN MOS‐HFETs

AbstractHigh quality SiO2 layers were successfully deposited onto AlGaN by photo‐chemical vapor deposition (photo‐CVD) using D2 lamp as the excitation source at room temperature. The resulting interface state density was only 8.86 × 1011 cm–2 eV–1. With a 2 µm gate, it was found that maximum drain–source current, maximum transconductance (gm,max) and gate voltage swing (GVS) of the fabricated nitride‐based metal–oxide–semiconductor heterostructure field effect transistors (MOS‐HFETs) were 225 mA/mm, 33 mS/mm and 6.5 V, respectively. Compared with metal‐semiconductor HFETs (MES‐HFETs), it was found that noise power density of MOS‐HFETs was lower and presented pure 1/f noise with smaller trapping effects. (© 2006 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

AlGaN/GaN MOSHFET with a SiO2 Gate by Liquid Phase Deposition

An efficient and low cost approach for depositing uniform silicon dioxide layers on GaN by liquid phase deposition (LPD) that is near room temperature will be described. The self-align and self-passivation process of LPD can ease the device fabrication. AlGaN/GaN metal oxide semiconductor heterostructure field effect transistors (MOSHFETs) with liquid phase deposited SiO2 as the insulating gate are demonstrated. Comparison between the AlGaN/GaN MOSHFETs and heterostructure field effect transistors (HFETs) will be made. Lower leakage currents, larger gate swing voltages and flatter transconductance ranges can be seen in MOSHFETs.

First AlGaN/GaN MOSFET with photoanodic gate dielectric

We present the first GaN based MOSFET with wet chemical processed gate oxide. The oxide was grown photoelectrochemically (PEC) in KOH based aqueous solutions and was determined to be Al x Ga 2− x O 3. This process offers low surface damage. The gate contact for our created PEC-MOSHFET (metal oxide semiconductor heterostructure field effect transistor) was fabricated by e-beam evaporation of tungsten on the Al x Ga 2− x O 3 layer, followed by a lithographic step and wet etch by H 2O 2. Source and drain contacts were placed by the liftoff technique using Ti/Al. Peak values for the mutual conductance ( g m) are 64 mS mm −1 for MOVPE (metalorganic vapour pressure epitaxy) structures with 2DEG mobility of 190 cm 2 V −1 s −1. We achieve a maximum drain current I Dmax of 540 mA mm −1 for the PEC-MOSHFET. The results obtained for transistor operation are compared to other gate dielectrics such as SiO 2 with different pre-treatments and to a conventional HFET with a Ni/Au Schottky gate. Depletion starts at threshold voltages V th of −4 V in the case of the PEC-MOSHFET, for the conventional HFET structure V th is about −9 V and for the SiO 2-MOSHFETs it varies between −11.5 and −14 V depending on the wet chemical pre-treatment. Leakage currents depend on device isolation and on gate currents, which are lowest for the SiO 2-MOSHFETs (∼2 pA) and several orders of magnitude bigger for the HFET (∼4 μA). Gate currents for the PEC-MOSHFET depend on the oxide growth and vary between microamperes and a few picoamperes.

LOW-FREQUENCY NOISE IN AlGaN/GaN HETEROSTRUCTURE FIELD EFFECT TRANSISTORS AND METAL OXIDE SEMICONDUCTOR HETEROSTRUCTURE FIELD EFFECT TRANSISTORS

The dependence of the 1/f noise on 2D electron concentration in the channel n Ch of AlGaN/GaN Heterostructure Field Effect Transistors and Metal Oxide Semiconductor Heterostructure Field Effect Transistors has been studied and compared. The dependencies of Hooge parameter αCh for the noise sources located in the channel of the transistors on sheet electron concentration are found identical for both types of devices. The increase of the Hooge parameter αCh with the decrease of the channel concentration observed in both types of devices confirms that the noise sources are located in the region under the gate in the AlGaN/GaN heterostructure and that electron tunneling from the 2D electron gas into the traps in GaN or AlGaN layers is a probable noise mechanism.

High-Temperature Performance of AlGaN/GaN Metal-Oxide-Semiconductor Heterostructure Field-Effect-Transistors

The characteristics of novel AlGaN/GaN Metal–Oxide–Semiconductor Heterostructure Field Effect Transistors (MOSHFETs) were measured in the temperature range of 20–300 °C. At 300 °C the leakage current of MOSHFET remains four orders of magnitude lower than that of regular HFET. The saturation current and transconductance for both types of transistors follow the temperature dependence of electron velocity in the channel. The recovery of the current collapse at elevated temperatures compensates the effect of the decrease of the steady-state saturation current with temperature. As a consequence, the saturation microwave power remains fairly constant in the temperature range 20–200 °C, varying only by about 20% or so. These results show high potential of MOSHFETs for high-temperature microwave, digital and switching applications.

First AlGaN/GaN metal oxide semiconductor heterostructurefieldeffect transistor based on photoanodic oxide

The DC characteristics of an AlGaN/GaN metal oxide semiconductor heterostructure field effect transistor are presented. The unique feature of this device is its oxide, which is formed photoelectrochemically at room temperature. For a device with a gate length of 2 µm state-of-the-art values of 540 mA/mm and 62 mS/mm were obtained for the drain current and transconductance, respectively.

Large periphery high-power AlGaN/GaN metal-oxide-semiconductor heterostructure field effect transistors on SiC with oxide-bridging

We report on AlGaN/GaN metal oxide semiconductor heterostructure field effect transistor (HFET) over SiC substrates with peripheries from 0.15 to 6 mm. These multigate devices with source interconnections were fabricated using a novel oxide-bridging approach. The saturation current was as high as 5.1 A for a 6 mm wide device with a gate leakage of 1 μA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for 1.5 μm gate length in a 5 μm source-drain opening. The cutoff frequency of around 8 GHz was practically independent of the device periphery. Large-signal output rf-power as high as 2.88 W/mm was measured at 2 GHz. Both the saturation current and the rf-power scaled nearly linearly with the gate width.

AlGaN/GaN metal oxide semiconductor heterostructure field effect transistor

We report on the AlGaN/GaN metal oxide semiconductor heterostructure field effect transistor (MOS-HFET) and present the results of the comparative studies of this device and a base line AlGaN/GaN heterostructure field effect transistor (HFET). For a 5-μ source-to-drain opening, the maximum current was close to 600 mA/mm for both devices. The gate leakage current for the MOS-HFET was more than six orders of magnitude smaller than for the HFET.