Degradation Of Oxide Reliability Research Articles

Relation between Defects on 4H-SiC Epitaxial Surface and Gate Oxide Reliability

Time-dependent dielectric breakdown (TDDB) measurement of MOS capacitors on an n-type 4 ° off-axis 4H-SiC(0001) wafer free from step-bunching showed specific breakdown in the Weibull distribution plots. By observing the as-grown SiC-epi wafer surface, two kinds of epitaxial surface defect, Trapezoid-shape and Bar-shape defects, were confirmed with confocal microscope. Charge to breakdown (Qbd) of MOS capacitors including an upstream line of these defects is almost the same value as that of a Wear-out breakdown region. On the other hand, the gate oxide breakdown of MOS capacitors occurred at a downstream line. It has revealed that specific part of these defects causes degradation of oxide reliability. Cross-sectional TEM images of MOS structure show that gate oxide thickness of MOS capacitor is non-uniform on the downstream line. Moreover, AFM observation of as-grown and oxidized SiC-epitaxial surfaces indicated that surface roughness of downstream line becomes 3-4 times larger than the as-grown one by oxidation process.

Reduction of oxide leakage currents of EEPROM at STI corners using sacrificial oxide/liner SiN/LPCVD MTO

Shallow trench isolation (STI) is the predominating isolation technology for advanced integrated circuits, but the oxide thickness of the convex corner of trenched Si surfaces is thinner than other planar Si surfaces, which causes leakage currents and gate oxide reliability degradation of electrically erasable and programmable read only memory (EEPROM) by the keen convex corner region. We present an improved shallow trench isolation process to reduce leakage currents by sacrificial thermal oxide, liner silicon nitride, and Low Pressure Chemical Vapor Deposition Medium Temperature Oxide (LPCVD MTO). We found that the sample fabricated by an improved STI process with sacrificial oxidation of EEPROM decreased leakage currents and eliminated humps shown at the samples fabricated by conventional STI process, and also obtained more improved endurance characteristics stress biases applied at wordlines. In spite of the shortcoming that it provides a few additional shallow trench isolation process steps, it is an effective method to reduce oxide leakage currents and alleviate oxide reliability degradation.

Impact of ESD protection device trigger transient on the reliability of ultra-thin gate oxide

Common ESD protection devices have a snapback characteristic similar to a silicon-control rectifier. The transient voltage required to trigger these devices usually is not an important design criterion as long as it is not too high. In this work, it is demonstrated that the defect generation mechanism in oxide during electrical stress remains unchanged in the sub-nanosecond stress regime. As a result, the voltage transient can create far more defects in the gate oxide than the main ESD event clamped at the holding voltage. Due to difficulty in measurement, this oxide reliability degradation can lead to chip failure but not show up in simulated ESD test.

A new model for TDDB lifetime distribution of SiO 2

This paper provide a new model for TDDB lifetime distribution based on statistical considerations. The model is based on two assumptions: an assumption of hole capture cross section and an assumption of critical defect number. In this model, a small critical defect number yields the Weidull distribution and a large one changes it to the lognormal distribution. Degradation of oxide reliability corresponds to decrease of a critical defect number and so called extrinsic breakdown is induced by a small critical defect number.

Temperature-accelerated dielectric breakdown in ultrathin gate oxides

Temperature-accelerated effects on dielectric breakdown of ultrathin gate oxide with thickness ranging from 8.7 to 2.5 nm are investigated and analyzed. Although superior reliability for ultrathin gate oxide at room temperature has been reported in recent literatures, a strong temperature-accelerated degradation of oxide reliability is observed in this study. Experimental results show that both charge-to-breakdown (Qbd) and breakdown field (Ebd) characteristics are greatly aggravated for ultrathin oxide at elevated temperature. The Arrhenius plot also confirms that the activation energies of Qbd and Ebd increase significantly as oxide thickness decreases, explaining the higher sensitivity to temperature for thinner oxides.

Effect of Phosphorus-Doped Polysilicon Anneal on Thin Oxide Reliability as Probed with X-Ray Damage Characterization

ABSTRACTIn this paper we address the degradation of oxide reliability after annealing the phosphorusdoped polysilicon of MOS structures. The oxide reliability was studied in terms of X-ray radiation sensitivity as well as breakdown characteristics.We found that annealing the polysilicon increased the radiation sensitivity of the gate oxide. We believe that this increase is a result of the phosphorus out-diffusion from the polysilicon into the oxide and a result of the creation of phosphorus related traps in the oxide bulk. We also found that the oxide charge to breakdown (Qbd) degradation correlates well with the density of the phosphorus in the oxide.