Oxide Defect Density Research Articles

MOS Compatibility of high-conductivity TaSi2/n+poly-Si gates

The MOS-VLSI parameters and process compatibility of a high-conductivity refractory silicide gate with a sheet resistance of ∼ 2 Ω/□ have been evaluated. The gate metallization typically consisted of 2.5 kÅ TaSi <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> /2.5 kÅ poly-Si, which was sintered prior to patterning with a CF <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</inf> /O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> plasma etch. Measurements were made to determine the metal work function, oxide fixed charge, surface-states density, dielectric strength, oxide defect density, lifetime, current leakage, and the flat-band voltage stability with respect to mobile charge contamination, slow trapping, and hot-electron trapping. On IGFET's (500-Å SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> , As-implanted source/ drain), V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> and β measurements were made as a function of the back-gate bias and the channel length as small as 2 µm. The MOS and IGFET parameters are nearly ideal and correspond to those expected of n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> poly-Si gates. Static and dynamic bias-temperature aging stability of the V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</inf> is excellent. These characteristics are preserved through subsequent standard VLSI process steps. However, certain process and structure limitations do exist and these have been defined.

A Method of Forming Thin and Highly Reliable Gate Oxides: Two Step Oxidation

A new two step oxidation has been developed as a method of forming thin and highly reliable gate oxides used in MOS LSI's. It consists of initial oxidation at low temperature with low concentration and following treatment at high temperature in a mixture of , , and gases. This report mainly covers oxide defect reduction effect and passivation effect of oxides formed by the two step oxidation. The oxide defect density depends on the condition of the initial oxidation and following heat‐treatment. Concretely, it is effective, for defect reduction, to use oxide as the initial oxide and give it high temperature treatment for over 20 min. The passivation effect depends on the concentration and the treatment time at the treatment. It became evident that over 90 min treatment is necessary for passivation at 1150°C with 3% . According to SIMS analysis, the mechanism of this passivation is fundamentally similar to that of a usual oxidation. Many applications may be expected for this two step oxidation.

The Dependence of the SiO2 Defect Density on Both the Applied Electric Field and the Oxide Thickness

By using liquid crystals in contact with the oxide and simultaneously applying an electric field across such a sandwich structure, defective regions can be nondestructively identified. By examining the number of defects as a function of the applied electric field and oxide thickness, it is possible to obtain information on the variation of the defect density with the applied electric field and oxide thickness. Experiments of this type indicate that the defect density was found to exponentially increase with the square root of the positive applied electric field. Also the total leakage current density was found to exponentially increase with the square root of the positive applied electric field in the presence of the liquid crystals. The defect diameter was found to be in the range of 0.14–0.42 μm. For oxide thickness above 0.2 μm the defect density exponentially decreases with increasing oxide thickness. But for oxide thicknesses less than 0.2 μm it is very difficult to judge the variation since the defect density increases very rapidly with decreasing oxide thickness. Spikes of were observed to protrude into the silicon substrate for thin oxides (about 0.1 μm); however, these spikes could be eliminated by increasing the oxide thickness (greater than 0.3 μm). With increasing oxide thickness the interface becomes evener and the density of the interface irregularities decreases. The electron space‐charge effects were postulated as a second explanation for the variation of the oxide defect density with the oxide thickness. This theoretical treatment agrees well with the experimental results. The space‐charge (electron) density in the oxide was equal to which is in agreement with the trap density of the silicon dioxide.

The Use of 1.1.1.‐Trichloroethane as an Optimized Additive to Improve the Silicon Thermal Oxidation Technology

Based on the pyrolysis of trichloroethene , also referred to as TCE, and the thermodynamic analysis of its reaction products a substitute for TCE is found. It is characterized by better physical and chemical properties and behaves as an additive during silicon oxidation identical to . This chlorinated hydrocarbon, 1.1.1.‐trichloroethane (referred to as C33) is used for fabrication of MOS capacitors on n‐type silicon to study the properties of oxides grown with this additive. Special attention is paid to the properties influencing the performance of charge coupled devices. Storage times of 500 sec, oxide defect density of 10/cm2, and surface‐state densities lower than are achieved. The cleaning effect on the furnace tube yields a mobile ion density lower than . The fixed oxide charge on (100) material is . Fabrication of CCD's with this technology proves its suitability in silicon device processing.

The effect of oxidation-expanded defects upon MOS parameters

Implantation of Ne ions was chosen as a means of introducing a uniformly distributed quantitatively controllable and reproducible amount of microdefects at the silicon surface. Each wafer was ion implanted on one-half of its surface, the other half remaining as a control. Seven implant fluences from 1×1012 to 5×1014 Ne cm−2 were used. The fluences, as well as the concentrations of defects expanded by the subsequent gate oxidation, were correlated with seven different MOS parameters. For implant fluences of 1×1014 cm−2 and above, increasing stacking-fault densities were found. The oxide defect density associated with time-dependent breakdown increased significantly with Ne dose. The presence of oxidation-expanded defects drastically increases the surface-generation velocity and decreases the bulk lifetime. Slight increases in flatband voltage and surface-state density occurred only for the wafers having the greatest defect concentrations. Oxidation of a P-containing damaged silicon surface results in a greater pileup of P at the surface than occurs for the oxidation of a similar but undamaged surface. It appears that the expanding defects restrain the diffusion of P inward from the surface.