Overetch Time Research Articles

Modeling and Characterization of the Narrow-Width Effect of 4H-SiC MOSFETs With Local Oxidation of SiC Isolation

In this article, the narrow-width effect (NWE) of 4H-SiC MOSFETs with local oxidation of SiC (LOCOSiC) isolation is reported. A channel width-dependent current hump was observed in the subthreshold region for n-type 4H-SiC MOSFETs with LOCOSiC, and a channel width-dependent threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{th}$ </tex-math></inline-formula> ) shift was observed for p-type 4H-SiC MOSFETs with LOCOSiC. This unusual NWE arises from the increase in the gate oxide thickness from the channel center toward the isolation edge and is different from the conventional NWE found in local oxidation of silicon (LOCOS) technology, which arises from the charge stored in the parasitic field oxide (FOX) capacitor and lateral dopant encroachment. A H2O diffusion and oxidation model is proposed in this article to explain the growth of a long bird’s beak in 4H-SiC MOSFETs with LOCOSiC. Technology computer-aided design (TCAD) simulations were executed to explore the H2O diffusion behavior of these MOSFETs, and an analytical formula was derived to predict the oxide layer thickness and length of bird’s beak along the diffusion path in the H2O diffusion and oxidation model. The problems caused by the long bird’s beak and unusual NWE can be overcome by increasing the overetching time of the pad oxide removal and marginally decreasing the thickness of the FOX layer. Therefore, the NWE of the LOCOSiC isolation is expected to be weaker than that of the LOCOS isolation because field implantation is unnecessary, and thus, dopant encroachment does not occur in the LOCOSiC technology.

Effect of Over-Etching and Prolonged Application Time of a Universal Adhesive on Dentin Bond Strength.

This study investigated the effect of over-etching and prolonged application time of a universal adhesive on dentin bond strength. Ninety extracted human molars were ground to dentin and randomly allocated into nine groups (G1–9; n = 10 per group), according to the following acid etching and adhesive application times. In the control group (G1), phosphoric acid etching was performed for 15 s followed by application of the universal adhesive Scotchbond Universal (3M) for 20 s, as per manufacturer’s instructions. In groups G2–5, both the etching and adhesive application times were either halved, doubled, quadrupled, or increased eightfold. In groups G6–9, etching times remained the same as in G2–5 (7.5 s, 30 s, 60 s, and 120 s, respectively), but the adhesive application time was set at 20 s as in the control group (G1). Specimens were then restored with a nanofilled composite material and subjected to microtensile bond strength testing. Bond strength data were statistically analyzed by ANOVA and Tukey’s post-hoc tests (α = 0.05). The relationship of bond strength with etching and adhesive application time was examined using linear regression analysis. Treatment of dentin with halved phosphoric acid etching and adhesive application times (G2) resulted in a significant bond strength decrease compared to the control group (G1) and all other test groups, including the group with halved acid etching, but 20 s of adhesive application time (G6). No significant differences in bond strength were found for groups with multiplied etching times and an adhesive application time of 20 s or more, when compared to the control group (G1). In conclusion, a universal adhesive application time of at least 20 s is recommended when bonding to over-etched dentin.

Selective etching of p-GaN over Al0.25Ga0.75N in Cl2/Ar/O2 ICP plasma for fabrication of normally-off GaN HEMTs

The article presents the results of development of selective etching of p-GaN over Al0.25Ga0.75N in Cl2/Ar/O2 ICP plasma for fabrication of normally-off p-GaN gate GaN HEMTs using a laser reflectometry system for precise control of the etched material thickness. By optimizing etching process parameters such as oxygen flow, ICP power and chamber pressure, high etching selectivity of p-GaN over Al0.25Ga0.75N were obtained, with values up to 56:1. High etching selectivity and the control of etch rates of p-GaN and Al0.25Ga0.75N layers withing a wide range by changing the ICP process parameters enabled application of developed etching processes in the technology of fabrication of normally-off AlGaN/GaN HEMTs with a p-GaN gate. High threshold voltage of around 1.6 V and current densities up to 400 mA/mm were obtained. Electrical measurements have shown that the shortest 1 min Al0.25Ga0.75N overetch time after selective etching of the p-GaN layer results in best electrical parameters of fabricated devices.

Investigation of feature orientation and consequences of ion tilting during plasma etching with a three-dimensional feature profile simulator

Pattern transfer in microelectronics fabrication using plasma-assisted etching processes is being challenged by the three-dimensional (3d) structures of devices such as fin field effect transistors. Etching of 3d structures typically requires a longer over-etch time to clear material in corners, introducing additional selectivity challenges to maintain feature scale critical dimensions. Feature open area, orientation, aspect ratio, and proximity to other nearby structures can influence the outcome of the etch process. In this paper, the authors report on the development and application of a 3d profile simulator, the Monte Carlo feature profile model in the investigation of aspect ratio, and feature orientation dependent etching. In these studies, energy and angularly resolved reactant fluxes were provided by the hybrid plasma equipment model. Results from the model were validated with trends from experimental data. Using reactant fluxes from He/Cl2 and Ar/Cl2 inductively coupled plasmas, etching of two dimensional (2d) and 3d structures in the context of ion tilting and orientation of the feature was investigated.

Surface Protection for Semiconductor Direct Bonding

Semiconductor direct wafer bonding is a widely used process for fabricating 3-dimensional structures, especially engineered substrates such as SOI wafers or cavity wafers with and without insulating layers at the bonding interface. The investigations described here concern cavity SOI wafers without insulating layers, as used for discrete and integrated pressure sensors. Semiconductor direct bonding is the initial bonding by mechanical contacting of high-quality surfaces activated by wet chemical and/or plasma treatments, followed by thermal annealing at temperatures and times related to the chosen activation. This ultimately results in a very strong mechanical bond, which can survive all of the subsequent process steps, such as those needed to process MEMS pressure sensors. The requirement for the direct bonding is that the wafers to be bonded have a very high quality; this means very low roughness, low waviness and no surface residues or contamination. In this paper, the focus is on roughness in relation to the bonding process and process integration. It is well known that prime wafers with vendor polishing as the finishing step have a very good mirror polished surface, and can be bonded very easily – therefore they are often used for basic wafer bonding investigations, such as the effectiveness of surface activation. On the other hand, fresh polishing as the final step before wafer bonding is often used to reconfigure the surface, to allow a very good wafer bonding. In practice, especially in industrial processes, the problem is that wafers need to be processed before bonding to generate the required functional structures (the reference pressure cavity in case of the pressure sensors and alignment marks on the wafer backside to retrieve the sealed cavities after bonding). On the other hand, fresh polishing directly before bonding is not possible, either due to availability or because it cannot be used for the already-structured wafers (either the structure on the wafers or the polishing pads would be damaged). Here, one option is to protect the bonding surfaces with a hard coating, such as by growing a thermal oxide on a silicon wafer. In the case of the pressure sensors, this layer can fulfil a double function – protecting the bonding surface and acting as a hard mask for the cavity etching. Hence, the flow of the cavity wafer can be summarized as follows: thermal oxidation, back side lithography of the alignment marks, plasma etching of oxide back side (hard mask structuring), resist removal, front-to-back side lithography, plasma etching of the cavity hard mask on the front side, resist removal, KOH etching of silicon in an etch bath (simultaneously etching of cavities on front side and alignment marks on wafer back side), hard mask stripping using oxide etching baths. Due to availability, Buffered Oxide Etchant (BOE) has to be used for stripping the hard mask from the wafer, and it was found that this etchant can slightly attack the silicon surface, making it a little rougher, which makes the bonding more difficult. With respect to a safe process, the etching time has to be long enough to remove the oxide in all cases, (e.g. grown oxide thickness in upper spec range, BOE oxide etching range in lower spec range), to reduce all the oxide everywhere on the wafer, but it must be short enough to prevent the roughening of the surface. Therefore, the extra etching time the wafer is left in the bath after the oxide has been removed, which is needed to cover natural process variations, must be as short as possible. This was evaluated experimentally. As a measure of the surface roughness, the bonding process itself was used, in particular, the travelling speed (Figure1) of the bonding front across the wafer – since the higher this is, the better the surface and the safer the overall process. As result, it was found that reducing the over-etch time by about 50%, reduced the travelling speed of the direct wafer bonding front by 20%, which is very significant. From this, it can be concluded, that the bonding behaviour of the silicon is strongly influenced by the time the free silicon surface remains in the BOE – the longer this time, the rougher the silicon, and the more difficult the bonding. This is ultimately very important for the overall process integration and to achieve a safe bonding process for almost void-free engineered substrates such as cavity wafers (Figure 2). Figure 1

Relationship between photovoltaic and diode characteristic parameters in the Sn/p-Si Schottky type photovoltaics

In order to investigate relationship between photovoltaic and diode characteristic parameters, we fabricated four kinds of samples of Sn/p-Si Schottky type photovoltaics using surface treatment by anodic oxidation and chemical etching method. Diode and photovoltaic characteristics of the samples were determined from the current–voltage measurements performed in dark and under illumination. Etching time of front surface of the p-Si substrate in HF solution used in the fabrication of Sn/p-Si Schottky type photovoltaics was found to be very influential on diode and photovoltaic parameters. Especially, an etching time of 30s showed a positive effect both on diode and photovoltaic characteristic parameters. It was also observed that the characteristic parameters of the samples were affected negatively depending on the over-etching time. More importantly, a close relationship between photovoltaic parameters (fill factor, conversion efficiency) and diode parameters (ideality factor, series resistance) was observed.

Mechanisms for plasma etching of RRAM SiO2 with diblock copolymer selectivity

To minimize the critical dimension of resistive switching random access memory (RRAM), good anisotropy and selectivity with diblock copolymer are required for silicon dioxide etching. Inductively coupled plasma (ICP) etcher using CHF 3/ H 2 mixture is used for effective etching of SiO 2. In this paper, a commercial software CFD-ACE+ was used to simulate reactor scale and feature scale model of SiO 2, diblock copolymer and Pt . Etch properties of SiO 2 at different chamber conditions were discussed. It was found that etch rate increased at the expense of selectivity as ICP power increased, which was the opposite trend for pressure. Selectivity and anisotropy are achieved at neutral to ion flux ratio 100:1. Moreover, the appropriate overetch time for SiO 2 layer to Pt layer was discussed.

Delay-Time Effect on the Transistor Performance after Reactive Ion Etching

Since recessed channel array transistor (RCAT) was adopted from 100 nm feature size, gate-induced-drain-leakage (GIDL) has been the major cause of refresh fail. [1] The process of inner-gate-recess was adapted and GIDL in RCAT structure has been remarkably reduced by lowering electric field at overlap region. Fig.1 (a) and (b) show the VSEM image of inner-gate-recessed-RCAT and the electric field simulation, respectively. The process of recessing gate-poly was executed at both cell array transistor such as RCAT and planar transistor in logical circuits. In case of planar transistor, there was no need to recess poly-Si except SiO2 layer. During the etching of poly-Si in the cell array, the thin oxide layer in the planar area should be preserved to prevent Si-pitting. HBr/O2 plasma has been used to improve the selectivity of poly-Si to gate oxide in gate-stack etching. HBr/O2 plasma produced polymer residues such as SiBr and SiBrOx layer on the underlying gate oxide and polymer residues should be removed. [2, 3] Fig.2 shows the variation of stand-by current of DRAM and propagation time of inverter (tPD) with wafer number in a lot investigated. Wafer number indicates the order in processing. As the number of wafer increased, stand-by current increased and tPD decreased. Fig.3 shows the saturation current of PMOS and the saturation current also decreased with increasing wafer number. Structural analysis was evaluated, and the difference between the first wafer and the last wafer was found. There was thicker SiO2 layer on the gate stack in the first wafer. Especially, to make the gate recessed profile of RCAT, the over-etch time increased and the exposure time in HBr/O2 plasma also increased. It induced to increase polymer residues and unexpected SiO2 offset spacer. As the HF removal was delayed for measuring critical dimension (CD) of gate stack and thickness of remain substrate, deposited SiBr among the polymer residues reacted with O2 in the air and additional SiO2 was grown. [4] The first wafer in the lot investigated had much more delay time than the last wafer. Therefore thicker SiO2 in the first wafer was grown than that of the last wafer, and the SiO2 in the first wafer was insufficiently removed by HF clean. SiO2 offset made under-lap from gate to source/drain and induced increasing resistance and decreasing saturation current. [5, 6] Fig.4 (a) and (b) show the TEM profiles and explain the cause of saturation current difference obtained from the same lot. Immediate HF cleaning after gate etching was introduced and CD was measured with increasing time by the scanning electron microscope (SEM). Fig. 5 shows the CD variation monitored as a function of delay time. While SiO2 layer was steadily grown with increasing delay time without HF cleaning, the SiO2 and residual SiBr layer on the sidewall of gate stack were easily removed and additional SiO2was not grown in case of immediate HF clean. As the integration process is more complicated and delicate, small variation brings the big failure. Delay time after reactive ion etching should be reduced, and immediate cleaning should be appropriately considered.

Numerical Simulation Method for Plasma-Induced Damage Profile in SiO2 Etching

We developed a numerical simulation method for the depth profiles of plasma-induced physical damage to SiO2 and Si layers during fluorocarbon plasma etching. In the proposed method, the surface layer is assumed to consist of two layers: a C–F polymer layer and a reactive layer. Physical and chemical reactions in the reactive layer divided into several thin slabs and in the deposited C–F polymer layer, which depend on etching parameters, such as etching time, gas flow rate, gas pressure, and ion energy (Vpp), are considered in detail. We used our simulation method to calculate the SiO2 etch rate, the thickness of the C–F polymer layer (TC–F), and the selectivity of SiO2 to Si during C4F8/O2/Ar plasma etching. We confirmed that the calculated absolute values and their behavior are consistent with experimental data. We also successfully predicted depth profiles of physical damage to the Si and SiO2 layers introducing our re-gridding method. We found that much Si damage is generated in the pre- and early stages of the overetching step of SiO2/Si layer etching despite the high selectivity. These simulation results suggest that the TC–F value and the overetching time must be carefully controlled by process parameters to reduce damage during fluorocarbon plasma etching. The results have also provided us with useful knowledge for controlling the etching process.

Effect of annealing on wet etch of amorphous IGZO thin film

Amorphous InGaZnO (a-IGZO) film is deposited on the glass substrate by radio-frequency sputtering and the influence of annealing on wet etch of a-IGZO films were investigated. The results show that etch rate of IGZO films decrease with the increase of annealing temperature. Etching taper angle is less than 60° and critical dimension (CD) loss is less than 1 μm in over-etching time of 30 s. The fact implies that IGZO films etching with oxalic acid may be a good wet etching way for the thin-film transistor (TFT) array process.

DRIE fabrication of notch-free silicon structures using a novel silicon-on-patterned metal and glass wafer

This paper presents a method of fabricating a silicon structure without notches using a new kind of substrate consisting of silicon-on-patterned metal and glass (SOMG). It has a metal interlayer with a thickness of 0.1 µm between a silicon wafer and glass wafer as an insulation layer to eliminate the micro-charging effect on the insulation surface for the silicon dry etching process. This substrate is fabricated by anodic bonding and polishing. To ascertain the effect of the SOMG substrate, 100 µm deep silicon structures with 5 and 20 µm wide trenches have been etched on SOG (silicon-on-glass) and SOMG substrates under similar conditions. In order to perform the deep silicon etching process, a thick photoresist of AZ9260 is used as a dry etch mask. In the results, no notches are on SOMG, while notches occur on SOG. Also, regardless of the over-etching time as the dimensions of the area to be etched, no notches are formed at the bottom of the silicon structure. This results in a notchless silicon structure. This research shows the feasibility of applying this technique to many applications using silicon devices.

Infinitely high selective inductively coupled plasma etching of an indium tin oxide binary mask structure for extreme ultraviolet lithography

Currently, extreme ultraviolet lithography (EUVL) is being investigated for next generation lithography. Among the core EUVL technologies, mask fabrication is of considerable importance due to the use of new reflective optics with a completely different configuration than those of conventional photolithography. This study investigated the etching properties of indium tin oxide (ITO) binary mask materials for EUVL, such as ITO (absorber layer), Ru (capping/etch-stop layer), and a Mo–Si multilayer (reflective layer), by varying the Cl2/Ar gas flow ratio, dc self-bias voltage (Vdc), and etch time in inductively coupled plasmas. The ITO absorber layer needs to be etched with no loss in the Ru layer on the Mo–Si multilayer for fabrication of the EUVL ITO binary mask structure proposed here. The ITO layer could be etched with an infinitely high etch selectivity over the Ru etch-stop layer in Cl2/Ar plasma even with a very high overetch time.

High-Etching-Selectivity Barrier SiC (k

Copper (Cu)/low-k interconnects were fabricated using novel Cu diffusion-barrier SiC films deposited with a novel precursor, 1,1-divinyl-silacyclopentane (DVScP). At 46% overetching time, the yield of the via-contact with the dielectric barrier of conventional SiC films was seriously reduced, while that of the novel SiC films was hardly reduced. By using the novel SiC films, the thickness of diffusion barriers was successfully reduced to 15 nm, matching the 32 nm node and beyond. By using the novel SiC films, the dielectric constant of the barrier films was decreased and their thickness was reduced with no yield reduction of the via-contact. As a result, the product of wiring resistance and capacitance (RC product) was reduced by 11.4%. The time-dependent dielectric breakdown (TDDB) lifetime of Cu interconnects with the SiC films was similar to that with the SiCO films.

Selective dry etching of attenuated phase-shift mask materials for extreme ultraviolet lithography using inductively coupled plasmas

Among the core extreme ultraviolet lithography (EUVL) technologies, mask fabrication is of considerable importance due to the use of new reflective optics having a completely different configuration from that of conventional photolithography. This study investigated the etching properties of attenuated phase-shift mask materials for EUVL, such as TaN (attenuator layer), Al2O3 (spacer), Mo (phase shifting layer), Ru (buffer/capping/etch-stop layer), and Mo–Si multilayer (reflective layer) by varying the Cl2∕Ar gas flow ratio, dc self-bias voltage (Vdc), and etch time in inductively coupled plasmas. For the fabrication of the attenuated EUVL mask structure proposed herein, the TaN, Al2O3, and Mo layers need to be etched with no loss of the Ru layer on the Mo–Si multilayer. The TaN and Al2O3 layers were able to be etched in BCl3∕Cl2∕Ar plasmas with a Vdc of −100V and the Mo layer was etched with an infinitely high etch selectivity over the Ru etch-stop layer in a Cl2∕Ar plasma with a Vdc of −25V even with increasing overetch time.

Highly selective dry etching of alternating phase-shift mask (PSM) structures for extreme ultraviolet lithography (EUVL) using inductively coupled plasmas (ICP)

Extreme ultraviolet lithography (EUVL) is the most promising candidate for next generation lithography due to its feature size of 32 nm or below. We investigated the etching properties of materials in an alternating, phase-shift mask (PSM) structure for EUVL, including a Ru top capping layer, Mo–Si multilayer (ML) and Ni etch stop layer (ESL), by varying the Cl 2/O 2 and Cl 2/Ar gas flow ratios, and the dc self-bias voltage ( V dc) in inductively coupled plasma (ICP). The Ru layer could be etched effectively in Cl 2/O 2 plasmas and Mo–Si ML could be etched with an infinitely high etch selectivity over Ni ESL in Cl 2/Ar plasmas, even with increasing overetch time.

Dry etching of TaN∕HfO2 gate-stack structure in BCl3∕Ar∕O2 inductively coupled plasmas

In this work, etching characteristics of TaN(200nm)∕HfO2(80nm) gate-stack structures on Si substrate were investigated by varying the process parameters such as BCl3∕(BCl3+Ar+O2) gas mixing ratio (Q), top-electrode power, dc self-bias voltage (Vdc), and overetch time in an inductively coupled plasma etcher. To understand the role of the etch gas chemistry, we measure the relative changes in the optical emission intensity of ions and radicals in the plasma as well as in the chemical binding states of the etched TaN surfaces. We used optical emission spectroscopy and x-ray photoelectron spectroscopy respectively. The results showed that BCl3∕Ar∕O2 plasma is more effective in etching the oxidized TaN than Cl2∕Ar∕O2 or HBr∕Ar∕O2 plasma. It is believed that the B radical species removes the oxygen atoms on the oxidized TaN surface more effectively by forming volatile boron-oxygen-chlorine compounds, such as trichloroboroxin (BOCl)3), boron oxychloride (BOCl), and boron dioxide. The measurement data also indicated that high etch selectivities of the TaN to the HfO2 layer could be obtained at the low Vdc, high top-electrode power, and shorter overetch time.

Surface Preparation for Transistor Performance Improvement in Triple Gate Oxide Integration

Fabrication of current high-performance metal-oxide-semiconductor field effect transistors (MOSFETs) requires a multiple gate oxide integration to obtain different oxide thicknesses and applied voltages. However, channel mobility and drive current are degraded as the number of oxide growth and etching steps increases during the multiple gate oxide integration. In multiple gate oxide integration, a shorter overetch time with a more dilute HF solution for the removal of preexisting oxides exhibits improved surface mobility and transistor drive current resulting from the suppression of surface roughness deterioration. The elimination of SC1 cleaning or the addition of a lower-temperature dilute SC1 cleaning in the pregate cleaning sequence also produces improved transistor mobility. Considering that the addition of SC1 cleaning in the pregate cleaning sequence is needed to remove particles on the surface, the use of a dilute SC1 cleaning may be a realistic method to achieve both improvement of transistor performance and removal of particles. Mobility and drive current of are found to be more sensitive to surface preparation changes than , which may be explained by the closer proximity of electrons to the interface compared to holes.

Experimental Investigation of the Impact of LWR on Sub-100-nm Device Performance

Argon Fluoride (ArF) lithography is essential to develop a sub-100-nm device, however, line edge roughness (LER) and line width roughness (LWR) is playing a critical role due to the immaturity of photoresist and the lack of etch resistance. Researchers are trying to improve LER and LWR properties by optimizing photoresist materials and process conditions. In this paper, experiment results are presented to study the impact of LER and LWR to device performance so that the reasonable control range of LER and LWR can be defined. To implement the experiment, a 80-nm node of single negative-channel metal-oxide-semiconductor transistors were fabricated, which had various ranges of gate length, width, LER, and LWR. The amount of LER and LWR could be successfully controlled by applying different resist materials, defocus, and overetch time. Experimental results show that leakage current is significantly increased as LWR increases when the gate length is less than 85 nm. The main degradation is standard deviation of off-current (I/sub off/), and LWR is better representation to characterize a device performance.

Releasing SU-8 structures using polystyrene as a sacrificial material

We have successfully developed a new method to release SU-8 structures with polystyrene as a sacrificial material. Toluene is initially used to dissolve solid polystyrene, and the resulting solution is employed to spin coat a sacrificial polystyrene layer onto a glass plate prior to SU-8 deposition. Toluene is used again at the end of the process to sacrificially etch the polystyrene layer to release the cured SU-8 structures. Toluene has no effect on the cured SU-8, even with significant over-etch times, and the dissolution and etch rates are relatively fast. Using this method, we have successfully released SU-8 membranes of an area of 50 cm 2.

Highly selective HBr etch process for fabrication of Triple-Gate nano-scale SOI-MOSFETs

New three-dimensional device concepts are considered necessary for the ultimate scaling of the gate length of metal-oxide-semiconductor field effect transistors (MOSFETs). Both Triple-Gate field effect transistors and FinFETs require a gate etch process with excellent selectivity over the gate oxide material. In this work, a highly selective, anisotropic gate etch process using HBr and O2 as the reactive gases in an inductively coupled plasma reactive ion etch tool is described. Polysilicon thickness measurements have been taken to calculate etch rate and uniformity. Polysilicon wafers for each experimental condition were given different overetch times and SiO2 losses were plotted against time, with the gradient yielding the SiO2 etch rate. The optimized etch process yields excellent results for nanoscale polysilicon gates.