Output Spin Research Articles

1.6 Gbit/s phosphorescent white LED based VLC transmission using a cascaded pre-equalization circuit and a differential outputs PIN receiver.

We proposed a cascaded amplitude equalizer used for high speed visible light communications (VLC) system. With the cascaded pre-equalization circuit, the -3dB bandwidth of VLC system can be extended from 17MHz to 366MHz using a commercially available phosphorescent white LED, a blue filter and a differential outputs PIN receiver. The data rate is 1.60Gbit/s exploiting 16QAM-OFDM with 400MHz modulation bandwidth over 1m free-space transmission under pre-forward error correction (pre-FEC) limit of 3.8 × 10(-3). To our knowledge, this is the highest data rate ever achieved by using a commercially available phosphorescent white LED in VLC system.

Automatic generation of embedded communication SW for heterogeneous MPSoC platforms

This paper addresses the problem of long design cycle of MPSoCs communication SW with automatic synthesis. The tool we propose takes as input a transaction level model (TLM) of MPSoC communication and outputs pin and cycle-accurate (PCA) bus drivers that can be linked to the synthesizable PCA model (PCAM). The TL communication is simple since TLM channels abstract away protocol details. PCAM communication, in turn, includes explicit definitions for each signal and pin. However, in most cases the TLMs are not suitable for implementation since they do not reflect the MPSoC platform. Usually the designers simulate (fast) TLMs, then manually implement PCA communication. Our communication SW synthesis transforms TL send and receive functions into platform specific PCAM bus drivers which can be automatically downloaded to the FPGA board. The presented results demonstrate the significant productivity gain achieved with our tool, with no great cost to either code size or system performance.