Output Voltage Steps Research Articles

Design and Implementation of a Single-Phase 15-Level Inverter With Reduced Components for Solar PV Applications

A new single-phase 15-level inverter with a reduced number of components for the Solar PV application is proposed in this paper. It is incorporate the proposed inverter with a boost converter to extract energy from the solar PV modules, the proposed inverter aids to generate fifteen stepped output voltage levels with lower THD. The proposed inverter can improve efficiency and reduce losses, cost, and complexity of the overall system. The conventional boost converter will boost the output voltage to a maximum voltage from Solar PV with MPPT(P&O). The proposed inverter is tested experimentally using the dSPACE RTI 1104 controller along with MATLAB/Simulink. A detailed comparison with existing MLIs with the proposed inverter. The work presents experimental results not only to show its efficiency but also to the effectiveness under different circumstances of linear and non-linear loads. The inverter is stable during the non-linear loads and well suits for grid-connected systems.

Compact Seven-Level Boost Type Inverter Topology

Boost type switched-capacitor inverter topologies are highly suitable for photovoltaic based distributed power generation and electric vehicle applications. This brief proposes a new single-stage boost type inverter topology with features of self-voltage balancing capability of floating capacitors (FCs), seven-level (7L) stepped output voltage generation with peak output voltage three times higher than the input voltage. The modes of operation are discussed in detail emphasizing the self-voltage balancing. Further, the proposed topology uses less number of semiconductor devices. A detailed comparison with other recent 7L inverter topologies is presented to attest to the merits of the proposed topology concerning a reduced number of components. Finally, a laboratory prototype is employed to validate the proposed topology’s operability, and the obtained experimental results are presented.

A 1-A 6-MHz Digitally Assisted Buck–Boost Converter With Seamless Mode Transitions and Fast Dynamic Performance for Mobile Devices

A 1-A 6-MHz buck-boost converter with seamless mode transitions and fast dynamic operation is proposed for extending the useable voltage range of Li-ion batteries in mobile devices, and thereby their battery life. The proposed converter employs a proportional-integral peak-current-mode pulsewidth modulation controller with a digital adaptive slew-rate control scheme that minimizes output undershoots, overshoots, and settling time during mode transitions and dynamic events, such as load and output voltage steps. Additionally, hysteretic mode detection is proposed to prevent falsely triggering the converter to transition between the various operation modes (i.e., buck, boost, and buck-boost) and negatively impacting the performance of the circuit loads. The converter is fabricated in 0.13-μm CMOS technology, and supports 2.3-5 V input and 1.5-3.6 V output. The converter achieves 91.7% peak efficiency and over 80% efficiency at 1-mA load across all conditions. The output voltage ripple is less than 10 mV with a 220-nH inductor and a 10-μF output capacitor.

Novel Reduced Switch Multi-Level Inverter for Range Extension of Novel EV Configuration

This project gives the novel idea of electric vehicle configuration for heavy vehicles which are most used in up and downstream. This configuration help to improve the efficiency of the system by twice when it is operated in the downstream. so, the concept is modifying the hybrid electric vehicle configuration by changing the internal combustion engine with a generator in addition to minimize the loss and increase the battery performance using a multilevel inverter. Multilevel Inverters are a new group of converters for DC-AC conversion in the medium and high voltage and power applications. In this paper, a new topology for the stepped wave output voltage generations have been proposed with a smaller number of switches. The topology needs 3 DC voltage sources and 7 switches to produce 15 levels at the load, beyond having a smaller number of switches has the advantages in terms of low voltage stresses across the switches. As an add on, a detailed comparative study of different topologies has been discussed in the paper to illustrate the advantages and features of the proposed topologies. Finally, experimental results have been included in the paper to validate the performances of the proposed topologies with a resistive load, and the prototype model is done for the multilevel inverter and the output displayed.

Grid integrated photovoltaic system with fuzzy based maximum power point tracking control along with harmonic elimination

ABSTRACTEfficient extraction and conversion of solar power is an important research area in the field of renewable energy integration. Although, literature is enriched with different power extraction, conversion, and harmonics elimination techniques but still there are problems of maximum power point tracking (MPPT) under partial shading conditions, photovoltaic (PV) mismatching, power fluctuation in steady‐state condition, and higher total harmonic distortion (THD) value. The article has two manifolds. First, it proposes a fuzzy embedded MPPT controller to extract the maximum available PV power under time‐varying environmental conditions. For that, it utilizes seven linguistic variables and fuzzy sets along with 49 rules base to have reduced power fluctuation and power losses in a steady‐state condition, and fast tracking under time‐varying temperature and solar irradiance condition. The performance of the proposed fuzzy‐logic control (FLC)‐49 rules base is compared with FLC‐25 rules and perturb & observe based MPPT controllers. Second, for fulfilling the load demands with lower switching losses and THD, particle swarm optimization (PSO) based selective harmonic elimination (SHE) technique is applied on a cascaded half‐bridge multilevel inverter. SHE technique utilizes switching angles, which are found by solving the nonlinear transcendental equations obtained by Fourier series expansion of stepped output voltage waveform. For that, the proposed research preferred meta‐heuristic techniques of PSO over the classical techniques because of their high convergence rate, short run time, less complexity, and ability to obtain lower THD.

An Interval Arithmetic Approach for Multilevel Converter Harmonic Minimization Using Parseval’s Theorem

Multilevel converters are used for DC/AC power supply conversion, which is often applied in electric vehicle (EV) motor drives. AC conversion is done by a stepped output voltage, which provides a near-sinusoidal voltage with its fundamental frequency, but contains some higher harmonics. The elimination of several harmonics is fully implemented and well described in numerous publications, see Chiasson et al. (2003, 2004, 2005); Li et al. (2010); Tarisciotti et al. (2014), and Majed et al. (2014). In these papers the first set of undesired harmonics was eliminated, which in general was done by solving an equivalent system of equations using different methods such as resultants, Newton-Raphson (Chiasson et al. (2003)) and Optimal Minimization of Total Harmonic Distortion (OMTHD) technique, see Li et al. (2010). Higher harmonics stayed unrecognized to these optimization algorithms and delivered an undesired power spectrum to the total harmonic distortion (THD) of AC conversion.This paper presents a novel approach to the global THD-optimization of three-phase systems taking into account all harmonics up to infinity. This global optimization is implemented using interval arithmetic, see Hansen and Walster (2003), which neither need a convex objective function nor continuous-differentiable function. Interval arithmetic computes guaranteed intervals containing the global minima. The optimum is computed with an algebraic objective function, which is derived from Parseval’s theorem on a 2π periodic function.

Photovoltaic Multi-level Inverters Technology

In this paper, the three predominant styles of multilevel inverter Reviews (diode-clamped, capacitors fly, and flowing the H-Bridge inverter). Different multi-stage inverter topology that is currently to be had on the market as a ways as additives for electric integration of the PV machine also are involved. The new trend of all this topology are trying to find to lessen prices, the dimensions of the inverter and losses via reducing the range of switches and capacitors and keep a fairly high output voltage step at least just like the previous topology

A Home-type (H-type) Cascaded Multilevel Inverter with Reduced Device Count: Analysis and Implementation

Multilevel inverter (MLI) is increasingly recognized as a low distorted wave synthesizing power converter built using recent power semiconductor devices. However, MLIs suffer from the requirement of higher device count. In this paper, a 15-level Home-type (H-type) inverter topology is proposed to address this concern. The H-type inverter topology is cascaded to synthesize a higher number of levels in output voltage. Voltage ratings of the dc sources are designed to generate a large number of uniform steps in output voltage. Analysis of the proposed method is presented for required number of switches, dc voltage sources, driver circuits and blocking voltage of switches. Comparative study demonstrates that the suggested topology requires reduced device count compared to the similar topologies reported in the literature. Simulation and experimental studies have been carried out to validate the performance of proposed MLI topology.

A 10-MHz Hysteretic-Controlled Buck Converter With Single On/Off Reference Tracking Using Turning-Point Prediction for DVFS Application

This paper presents a turning-point output voltage (TPOV) prediction method to enhance the reference tracking speed of buck converters for dynamic voltage and frequency scaling (DVFS) application. The optimal reference tracking is modeled, and the TPOV is formulated. The parasitic effects are compensated with the proposed calibration scheme. Reference tracking considering load current changes is evaluated with the proposed end-point determination method. Additionally, this work optimizes the feedback network for smooth loop transition, and incorporates the frequency-locking circuit and the error correction path to address the shortcomings of the hysteretic control. The prototype is fabricated in a 0.13- $\mu \text{m}$ CMOS process with a 1.2-V supply voltage. The converter achieves a near-optimum reference tracking over a wide range of output voltages, from 0.5 to 1 V. Various output voltage steps are measured for different load cases. For a 0.5–1-V output voltage step, with a 90-nH inductor and a 1- $\mu \text{F}$ output capacitor, the up- and down-tracking take 558 and 542 ns, respectively, matching the theoretical result of 533 ns. The prototype achieves a peak efficiency of 93.5%, and over 85% efficiency is measured with $\mathrm {V}_{\mathrm {O}}$ from 0.5 to 1 V and $\mathrm {I}_{\mathrm {O}}$ from 130 to 550 mA.

New level doubling architecture of cascaded multilevel inverter

This study presents a new topology of single-phase cascaded multilevel inverter (CMLI). The proposed topology offers an optimised DC source utilisation, reduced switch count and curtailment of active switches in the conduction path for minimising power losses. It can produce almost twice the number of output voltage steps in comparison to the cascaded H-bridge, hence named level-doubling architecture, and can be operated as both symmetric and asymmetric CMLIs. Identical modules of proposed CMLI precludes requirement of a variety of semiconductors and provides ease for spare management. The modular design also facilitates mass production and enhances system reliability. Furthermore, the proposed topology can be easily extended to high-voltage applications. The proposed design is tested for its practicability by simulations in MATLAB/Simulink and results are verified by experimental set up of a scaled prototype single-phase model.

Family of Multiport Switched-Capacitor Multilevel Inverters for High-Frequency AC Power Distribution

This paper proposes a family of multiport switched-capacitor multilevel inverter (SCMLI) topologies for high-frequency ac power distribution. It employs asymmetric dc voltage sources with a common ground that makes it ideal to be employed in renewable energy farms and modern electric vehicles. The proposed family of step-up SCMLI attains higher number of output voltage steps with optimum component count in comparison to several existing topologies. The problem of capacitor voltage balancing is solved as the capacitors are inherently charged to a finite voltage every half cycle. In-depth study on two staircase modulation strategies, namely, selective harmonic elimination and minimum total harmonic distortion (THD) scheme is presented with study on the variation of switching angles and THD with modulation indices under both schemes. Working principle and analysis are presented for the proposed family of topologies. Simulation outcomes are validated with experimental results under both the aforementioned modulation schemes with equal and unequal output voltage waveform steps.

Experimental verification of trinary DC source cascaded H-bridge multilevel inverter using unipolar pulse width modulation

ABSTRACTMultilevel inverters (MLIs) are an imperative solution for high power and high voltage applications. The MLIs can be classified into two categories such as symmetric and asymmetric. The asymmetric type MLIs has large number of output voltage steps with less number of input DC voltage sources and switching devices. In this paper, a single phase asymmetric (trinary sequence DC source) Cascaded H-Bridge MLI has been developed using unipolar PWM control schemes. The topology can produce 27-level output voltage with the help of 12 switches and 3 DC sources. It has been examined with a diverse combination of multicarrier unipolar PWM control. The PWM control includes Phase Disposition (PDPWM), Alternative Opposition Disposition (APODPWM), Carrier overlapping (COPWM), and Variable Frequency (VFPWM). The harmonic content of output voltage for each technique has been observed with different modulation indices. The demonstration of proposed topology for generating 27-level output voltage has been tested through simulation in MATLAB-SIMULINK and verified with laboratory-based experimental setup. From the results, it is evident that the APODPWM offers quality output voltage with relatively low harmonic distortion. Also, it has been observed that COPWM performance is superior since it delivers relatively higher fundamental RMS output voltage.

FPGA Implementation of a Three-Level Boost Converter-fed Seven-Level DC-Link Cascade H-Bridge inverter for Photovoltaic Applications

This paper presents an optimized single-phase three-level boost DC-link cascade H-bridge multilevel inverter (TLBDCLCHB MLI) system to generate a seven-level stepped output voltage waveform for photovoltaic (PV) applications. The proposed TLBDCLCHB MLI system is obtained by integrating a three-level boost converter (TLBC) with a seven-level DC-link cascade H-bridge (DCLCHB) inverter. It consists of a TLBC, level generation unit (LGU) and phase sequence generation unit (PSGU). When compared with traditional boost converter-fed multilevel inverter systems, the proposed TLBDCLCHB MLI system requires a single DC source, fewer power switches and gate drivers. Reduction in the switch count and number of DC sources makes the system cost effective and requires a smaller installation area. Pulse generation for the power switches of an LGU in a DCLCHB inverter is accomplished by providing proper conducting angles that are generated by optimized conducting angle determination (CAD) techniques. In this paper two CAD techniques i.e., equal-phase CAD (EPCAD) and step pulse wave CAD (SPWCAD) techniques are proposed to evaluate the performance of the proposed system in terms of the total harmonic distortion (THD) and the quality of the stepped output voltage waveform. The proposed system has been modeled and simulated using MATLAB/SIMULINK software. Results are presented and discussed. Also, a prototype model of a single-phase TLBDCLCHB MLI system is developed using a field-programmable gate array (FPGA)-based pulse generation with a resistive load and its performance is analyzed for various operating conditions.

A Generalized Switching Strategy and Capacitor Sizing Algorithm for Granular Multilevel Converters

The granular multilevel converter (GMC) is a multilevel converter built by hybridizing a conventional two-level converter with an asymmetrical cascaded H-bridge converter. Addition of each additional H-bridge submodule doubles the number of the GMC output voltage steps. Thus, with a small number of power electronic switches and associated gate drive signals and circuits, a GMC can offer a high-quality ac voltage to meet the stringent requirements of high-performance drives and grid-tied converters in low and medium voltages. This paper proposes: 1) a generalized switching strategy to control the output voltage as well as capacitor voltages of H-bridge submodules for a GMC with an arbitrary number of submodules $n$ (this proposed strategy is scalable, which allows for easy modification of the voltage rating or the number of the voltage steps of the GMC) and 2) a systematic analysis for optimal sizing of the submodule capacitors to minimize the required total energy of the installed capacitors. Simulation and experimental case studies evaluate the performance of the proposed switching and capacitor sizing algorithms.

Novel Cascaded Switched-Diode Multilevel Inverter for Renewable Energy Integration

In this paper, a new topology of two-stage cascaded switched-diode (CSD) multilevel inverter is proposed for medium-voltage renewable energy integration. First, it aims to reduce the number of switches along with its gate drivers. Thus, the installation space and cost of a multilevel inverter are reduced. The spike removal switch added in the first stage of the inverter provides a flowing path for the reverse load current, and as a result, high voltage spikes occurring at the base of the stepped output voltage based upon conventional CSD multilevel inverter topologies are removed. Moreover, to resolve the problems related to dc source fluctuations of multilevel inverter used for renewable energy integration, the clock phase-shifting (CPS) one-cycle control (OCC) is developed to control the two-stage CSD multilevel inverter. By shifting the clock pulse phase of every cascaded unit, the staircase-like output voltage waveforms are obtained and a strong suppression ability against fluctuations in dc sources is achieved. Simulation and experimental results are discussed to verify the feasibility and performances of the two-stage CSD multilevel inverter controlled by the CPS OCC method.

Symmetric switched diode multilevel inverter structure with minimised switch count

A new symmetric switched diode multilevel inverter with reduced power switches for medium-voltage applications is presented. The proposed topology consists of several double-source units to produce the synthesised stepped output voltage waveform with reduced total harmonic distortion. The required number of insulated bipolar junction transistors, power diode, and total power losses are compared between conventional and recent topologies. The seven-level output voltage is simulated by using simulation software MATLAB/Simulink, and hardware prototype model has been developed to prove the superiority of the proposed topology. Finally, the advantage of the proposed topology is highlighted, and the topology for high-voltage applications is suggested.

Optimal Structures for Cascaded Multilevel Inverter

The general function of a multilevel inverter is to synthesize a desired output voltage from several levels of dc voltages as inputs. In order to increase the steps in the output voltage, a new H- bridge topology is recommended which benefits from a series connection of several sub-multilevel inverters. In addition, for producing an output voltage with a constant number of steps, there are different configurations with a different number of components. In this paper, the optimal structures for H- bridge topology are investigated for various objectives such as minimum number of switches and dc voltage sources and minimum standing voltage on the switches for producing the maximum output voltage steps. Two new algorithms for determining the dc voltage sources magnitudes have been proposed. Finally, in order to verify the theoretical issues, simulation results for 25 level inverter with a maximum output voltage of 120V are presented.

A Novel Approach to GSA, GA and Wavelet Transform to Design Fuzzy Logic Controller for 1ϕ Multilevel Inverter

<p>This paper proposes a novel approach for obtaining a closed loop control scheme based on Fuzzy Logic Controller to regulate the output voltage waveform of multilevel inverter. Fuzzy Logic Controller is used to guide and control the inverter to synthesize a stepped output voltage waveform with reduced harmonics. In this paper, three different intelligent soft-computing methods are used to design a fuzzy system to be used as a closed loop control system for regulating the inverter output. Gravitational Search Algorithm and Genetic Algorithm are used as optimization methods to evaluate switching angles for different combination of input voltages applied to MLI. Wavelet Transform is used as synthesizing technique to shape stepped output waveform of inverter using orthogonal wavelet sets. The proposed FLC controlled method is carried out for a wider range of input dc voltages by considering ±10% variations in nominal voltage value. A 7-level inverter is used to validate the results of proposed control methods. The three proposed methods are then compared in terms of various parameters like computational time, switching angles and THD to justify the performance and system flexibility. Finally, hardware based results are also obtained to verify the viability of the proposed method.</p>

A Novel Six-Level Inverter Topology for Medium-Voltage Applications

In this paper, a novel topology of six-level inverters for a medium-voltage high-power applications is proposed, which consists of inner flying-capacitor inverter (FCI) units and outer two-level inverter units. The proposed topology can reduce the number of devices, components, and isolated sources compared with the existing ones in the case of the same number of output voltage steps, which result in a reduction of the size and weight of the inverters. Also, the total power loss of the proposed topology is lower than that of the diode-clamped inverter (DCI) and FCI. Besides, the estimated cost of the proposed topology is about 60.5% and 81.3% compared with the DCI and FCI, respectively. In addition, the modulation technique and the control strategy for the dc-link capacitor and flying-capacitor voltages are developed for the proposed topology. The effectiveness of the proposed six-level inverter for the medium-voltage applications has been verified by simulation results. Also, the feasibility of the proposed inverter has been proved by experimental results for the prototype at the laboratory.

Capacitor Aging Detection in a DC–DC Converter Output Stage

One of the most significant reliability issues in switching-mode power supplies is electrolytic capacitor degradation caused by aging. This paper proposes an output voltage transient analysis method to detect capacitor wear-out at the output stage of a step-down dc–dc converter. Changes in the converter output voltage dynamics are evaluated by analyzing the output voltage step response with respect to a decrease in the capacitance. The sensitivity of the method is assessed with respect to parameter variations using an equivalent main circuit model. The feasibility of the presented method is verified by experimental tests using a converter prototype. The results show that the presented method is practical and adequate for detecting capacitor degradation in various operating conditions.