Output Transition Time Research Articles

ACCURATE GATE DELAY EXTRACTION FOR TIMING ANALYSIS OF BODY-BIASED CIRCUITS

Static body biasing is a circuit technique in which bias voltage is selected from more than one available voltage after manufacturing. It allows circuits to be designed at more favorable process corners; but effective application requires gate delays to be available for the new process corners, without the expense of re-characterizing individual gates. We show that the new delay of a gate (when body bias is applied) can be extrapolated from its old delay without body bias together with old and new delays of a few reference gates. Output transition time, which is another component of gate timing model, is extrapolated in a similar manner. Experiments with an industrial 32-nm gate library show that the average error in the new gate delays is less than 4.3%.

Pole-Zero, Zero-Pole Canceling Input Shapers

This paper presents the development of an input-shaper/time-delay filter, which exploits knowledge of the zeros of a minimum-phase transfer function to reduce the output-transition time for a rest-to-rest maneuver problem, compared to the traditional zero vibration (ZV) input shaper. The maneuver time of the robust input shaper presented in this work will correspondingly have a smaller maneuver time compared to the zero vibration derivative (ZVD) input-shaper. The shaped profile is changing with time even after the completion of the maneuver similar to postactuation controllers. All the traditional technique for addressing multiple modes and desensitizing the filter over a specified domain of uncertainties are applicable to the technique presented in this paper.

Preview Control of Dual-Stage Actuator Systems for Superfast Transition Time

This paper introduces a preview control design method to reduce the settling time of dual-stage actuators (DSAs). A DSA system is comprised of two actuators connected in series, a primary (coarse) actuator, and a secondary (fine) actuator. The objective of the proposed design is to account for the redundancy of actuators and use the information of future reference levels in order to compute a pair of inputs to be applied before the output transition time. Experimental results show that the proposed design method significantly reduces the output transition time when compared to conventional forms of DSA control design.

Low energy multi-stage level converter for sub-threshold logic

Robustness is the main concern in the design of level converters (LCs) for sub-threshold voltage applications. Besides this, when a sub-threshold voltage is applied to the input of the LC, the output transition time of the LC is very long and the short-circuit current through the logic gates that are driven by the LC output is large. The circuit's total energy consumption increases. In this study, a novel single-stage LC that can operate robustly for sub-threshold signal is firstly presented. Based on the single-stage LC circuit, a multi-stage sub-threshold LC structure is proposed, which features similar operation robustness, and at the same time, greatly reduces the output transition time of the LC. As a result, the circuit's total energy consumption (including that of the fanout logic gates) is significantly reduced. Extensive simulations were carried out to demonstrate the operation robustness of the authors proposed multi-stage sub-threshold LC. Measurements were done on a fabricated test chip to verify the operation and demonstrate the performance improvement of the design.

Simple and accurate modeling of the output transition time in nanometer CMOS gates

In this paper, a model of the output transition time on nanometer CMOS gates is proposed. The development of this model follows the general approach used by Auvergne in (IEE Electron. Lett. 2002; 38(4):175–177, IEEE Trans. Circuits Systems—part I 2000; 47(9):1362–1369, IEEE Proc. ISCAS 2001; 5:363–366, IEEE Trans. Computer-Aided Design Integr. Circuits Systems 2002; 21(11):1352–1363), which separately models the output transition time under fast and slow inputs. The proposed model is based on a combined transient and DC circuit analysis, and requires a few simulations. This approach allows for strongly reducing the number of required parameters and simulations compared with other models proposed in the literature. The analytical model proposed is very simple and has a clear physical meaning, thereby allowing an efficient implementation in CAD tools performing timing analysis, as well as an easy scalability through different processes and technology generations. Spectre simulations on a 65 nm CMOS technology and the 45, 32, 22 nm Berkeley Predictive Technology Models (BPTM) [Berkeley Predictive Technology Model (BPTM). [email protected]/25/2008: http://www.eas.asu.edu/∼ptm/] show that the model accuracy is the same as the state-of-the-art models, with an average error of only 4%. Comparison with currently used table-based models showed also a significant reduction in the CPU time needed to simulate and characterize CMOS logic gates. Copyright © 2009 John Wiley & Sons, Ltd.

An optimal feedforward control design for the set-point following of MIMO processes

In this paper we propose a new methodology for the design of a feedforward action for the improvement of the set-point following performance of feedback controlled square MIMO processes. In particular, by exploiting an analytical decoupling technique, the feedforward signals are determined in order to achieve predefined output transition times, by assuming that the transfer function matrix of the system consists of first order plus dead time transfer functions. An analytical expression of the feedforward signal is derived and this allows to solve easily a multiobjective optimisation problem in order to minimise the transition time of each output subject to constraints of the actuators. Simulation as well as experimental results demonstrate the effectiveness of the method.

Minimum-Time/Energy, Output Transitions for Dual-Stage Systems

This article addresses the optimal (minimum-time/energy) trajectory design for changing the output from one value y̱ to another y¯ within a finite time interval [0,tf] called the output-transition time interval. The output should be maintained constant (at the desired value) outside the output-transition time interval. The main contribution of this article is to establish the existence of a solution to the problem when preactuation (input applied during time t<0) and postactuation (input applied during time t>tf) are allowed. The advantage of using pre- and postactuation inputs is illustrated with an experimental dual-stage actuator system.

Characterization of Standard Cells for Intra-Cell Mismatch Variations

With the adoption of statistical timing across industry, there is a need to characterize all gates/cells in a digital library for delay variation (referred to as statistical characterization). Statistical characterization needs to be performed efficiently with acceptable accuracy as a function of several process and environmental parameter variations. In this paper, we propose an approach to consider intra-cell process mismatch variations to characterize a cell's delay and output transition time (output slew) variations. A straightforward approach to address this problem is to model these mismatch variations by characterizing for each device fluctuation separately. However, the runtime complexity for such characterization becomes of the order of number of devices in the cell and the number of simulations required can easily become infeasible. We analyze the fluctuations in switching and nonswitching devices and their impact on delay variations. Using these properties of the devices, we propose a clustering approach to characterize for cell's delay variations due to intra-cell mismatch variations. The proposed approach results in as much as 12X runtime improvement with acceptable accuracy, compared with Monte Carlo simulation. We show that this approach ensures an upper bound on the results while keeping the number of simulations for each cell independent of the number of devices.

Statistical Gate Delay Model for Multiple Input Switching

In this paper, we propose a calculation method of gate delay for SSTA (Statistical Static Timing Analysis) considering MIS (Multiple Input Switching). In SSTA, statistical maximum/minimum operation is necessary to calculate the latest/fastest arrival time of multiple input gate. Most SSTA approaches calculate the distribution in the latest/fastest arrival time under SIS (Single Input Switching assumption), resulting in ignoring the effect of MIS on the gate delay and the output transition time. MIS occurs when multiple inputs of a gate switch nearly simultaneously. Thus, ignoring MIS causes error in the statistical maximum/minimum operation in SSTA. We propose a statistical gate delay model considering MIS. We verify the proposed method by SPICE based Monte Carlo simulations. Experimental results show that the neglect of MIS effect leads to 80% error in worst case. The error of the proposed method is less than 20%.

Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations

Process variation is becoming a primal concern in timing closure of LSI (Large Scale Integrated Circuit) with the progress of process technology scaling. To overcome this problem, SSTA (Statistical Static Timing Analysis) has been intensively studied since it is expected to be one of the most efficient ways for performance estimation. In this paper, we study variation of output transition-time. We firstly clarify that the transition-time variation can not be expressed accurately by a conventional first-order sensitivity-based approach in the case that the input transition-time is slow and the output load is small. We secondly reveal quadratic dependence of the output transition-time to operating margin in voltage. We finally propose a procedure through which the estimation of output transition-time becomes continuously accurate in wide range of input transition-time and output load combinations.

Optimal Output Transitions for Dual-Stage Systems

This paper solves the minimum-energy output-transition problem for dual-stage systems, such as dual-stage disk-drives, where the second actuator can be used to increase the bandwidth and precision of conventional single-actuator systems. The objective is to find optimal inputs that change the system output from an initial value to a final value during a specified output-transition time interval. The paper shows that, for dual-stage systems, inputs applied outside the output-transition time interval (i.e., pre- and postactuation) can substantially reduce the required input energy. For an experimental dual-stage system, results are presented to show that the input energy can be reduced by 65% with the use of pre- and postactuation inputs when compared to standard methods that do not use such pre- and postactuation.

Parameterized Non-Gaussian Variational Gate Timing Analysis

As technology scales down, timing verification of digital integrated circuits becomes an extremely difficult task due to the gate and wire variability. Therefore, statistical timing analysis (denoted by sigmaTA) is becoming unavoidable. In this paper, two new approaches for doing variational gate TA for Gaussian and non-Gaussian sources of variation in parameterized sigmaTA are presented. To start, a variational RC-pi load is approximated by using a canonical first-order model. Next, an accurate variational gate TA (VGTA) technique, which accounts for variational RC-pi loads, variational input transitions, and a variation-aware gate library, is introduced. The proposed method relies on static effective-capacitance-calculation method and its variational form. Experimental results demonstrate that VGTA exhibits an average error of 4% for gate delay and output transition time with respect to the Monte Carlo simulation with 104 samples. Next, a more efficient VGTA [called Fast VGTA (F-VGTA)] based on a single-iteration variational effective capacitance calculation is presented. Experimental results show that F-VGTA achieves an average error of 7% for gate delay and output transition time with respect to the Monte Carlo simulation with 104 samples but with runtimes that are about two times faster than VGTA.

PARETO OPTIMAL FEEDFORWARD CONSTRAINED REGULATION OF MIMO LINEAR SYSTEMS

In this paper we present a methodology for the feedforward minimum-time regulation of Multiple-Input-Multiple-Output (MIMO) square linear systems. The aim is to synthesize bounded smooth input functions, subject to non-saturating constraints on the inputs and their derivatives until an arbitrary predefined order, in order to provide given transitions of the outputs. The posed problem yields to the construction of a Pareto set of output transition times, which is determined by employing an ad hoc parametrized family of output transition functions and a suitably devised input-output inversion procedure. Illustrative examples are given in order to show the effectiveness of the methodology.

Minimum-Energy Output Transitions for Linear Discrete-Time Systems: Flexible Structure Applications

This paper finds minimum-energy inputs to change the position of an output point, on a flexible structure, from one value to another. Current methods transform the output-transition problem into a state-to-state transition problem by constraining the initial and final states of the output transition, for example, to be rest (rigid-body) configurations of the flexible structure. However, the choice of the initial and final states can be ad hoc, and the resulting output-transition cost (input energy) might not be minimum. The contribution of this paper is the direct solution of the optimal output-transition problem; the problem is posed and solved for general linear discrete-time systems. The novelty of the proposed approach is that inputs are not applied just during the output-transition time interval; rather, inputs are also applied outside the output-transition time interval, that is, before the beginning of and after the end of the output-transition time interval. (These inputs are called pre- and postactuation.) The implications of using pre- and postactuation are illustrated by using an example of discrete-time flexible structure model, which consists of a flexible rod connecting two masses. Simulation results are presented, which show substantial reduction of output-transition costs with the use of the proposed method when compared to the use of the standard state-to-state transition approach.

A new design for a PID plus feedforward controller

In this paper, a new design and tuning procedure for a PID plus feedforward controller is proposed. It consists of determining a feedforward signal in order to achieve a predefined process output transition time assuming a first order plus dead time model of the process. Then, the PID parameters are tuned by any conventional method in order to assure a good load disturbance rejection and the reference signal to the closed-loop system is obtained by filtering appropriately the set-point step signal. Simulation and experimental results show that the method outperforms the typical (inverse) model-based approach despite its simplicity and it is therefore suitable to implement in Distributed Control Systems as well as in single-station controllers.

Propagation delay and short-circuit power dissipation modeling of the CMOS inverter

This paper introduces a new, accurate analytical model for the evaluation of the delay and the short-circuit power dissipation of the CMOS inverter. Following a detailed analysis of the inverter operation, accurate expressions for the output response to an input ramp are derived. Based on this analysis improved analytical formulae for the calculation of the propagation delay and short-circuit power dissipation, are produced. Analytical expressions for all inverter operation regions and input waveform slopes are derived, which take into account the influences of the short-circuit current during switching, and the gate-to-drain coupling capacitance. The effective output transition time of the inverter is determined in order to map the real output voltage waveform to a ramp waveform for the model to be applicable in an inverter chain. The final results are in very good agreement with SPICE simulations.

Modelling output waveform and propagation delay of a CMOS inverter in the submicron range

An accurate, analytical model is presented for the evaluation of the CMOS inverter delay in the submicron regime. Following an exhaustive analysis of the inverter operation, accurate expressions of the output response to an input ramp are derived, which result in the analytical calculation of the propagation delay. These expressions are valid for all the inverter operation regions and input waveform slopes, and take into account the influences of the short-circuit current and the gate–drain coupling capacitance. The effective output transition time of the inverter is determined, in order to map the real output waveform to a ramp waveform for the model to be applicable to CMOS gate chains. The results are in very good agreement with SPICE simulations.

Effects of simultaneous switching noise on the tapered buffer design

Complementary metal-oxide-semiconductor (CMOS) output buffers, comprised of a series of tapered inverters, are used to drive large off-chip capacitances. The ratio of the size of transistors between two consecutive stages is the buffer taper factor. With higher frequency of operation and simultaneous switching of the output drivers, the parasitic inductance present at the pin-pad-package interface results in significant switching noise on the power lines. A comprehensive analysis and estimate of simultaneous switching noise (SSN) including the velocity saturation effects seen in the submicron transistors during the switching of output drivers is presented. The effect of SSN on the overall buffer propagation delay and transition time is discussed. The presence of SSN results in an increase in the optimum taper factor between inverter stages for a given capacitive load. Beyond a critical value, the output transition time of a tapered buffer increases with reducing taper factor due to SSN. SSN can be reduced by skewing the switching of output buffers, SPICE simulation results show that skewing buffer switching with additional inverter stages reduces SSN and increases buffer propagation delay.

Split inherent-capacitive load model for CMOS buffer design

CMOS buffers are made up of a series of tapered inverters with each inverter driving a larger inverter. A split inherent-capacitance load model has been used in the design of tapered buffers, giving an improved value for the optimum taper factor between inverter stages. The overall buffer propagation delay and output transition time so obtained are smaller than those obtained using the split-capacitive load buffer model, but there is a small increase in area and power dissipation.

A comprehensive delay model for CMOS inverters

A method to accurately calculate the delay and the output transition-time of a CMOS inverter for any input ramp and output loading is considered. This paper is an extension of Sakurai's work (1990) on delay modeling of inverters for fast input ramps. We observed that two different mechanisms, that can be adequately modeled analytically, govern the delay and the output transition-time of an inverter in two extreme cases: infinitely fast and infinitely slow inputs. These extreme points are joined by a curve that can predict the delay and the output transition-time for any input. We found that the delay and the output transition-time for an inverter with small fanouts are similar to those for large input transition-times. This behavior is explained by the use of I-V trajectories. We describe a method to generate parameters to model delay and output transition-time for different fanouts and input transition-times; this method can be generalized to add parameters for different temperatures and supply voltages. Given a new process technology and its corresponding SPICE-model parameters, our delay calculation scheme comprises characterizing a minimal number of coefficients for each new technology (a one-time process) and evaluating the analytical forms thereafter to obtain the delay and the transition-time. Our delay equations also explain negative delays that arise in case of slow input rise-times. A program incorporating the above idea has been implemented in C. Delay and transition-time values obtained from the program have been found to be typically within 3% of SPICE. >