Simple and accurate modeling of the output transition time in nanometer CMOS gates

Abstract

In this paper, a model of the output transition time on nanometer CMOS gates is proposed. The development of this model follows the general approach used by Auvergne in (IEE Electron. Lett. 2002; 38(4):175–177, IEEE Trans. Circuits Systems—part I 2000; 47(9):1362–1369, IEEE Proc. ISCAS 2001; 5:363–366, IEEE Trans. Computer-Aided Design Integr. Circuits Systems 2002; 21(11):1352–1363), which separately models the output transition time under fast and slow inputs. The proposed model is based on a combined transient and DC circuit analysis, and requires a few simulations. This approach allows for strongly reducing the number of required parameters and simulations compared with other models proposed in the literature. The analytical model proposed is very simple and has a clear physical meaning, thereby allowing an efficient implementation in CAD tools performing timing analysis, as well as an easy scalability through different processes and technology generations. Spectre simulations on a 65 nm CMOS technology and the 45, 32, 22 nm Berkeley Predictive Technology Models (BPTM) [Berkeley Predictive Technology Model (BPTM). [email protected]/25/2008: http://www.eas.asu.edu/∼ptm/] show that the model accuracy is the same as the state-of-the-art models, with an average error of only 4%. Comparison with currently used table-based models showed also a significant reduction in the CPU time needed to simulate and characterize CMOS logic gates. Copyright © 2009 John Wiley & Sons, Ltd.