Output Queues Research Articles

Evolutionary approach for buffer management in asynchronous transfer mode networks

Fuzzy systems are becoming more widespread in many applications and it is possible to implement using very large scale integration technology. This article deals with buffer management scheme based on evolutionary computing for shared memory asynchronous transfer mode switches. Output queuing is done in the proposed system to increase the throughput. The objective of this research is to model a fuzzy buffer management system that sets the threshold for the output ports in the shared memory. Genetic algorithm technique is used to optimise the fuzzy system parameters derived for each switch size and offers a high degree of scalability. The performance of designed 'fuzzy-genetic algorithm' buffer management system is compared with the push-out mechanism (ideal mechanism) and dynamic threshold mechanism. Fuzzy system is simulated using the MODELSIM software and genetic algorithm is simulated using the JAVA language.

Active Queue Management Algorithm Based on Fuzzy Sliding Model Controller

The active queue management (AQM) problem of networks is discussed. An AQM scheme is presented based on improved sliding model controller. The proposed controller combines the excellent characteristics of linear sliding model controller (LSMC) and the terminal sliding model controller (TSMC). The LSMC is used to speed up the error convergence when the error is greater than one, and the TSMC is adopted to guarantee the error convergence to zero in a finite time when the error is around the zero. The chattering in the conventional sliding model control systems is avoided with the employed continuous controller. The simulation results show that the proposed scheme has strong robust against the network modeling uncertainties and disturbances, as well as leads to the convergence of the output queue to the desired value quickly and precisely than employing either LSMC or TSMC alone.

A weightiest Scheduling Based on Queue Length and Queue Delay Restriction for Asynchronous Optical Packet Switch

Packet scheduling plays an important role in the asynchronous optical switched node. An intelligence scheduling algorithm can reduce packet loss probability and increase the throughput to guarantee the quality of service. A weighted scheduling algorithm based on the queue length associated with waiting delay restriction was proposed to solve the problem of packet queue starvation and time delay. The work has contributed with a much powerful scheduling mechanism which reduces resource contention at the asynchronous OPS core nodes and guarantees a reasonable packet delay thanks to its weighted scheduling algorithm based on queue length and waiting delay for variable length OPS network. The scheduler calculates every input port with NxK virtual output queue (VOQ) weight and schedules the maximal weight queue packets to available output channel. The analysis and simulation results show that the proposed scheduling has high throughput and low packet loss ratio.

A Novel Analytical Model for Switches With Shared Buffer

Switches with a shared buffer have lower packet loss probabilities than other types of switches when the sizes of the buffers are the same. In the past, the performance of shared buffer switches has been studied extensively. However, due to the strong dependencies of the output queues in the buffer, it is very difficult to find a good analytical model. Existing models are either accurate but have exponential complexities or not very accurate. In this paper, we propose a novel analytical model called the Aggregation model for switches with shared buffer. The model is based on the idea of induction: first find the behavior of two queues, then aggregate them into one block; then find the behavior of three queues while regarding two of the queues as one block, then aggregate the three queues into one block; then aggregate four queues, and so on. When all queues have been aggregated, the behavior of the entire switch will be found. This model has perfect accuracies under all tested conditions and has polynomial complexity.

Emulating output queueing with parallel packet switches

This work employs an approximate Markov chain to analyze that a parallel packet switch (PPS) can emulate a first-come first-served (FCFS) output-queued (OQ) packet switch only operating slower than the external line rate. The PPS comprises multiple packet switches operating independently and in parallel. The PPS class is characterized by deployment of parallel center-stage switches with memory buffers running slower than the external line rate. Each lower speed packet switch operates at a fraction of the external line rate R. For example, each packet switch can operate at internal line rate R/ K, where K is the number of center-stage switches. This work presents a proposed novel Markov chain model successfully exhibits these performance characteristics for throughput, cell delay and cell drop rate. This novel Markov chain model extends from our previous paper [Chia-Lung Liu, Woei Lin, Performance analysis of the sliding-window parallel packet switch, in: IEEE 40th International Conference on Communications 2005, ICC 2005, May 16–20, 2005; Chia-Lung Liu, Woei Lin, Evaluation and analysis of the sliding-window parallel packet switch, in: IEEE 19th International Conference on Advanced Information Networking and Applications, AINA, vol. 2, 2005, pp. 355–358]. Simulation comparison demonstrates that the chains are accurate for practical network loads. With the proposed model, major finding are that: (1) it is theoretically possible for the throughput and cell drop rates of a PPS to emulate those of a FCFS-OQ packet switch when each lower speed packet switch operates at a rate of approximately R/ K; and, (2) this work also demonstrates that it is theoretically possible for the cell delay of a PPS to emulate that of FCFS-OQ packet switch when each lower speed packet switch operates at a rate of approximately (3R/cell delay of FCFS-OQ switch). Additionally, this work develops and investigates a novel PIAO PPS which distributes cells or variable-length packets to center-stage switches and uses multiplexers with push-in arbitrary-out (PIAO) queues.

An efficient scheduling algorithm for input-queued switches

This letter presents an efficient scheduling algorithm DTRR (Dual-Threshold Round Robin) for input-queued switches. In DTRR, a new matched input and output by round robin in a cell time will be locked by two self-adaptive thresholds whenever the queue length or the wait-time of the head cell in the corresponding Virtual Output Queue (VOQ) exceeds the thresholds. The locked input and output will be matched directly in the succeeding cell time until they are unlocked. By employing queue length and wait-time thresholds which are updated every cell time simultaneously, DTRR achieves a good tradeoff between the performance and hardware complexity. Simulation results indicate that the delay performance of DTRR is competitive compared to other typical scheduling algorithms under various traffic patterns especially under diagonal traffic.

Low‐delay scheduling algorithm that considers fairness between ports

AbstractA Virtual Output Queuing (VOQ) input buffer type switch provided with a buffer in each input port is proposed in this paper as an input buffer type switch that avoids Head‐of‐Line (HoL) blocking. A scheduling algorithm for a multiple VOQ input buffer type switch is also proposed. As a representative algorithm we use a Two‐Dimensional Round Robin (2DRR) scheduling algorithm that achieves low‐delay and has iSLIP to avoid starvation as well as high fairness between ports. This paper also proposes a layered scheduling algorithm for a VOQ input buffer type switch with an objective of fairness between ports and switching with lower delay. The frequency of packets not being output is reduced regardless of whether an output port is empty by using up patterns of all I/O pairs in N input N output switches. The N input N output switching is divided into smaller units. Fairness between the units is achieved by successively shifting the order of priority of each unit that will be switched. Simulations were used to evaluate the effectiveness of the proposed scheduling algorithm. © 2007 Wiley Periodicals, Inc. Electron Comm Jpn Pt 1, 90(6): 43–52, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecja.20313

Rate adaptation for wireless video streaming based on error statistics

This paper presents a new rate-control algorithm for live video streaming over wireless IP networks, which is based on selective frame discarding. In the proposed mechanism excess 'P' frames are dropped from the output queue at the sender using a congestion estimate based on packet loss statistics obtained from RTCP feedback and from the Data Link (DL) layer. The performance of the algorithm is evaluated through computer simulation. This paper also presents a characterisation of packet losses owing to transmission errors and congestion, which can help in choosing appropriate strategies to maximise the video quality experienced by the end user.

A new scalable service discipline for real-time traffic: The framed-deadline scheduler

Quality of Service (QoS) support in a scalable and low-complexity fashion is important in high-speed networks carrying real-time traffic. There are service disciplines that can provide end-to-end bandwidth and delay guarantees. However, they are designed to operate with expensive output queuing switches or with combined input–output queuing (CIOQ) switches that require very complicated fabric schedulers. We propose a novel service discipline, the Framed-deadline Scheduler (FDS), for connection oriented networks. FDS can work with a CIOQ packet switch to provide the same end-to-end QoS guarantees as service disciplines that only work with output queuing switches. The fabric scheduler of the CIOQ switch is simple and the implementation of FDS has O(1) complexity. Hence, FDS is a scalable service discipline that can provide end-to-end QoS guarantees for real-time traffic in high-speed networks.

Quality of service provision in combined input and crosspoint queued switches without output queueing match

Packet switches play one of the most critical roles in supporting quality of service (QoS) in computer communication networks. Although the output queued (OQ) switch architecture can achieve optimal QoS performance, it is not a practical architecture for high-speed switching due to the switching fabric speedup, which requires complex implementation. Combined input and crosspoint queued (CICQ) switches employ the crossbar-based switching fabric structure and apply buffers at both ingress port modules and crosspoints inside the switching fabric. This switch architecture is promising to achieve high performance without complex implementation. Current available approaches for QoS provision in CICQ switches are based on the output queueing match technique. Although such approaches can provide bandwidth and delay guarantees, they still require switching fabric speedup, which may significantly increase the implementation complexity of high-speed CICQ switches. In this paper, we compare the QoS performance that can be achieved in CICQ switches with the QoS performance guaranteed by OQ switches. Based on this comparison, we investigate the possibility of achieving equivalent QoS guarantees in a CICQ switch as in an OQ switch without output queueing match, thus with no switching fabric speedup. Our analysis shows that if sufficient crosspoint buffer space is allocated, a CICQ switch employing a typical scheduling algorithm, such as weighted fairing queueing (WFQ), can provide an identical bandwidth guarantee as the OQ switches without any switching fabric speedup, and can achieve equivalent delay performance as the OQ switch by slightly increasing bandwidth allocation.

On the Maximum Throughput of a Combined Input-Crosspoint Queued Packet Switch

Combined input-crosspoint buffered (CICB) packet switches have been of research interest in the last few years because of their high performance. These switches provide higher performance than input-buffered (IB) packet switches while requiring the crosspoint buffers run at the same speed as that of the input buffers in IB switches. Recently, it has been shown that CICB switches with one-cell crosspoint buffers, virtual output queues, and simple input and output arbitrations, provide 100% throughput under uniform traffic. However, it is of general interest to know the maximum throughput that a CICB switch, with no speedup, can provide under admissible traffic. This paper analyzes the throughput performance of a CICB switch beyond uniform traffic patterns and shows that a CICB switch with one-cell crosspoint buffers can provide 100% throughput under admissible traffic while using no speedup.

A simulation study on the performance of task-determination rules and delivery-dispatching rules for multiple-load AGVs

In this paper, the control problem of multiple-load automated guided vehicles (AGVs) is studied. A control process that identifies four problems faced by multiple-load AGVs is proposed. The first problem is the task-determination problem, in which a multiple-load AGV determines whether its next task is a pickup task or a delivery task. The second problem is the delivery-dispatching problem, in which a multiple-load AGV determines which delivery point it should visit next if its next task is a delivery task. The third problem is the pickup-dispatching problem, in which a multiple-load AGV determines which pickup point it should visit next if its next task is a pickup task. Finally, the fourth problem is the load-selection problem, which requires a multiple-load AGV to determine which load it should pick up from the output queue of a pickup point. This paper focuses on the first and second problems. Different task-determination rules and delivery-dispatching rules are proposed for these two problems. For the problems that are not the main focus of this study, rules found in the literature or real systems are adopted in this study. The objective of this study is twofold. First, we need to understand how well the proposed rules will perform in different performance measures, e.g. the system's throughput and the mean lateness of parts. Second, we need to understand the mutual effects that different types of rules have on each other, so that the best combination of rules can be identified. Computer simulations were conducted to test the performance of the proposed rules. It is hoped the knowledge learned from this study can be beneficial to real multiple-load AGV systems similar to the one studied here.

A simulation study on the performance of pickup-dispatching rules for multiple-load AGVs

In this paper, the pickup-dispatching problem of multiple-load AGVs (automated guided vehicles) is studied. This problem is defined in the multiple-load control process proposed by Ho and Chien [Ho, Y. C., & Chien, S. H. (2004). A simulation study on the performance of delivery-dispatching rules for multiple-load AGVs. In E. Kozan (Ed.), Proceedings of abstracts and papers (On CD-ROM) of the 5th Asia-Pacific industrial engineering and management systems conference and the 7th Asia-Pacific division meeting of the international foundation of production research (pp. 18.1.1-18.1.15). Brisbane: APIEMS]. Their control process identifies four problems faced by a multiple-load AGV. These problems are task-determination, delivery-dispatching, pickup-dispatching and load-selection. This paper focuses on the third problem. For this problem, nine pickup-dispatching rules are proposed and studied. The first, second and fourth problems are not the main focus of this study, thus only one task-determination rule, one delivery-dispatching rule and two load-selection rules are adopted for them. The objective of this study is twofold. First, to understand the performance of the proposed rules in different performance measures, e.g., the system's throughput, the mean flow time of parts (MFTP) and the mean tardiness of parts (MTP). Second, the effects that the proposed rules have on each other's performance are investigated. Computer simulations are used to achieve these objectives. The experimental results reveal a rule that dispatches vehicles to the machine with the greatest output queue length is the best in all performance measures. Also, distance-based or due-time-based rules do not perform as well as queue-based rules. It is also found that the performance of pickup-dispatching rules is affected by different load-selections rules.

Efficient Scheduling for SDMG CIOQ Switches

Combined input and output queuing (CIOQ) switches are being considered as high-performance switch architectures due to their ability to achieve 100% throughput and perfectly emulate output queuing (OQ) switch performance with a small speedup factor S. To realize a speedup factor S, a conventional CIOQ switch requires the switching fabric and memories to operate S times faster than the line rate. In this paper, we propose to use a CIOQ switch with space-division multiplexing expansion and grouped input/output ports (SDMG CIOQ switch for short) to realize speedup while only requiring the switching fabric and memories to operate at the line rate. The cell scheduling problem for the SDMG CIOQ switch is abstracted as a bipartite k-matching problem. Using fluid model techniques, we prove that any maximal size k-matching algorithm on an SDMG CIOQ switch with an expansion factor 2 can achieve 100% throughput assuming input line arrivals satisfy the strong law of large numbers (SLLN) and no input/output line is oversubscribed. We further propose an efficient and starvation-free maximal size k-matching scheduling algorithm, kFRR, for the SDMG CIOQ switch. Simulation results show that kFRR achieves 100% throughput for SDMG CIOQ switches with an expansion factor 2 under two SLLN traffic models, uniform traffic and polarized traffic, confirming our analysis.

Measurement of Processing and Queuing Delays Introduced by an Open-Source Router in a Single-Hop Network

Measurement of the main contributions to the single-hop delay introduced by an open-source router is dealt with. A new method is proposed, which is capable of distinguishing the time interval during which a generic packet stays in either input or output queue (queuing delay) of the router under analysis and the time interval characterizing the effective routing process (processing delay) the packet undergoes. Thanks to proper measurement probes, i.e., kernel-layer functions, the method makes the occurring time of events of interest available at the application layer, thus giving the possibility of separately evaluating the aforementioned delays and, ultimately, pursuing a deeper insight of the considered router. After brief remarks concerning various delays a packet experiences when passing through a generic router, the measurement principle underlying the method is presented in detail. Particular emphasis is put on its capability of locally monitoring the transit of each packet from the input to the output port of an open-source router along with main features and implementation issues of the proposed measurement probes. Results obtained in many experiments carried out on a suitable test bed in different operating conditions are then given in order to highlight the method's reliability and effectiveness.

An integrated fuzzy-GA approach for buffer management

This paper deals with a novel buffer management scheme based on evolutionary computing for shared-memory asynchronous transfer mode (ATM) switches. The philosophy behind it is adaptation of the threshold for each logical output queue to the real traffic conditions by means of a system of fuzzy inferences. The optimal fuzzy system is achieved using a systematic methodology, based on genetic algorithms (GAs), which allows the fuzzy system parameters to be derived for each switch size, offering a high degree of scalability to the fuzzy control system. Its performance is comparable to that of the push-out (PO) mechanism, which can be considered ideal from a performance viewpoint, and at any rate much better than that of threshold schemes based on conventional logic. In addition, the fuzzy threshold (FT) scheme is simple and cost-effective when implemented using VLSI technology

Providing service guarantees in high-speed switching systems with feedback output queuing

We consider the problem of providing per-customer service guarantees in a high-speed packet switch typically situated at the edge between a set of customers and a service provider network. As basic requirements, the switch should be scalable to high speeds per port, a large number of ports, and a large number of customers (macroflows) with independent guarantees. Existing scalable solutions are based on virtual output queuing, which is computationally complex when required to provide service guarantees for a large number of macroflows. We present a novel architecture for packet switching that provides support for such service guarantees. A cost-effective fabric with small external speedup is combined with a feedback mechanism that enables the fabric to be virtually lossless, thus avoiding packet drops indiscriminate of macroflows' behavior. Through analysis and simulation, we show that this architecture provides accurate support for service guarantees, has low computational complexity, and is scalable to very high port speeds.

THREE-STAGE CLOS-NETWORK SWITCH ARCHITECTURE WITH BUFFERED CENTER STAGE FOR MULTI-CLASS TRAFFIC

Memory-space-memory (MSM) arrangement is a popular architecture to implement three-stage Clos-network switches with distributed arbitration. The scalability of this architecture, however, is limited by the round-trip communication delay between the first and the second stages. Moreover, virtual output queue does not completely remove the blocking in the buffered modules under multi-class traffic. In this paper, we propose a competition-free memory–memory–memory (CFM3) switch which is a three-stage Clos-network switch with buffered center stage. The CFM3 deploys buffered modules in all stages to simplify communication between stages. To reduce the blocking, each module is equipped with a set of buffers fully separated according to the destinations, classes of packets and the input ports of the module. Despite the buffered center stage, CFM3 is free from reordering problem due to simple control mechanism. Simulation result shows the delay of the proposed CFM3 switch closely approaches that of the ideal Output Queued switch under multi-class traffic when strict priority policy popularly used for class-based switch is deployed. The CFM3 achieves 100% throughput under uniformly distributed four-class traffic with strict priority policy while traditional MSM switch records about 77% throughput.

Analysis of Distributed DDQ for QoS Router

In a packet switching network, congestion is unavoidable and affects the quality of real-time traffic with such problems as delay and packet loss. Packet fair queuing (PFQ) algorithms are well-known solutions for quality-of-service (QoS) guarantee by packet scheduling. Our approach is different from previous algorithms in that it uses hardware time achieved by sampling a counter triggered by a periodic clock signal. This clock signal can be provided to all the modules of a routing system to get synchronization. In this architecture, a variant of the PFQ algorithm, called digitized delay queuing (DDQ), can be distributed on many line interface modules. We derive the delay bounds in a single processor system and in a distributed architecture. The definition of traffic contribution improves the simplicity of the mathematical models. The effect of different time between modules in a distributed architecture is the key idea for understanding the delay behavior of a routing system. The number of bins required for the DDQ algorithm is also derived to make the system configuration clear. The analytical models developed in this paper form the basis of improvement and application to a combined input and output queuing (CIOQ) router architecture for a higher speed QoS network.

Matching output queueing with a multiple input/output-queued switch

We have previously proposed an efficient switch architecture called multiple input/output-queued (MIOQ) switch and showed that the MIOQ switch can match the performance of an output-queued switch statistically. In this paper, we prove theoretically that the MIOQ switch can match the output queueing exactly , not statistically, with no speedup of any component. More specifically, we show that the MIOQ switch with two parallel switches (which we call a parallel MIOQ (PMIOQ) switch in this paper) can provide exact emulation of an output-queued switch with a broad class of service scheduling algorithms including FIFO, weighted fair queueing (WFQ) and strict priority queueing regardless of incoming traffic pattern and switch size. To do that, we first propose the stable strategic alliance (SSA) algorithm that can produce a stable many-to-many assignment, and prove its finite, stable and deterministic properties. Next, we apply the SSA algorithm to the scheduling of a PMIOQ switch with two parallel switches, and show that the stability condition of the SSA algorithm guarantees for the PMIOQ switch to emulate an output-queued switch exactly. To avoid possible conflicts in a parallel switch, each input-output pair matched by the SSA algorithm must be mapped to one of two crossbar switches. For this mapping, we also propose a simple algorithm that requires at most 2N steps for all matched input-output pairs. In addition, to relieve the implementation burden of N input buffers being accessed simultaneously, we propose a buffering scheme called redundant buffering which requires two memory devices instead of N physically-separate memories. In conclusion, we demonstrate that the MIOQ switch requires two crossbar switches in parallel and two physical memories at each input and output to emulate an output-queued switch with no speedup of any component.