Output Logic Levels Research Articles

Performance Evaluation of a Low Energy Universal Gate for VLSI with 16nm Technology

NAND & NOR logic gates are general purpose logic gates that can be used to build other logic gates. This article describes a new NAND gate based on 3T (3 transistors) which has the correct output logic level and behaves similarly to the previous design NAND gate logic. The proposed structure has faster processing and lower power consumptionwhat makes it ideal for large-scale integration (VLSI) applications. Typical 16nm CMOS fabrication techniques were used for simulation, building Nand Gate, and to compare it to Nand Gate with different techniques and design such as using four transistors. It turns out that the amount of delay in this desgin with the selected technology compared to other projects with other technologies is less, that is, 0.02966 ns, which proves that the smaller the delay, the faster the gate operates.

Boolean Logic Function Realized by Phase-Change Blade Type Random Access Memory

Phase-change random access memory (PCRAM) has been considered as one of the most promising candidates for future nonvolatile storage applications. Recent advent of the blade-type PCRAM further shed a light on its commercial prospect due to its much smaller energy consumption than the conventional Lance-type PCRAM. However, the logic computing capability of the blade-type PCRAM remains vague up-to-date. To deeply study its function versatility, we developed a comprehensive three-dimensional model based on the classical nucleation-growth theory to mimic the crystallization and amorphization processes of the blade-type PCRAM device. According to this well-established model, the device resistance after phase transformation was calculated with respect to different crystallization and amorphization pulses. By pertaining high and low pulse magnitudes and device resistances to appropriate input and output logic levels, a variety of Boolean logic functions, including “ NAND,” NOR,” AND,” OR,” and “ NOT,” were successfully achieved on one single PCRAM cell. The feasibility of simultaneously realizing storage and logic computing functions on the designed PCRAM device was therefore demonstrated. Such intriguing merit, combined with its superb storage traits, makes the proposed blade-type PCRAM cell suitable for current in-memory computing and neuromorphic circuits as the key components of future digital computers operated on non-von Neumann mode.

A review on all-optical logic adder: Heading towards next-generation processor

In this paper few literatures on all-optical adders, reported approximately in last fifteen years, have been reviewed. Being the key element of arithmetic and logic unit (ALU), adder has attracted stirring attention of the researchers. The reviewed articles are primarily categorized into three broad sections based on the platforms utilized in designing all-optical adder namely semiconductor optical amplifier (SOA), plasmonics and photonic crystal (PhC). SOA based designs offer high contrast ratio between the output logic levels, however; at the cost of high response time and operating power. Plasmonic based designs provide miniaturized physical footprint of the devices owing to the tight optical confinement. Nevertheless, the process of fabrication involved with the plasmonic based designs along with the loss incurred at the metal are among the limiting features. In contrast, PhC based designs are much more advantageous owing to the notable characteristics of light propagation. The operating power and bandwidth of operation are also higher as compared to the other designs. Photonic crystal-based designs are further categorized into linear and nonlinear domains based on their operating principle. The design structures and performances have been summarized and a comparison is made. Some insights have been discussed leading to design of more efficient PhC based all-optical adders for next generation ultra-first optical processors.

Design and Analysis of Low Power Level Shifter in IC Applications

In this paper, level Shifter circuit is analyzed which is efficient for converting low-voltage digital input signal into high-voltage digital output signal. The circuit has a diagnostic current generation device by using a logic error correction circuit that work by identifying the input and output logic level .When input signal changes, circuit produce low power operation only because it can dissipate power at the operating current. For the comparative analysis of this error correction Level Shifter different methodologies are used which named as biasing for the level Shifter. Result shows that the circuit converts a 0.4-V input signal to 3-V output signal. Simulation results are carried out by using 0.35μm CMOS technology. Power dissipation is 34nW for a 0.4V at 10 kHz input pulse. General Terms Low power design, leakage power, power dissipation, delay.

A Low-Power Subthreshold to Above-Threshold Voltage Level Shifter

This brief presents a power-efficient voltage level-shifter architecture that is capable of converting extremely low levels of input voltages to higher levels. In order to avoid the static power dissipation, the proposed structure uses a current generator that turns on only during the transition times, in which the logic level of the input signal is not corresponding to the output logic level. Moreover, the strength of the pull-up device is decreased when the pull-down device is pulling down the output node in order for the circuit to be functional even for the input voltage lower than the threshold voltage of a MOSFET. The operation of the proposed structure is also analytically investigated. Post-layout simulation results of the proposed structure in a 0.18-μm CMOS technology show that at the input low supply voltage of 0.4 V and the high supply voltage of 1.8 V, the level shifter has a propagation delay of 30 ns, a static power dissipation of 130 pW, and an energy per transition of 327 fJ for a 1-MHz input signal.

Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures

This paper proposes an efficient algorithm to synthesize prefix graph structures that yield adders with the best performance-area trade-off. For designing a parallel prefix adder of a given bit-width, our approach generates prefix graph structures to optimize an objective function such as size of prefix graph subject to constraints like bit-wise output logic level. Given bit-width n and level (L) restriction, our algorithm excels the existing algorithms in minimizing the size of the prefix graph. We also prove its size-optimality when n is a power of two and L= log <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> . Besides prefix graph size optimization and having the best performance-area trade-off, our approach, unlike existing techniques, can 1) handle more complex constraints such as maximum node fanout or wire-length that impact the performance/area of a design and 2) generate several feasible solutions that minimize the objective function. Generating several size-optimal solutions provides the option to choose adder designs that mitigate constraints such as wire congestion or power consumption that are difficult to model as constraints during logic synthesis. Experimental results demonstrate that our approach improves performance by 3% and area by 9% over even a 64-bit full custom designed adder implemented in an industrial high-performance design.

A new universal gate for low power SoC applications

This paper formulates a new design technique for an area and energy efficient Universal NAND gate. The proposed robust three transistors (3T) based NAND gate is just as effective for dynamic power control in CMOS VLSI circuits for System on Chip (SoC) applications. The 3T NAND gate is intuitively momentous and lead to better performance measures in terms of dynamic power, reduced area and high speed while maintaining comparable performance than the other available NAND gate logic structures. Simulation tests were performed by employing standard Berkeley Predictive Technology Model (BPTM) 22 nm, 45 nm and 90 nm process technologies. The experiment and simulation results show that, the proposed 3T NAND gate effectively outperforms the basic CMOS NAND gate with excellent driving capability and signal integrity with exact output logic levels.

A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs

This paper presents a level shifter circuit capable of handling extremely low-voltage inputs. The circuit has a distinctive current generation scheme using a logic error correction circuit that works by detecting the input and output logic levels. The proposed level shifter circuit can convert low-voltage digital input signals into high-voltage digital output signals. The circuit achieves low-power operation because it dissipates operating current only when the input signal changes. Measurement results demonstrated that the circuit can convert a 0.23-V input signal into a 3-V output signal. The power dissipation was 58 nW for a 0.4-V 10-kHz input pulse.

Complementary Symmetry Nanowire Logic Circuits: Experimental Demonstrations and in Silico Optimizations

Complementary symmetry (CS) Boolean logic utilizes both p- and n-type field-effect transistors (FETs) so that an input logic voltage signal will turn one or more p- or n-type FETs on, while turning an equal number of n- or p-type FETs off. The voltage powering the circuit is prevented from having a direct pathway to ground, making the circuit energy efficient. CS circuits are thus attractive for nanowire logic, although they are challenging to implement. CS logic requires a relatively large number of FETs per logic gate, the output logic levels must be fully restored to the input logic voltage level, and the logic gates must exhibit high gain and robust noise margins. We report on CS logic circuits constructed from arrays of 16 nm wide silicon nanowires. Gates up to a complexity of an XOR gate (6 p-FETs and 6 n-FETs) containing multiple nanowires per transistor exhibit signal restoration and can drive other logic gates, implying that large scale logic can be implemented using nanowires. In silico modeling of CS inverters, using experimentally derived look-up tables of individual FET properties, is utilized to provide feedback for optimizing the device fabrication process. Based upon this feedback, CS inverters with a gain approaching 50 and robust noise margins are demonstrated. Single nanowire-based logic gates are also demonstrated, but are found to exhibit significant device-to-device fluctuations.

Cascadable adiabatic logic circuits for low-power applications

There have been several strategies proposed to realise adiabatic circuits. Most of them require a clock signal and also its complement form. In this investigation, the authors we propose a family of adiabatic circuits, which consist of two branches and which enable control of charging and discharging of the capacitive load only by the input signal, work with single time varying supply and with no need of complementary inputs. A mathematical expression has been developed to explain the energy dissipation in our adiabatic inverter circuit. Measurements of energy drawn, recovered and dissipated have been carried out through simulation and, they are the same as obtained from the theoretical expression. In the proposed circuit, the input and output logic levels are approximately the same and can be used for building cascaded logic circuits. The energy saving in this family is to the tune of 50% compared with CMOS circuits constructed with similar circuit parameters, up to 250 MHZ. The authors have described the proposed inverter, NAND gates, NOR gates, adder circuits and JK flip-flop along with their simulation results.

Optoelectronic Flexible-Function Logic Gate Using Monostable-Bistable Transition of Serially Connected Resonant Tunneling Transistors

A novel optoelectronic resonant tunneling logic gate, OE MOBILE, is proposed and its basic logic functions such as NOT, NOR, NAND, OR, and AND are confirmed for optical inputs. The fundamental idea is to use optical inputs to determine the logic level of the gate which consists of two serially connected resonant tunneling transistors (RTTs) with a p+/n-junction gate. The OE MOBILE is operated by oscillating bias voltage to employ monostable-bistable transition. At the time when the transition occurs, the optical inputs are applied by illuminating the RTTs to control their peak currents and consequently to determine the output logic levels. The power of an optical input for logic operations is as small as 5 µW owing to the operation based on monostable-bistable transition. It should be pointed out that the functions of an OE MOBILE can be changed between NOR and NAND by changing the control terminal voltage.

All-optical logic NOR gate using a semiconductorlaser amplifier

The authors report on the realisation of a NOR gate using SLA. The operation is based on the nonlinearity of the SLA gain. The power difference between the output logic level is > 100 µW with a 9 dB contrast.

Modelling and analysis of bridging faults in emitter-coupled logic (ECL) circuits

With the recent achievement of lower power and higher densities, bipolar ECL technology is expected to be used widely in high performance digital circuits. Recent investigations have revealed that bridging faults can be a major failure mode in ICs. The paper presents a detailed analysis of bridging faults in ECL. Certain bridging faults manifest as stuck-at faults. Effects of bridging faults between logical units without feedback and logical units with feedback in ECL are presented. An analytical approach is presented for computation of logic levels at ECL outputs under varying unknown bridging resistances. Effects of bridging faults and bridging resistances on output logic levels in ECL have been examined along with their effects on noise immunity.

Pass-transistor logic design

Logic functions implemented using CMOS transmission gates provide a moderate improvement in area and speed over logic gate implementations. Several techniques for the implementation of pass transistor logic are presented. These techniques use only nMOS transistors in the pass network. The output logic level is restored using additional circuitry. The proposed designs require less silicon area, less power dissipation, and operate at higher speeds compared with the conventional CMOS pass-transistor networks. The speed of operation depends mainly on the circuitry used to restore the output signal of the pass network. The different techniques are compared with respect to the layout area and operating speed.

Optically induced latch-up and other effects in CMOS UVEPROMs

Photographic flash-gun equipment used close to uncovered CMOS UVEPROMs can induce a variety of different failure modes including: (a) destructive latch-up, (b) transients in the output logic levels and in the supply current and (c) a nonde structive ‘output latching’ effect. The mode of failure observed depends on the level of illumination used and on the logic state of the output pins.