Output Data Rate Research Articles

A real time sorting algorithm to time sort any deterministic time disordered data stream

In new generation high intensity high energy physics experiments, millions of free streaming high rate data sources are to be readout. Free streaming data with associated time-stamp can only be controlled by thresholds as there is no trigger information available for the readout. Therefore, these readouts are prone to collect large amount of noise and unwanted data. For this reason, these experiments can have output data rate of several orders of magnitude higher than the useful signal data rate. It is therefore necessary to perform online processing of the data to extract useful information from the full data set. Without trigger information, pre-processing on the free streaming data can only be done with time based correlation among the data set. Multiple data sources have different path delays and bandwidth utilizations and therefore the unsorted merged data requires significant computational efforts for real time manifestation of sorting before analysis. Present work reports a new high speed scalable data stream sorting algorithm with its architectural design, verified through Field programmable Gate Array (FPGA) based hardware simulation. Realistic time based simulated data likely to be collected in an high energy physics experiment have been used to study the performance of the algorithm. The proposed algorithm uses parallel read-write blocks with added memory management and zero suppression features to make it efficient for high rate data-streams. This algorithm is best suited for online data streams with deterministic time disorder/unsorting on FPGA like hardware.

A Novel Segment-Based Data Transfer Scheme for Low-Power CMOS Surveillance Image Sensors

Smart image sensors with low data rate output are well fitted for security and surveillance tasks, since at lower data rates, power consumption is reduced and the image sensor can be operated with limited energy resources such as solar panels. In this paper, a new data transfer scheme is presented to reduce the data rate of the pixels which have undergone value change. Although different pixel difference detecting architectures have been previously reported but it is shown that the given method is more effective in terms of power dissipation and data transfer rate reduction. The proposed architecture is evaluated as a [Formula: see text]-pixel sensor in a standard CMOS technology and comparison with other data transfer approaches is performed in the same process and configuration.

Low‐complexity hopping DFT design based on a compact recursive structure

A novel hopping discrete Fourier transform (DFT) algorithm and its architecture design for efficiently computing time–frequency spectra are presented. Since the sliding process is adopted sample by sample, the spectral bin output data rate is the same as the input data rate. Under the conditions of an M-sample complex input sequence (M = 256), and N-point recursive DFT computation (N = 64) for time hop L (L = 4), the proposed method has the following advantages: (i) the computational complexity of Proposed-I requires only four complex additions and four complex multiplications for each frequency bin, after the first spectral component has been finally calculated; (ii) Proposed-II utilises a re-timing scheme to greatly shorten and balance the critical path; (iii) Proposed-II is less computationally complex than Wang et al.’s method, as the numbers of multiplication and addition operations in the proposed algorithm are 768 and 1024, representing reductions of 50 and 20%, respectively. In addition, the number of coefficients can be reduced by 50% compared with Park et al.’s method. In the FPGA implementation, the proposed design can be operated at 47.26 MHz. It is thus more suitable for use with real-time analytic applications of time–frequency spectra.

Online Data Reduction using Track and Vertex Reconstruction on GPUs for the Mu3e Experiment

The Mu3e experiment searches for the lepton flavour violating decay μ + → e + e − e + , aiming to achieve a sensitivity of 2 · 10 −15 in its first phase and ultimately aspiring to a final sensitivity of 10 −16 . During the first phase of the experiment, a muon rate of ∼ 10 8 μ /s will be available, resulting in a data rate of ∼ 80 Gbit/s. The trigger-less readout system is based on optical links and switching FPGAs sending the complete detector data for a time slice to one node of the filter farm. A full online reconstruction is necessary to reduce the data rate to a manageable amount to be written to disk. Graphics processing units (GPUs) are used to fit tracks with a non-iterative 3D tracking algorithm for multiple scattering dominated resolution. In addition, a three track vertex selection is performed by calculating the vertex position from the intersections of the tracks. Together with kinematic cuts, this allows for a reduction of the output data rate to below 100MB/s using 12 DAQ PCs.

Electronics design and system integration of the ATLAS New Small Wheels

The upgrades of the Large Hadron Collider (LHC) at CERN and the experiments in 2019/20 and 2024/26 will allow to increase the instantaneous luminosity to L=2× 1034 cm−2s−1 and L=5−7× 1034 cm−2s−1, respectively. For the High Luminosity (HL) HL-LHC phase, the expected mean number of interactions per bunch crossing will be 55 at L=2× 1034 cm−2s−1 and 140 at L=5× 1034 cm−2s−1. This increase drastically impacts the ATLAS trigger system and trigger rates. For the ATLAS Muon Spectrometer, a replacement of the innermost endcap stations, the so-called ``Small Wheels", which are operating in a magnetic field, is therefore planned for 2019/20 to be able to maintain a low pT threshold for single muons and excellent tracking capability in the HL-LHC regime. The New Small Wheels will feature two new detector technologies: resistive Micromegas and small strip Thin Gap Chambers comprising a system of 2.4 million readout channels. Both detector technologies will provide trigger and tracking primitives fully compliant with the post-2026 HL-LHC operation. To allow for some safety margin, the design studies assume a maximum instantaneous luminosity of L=7× 1034 cm−2s−1, 200 pile-up events, trigger rates of 1 MHz at Level-0 and 400 KHz at Level-1. A radiation dose of 1700 Gy (innermost radius) is expected. The on-detector electronics will be implemented on some 8000 boards; four different custom ASICs will be used. The large number of readout channels, high speed output data rate, harsh radiation and magnetic environment, small available space, poor access and low power consumption all impose great challenges for the system design. The overall design and first results from integration of the electronics in a vertical slice test will be presented.

Performance Evaluation of LTE based System Parameters using OFDM in Indoor and Outdoor Environment

Background/Objectives: OFDM is a wireless broad band technology employed in 4G wireless system. OFDM is the Frequency Division Multiplexing (FDM) modulation technique used for sending a group of signals simultaneously over a channel. OFDM divides the signal into a number of narrow signals which are sent at various frequencies to the receiver. Method/Analysis: Long Term Evolution is a 4G technology used for both indoor and outdoor environments. LTE is able to produce higher data output rates and reduce the cost of delivering a megabyte of data. The outside sources of interference, design and configuration of the LTE network may reduce the spectrum efficiency and results in low data output rates for users and high costs for network operators. LTE will be deployed to provide multimedia services for mobile and portable scenarios. Findings/Applications: This paper concentrates on correlating SNR to the performance of LTE in indoor and outdoor environments. An average throughput and a consistent performance are observed more frequently in outdoor areas when compared to indoor areas. A comparison of indoor and outdoor parameters is shown by simulating in MATLAB.

A scalable decimation filter ASIC for high resolution digital magnetometer with sigma-delta modulator feedback loop

High-resolution digital magnetometers often use sigma-delta modulator feedback loops for large dynamic range, good linearity and low power consumption. A decimation filter is usually needed to obtain the high-resolution output data and reduce the output data rate at the same time. A scalable decimation filter application specific integrated circuit (ASIC) for high-resolution digital magnetometer with sigma-delta modulator feedback loop has been designed, implemented and fabricated. Keeping the decimation ratio of 128 to 1 fixed, the ASIC chip was carefully designed to be scaled with input data rate accordingly, thus maintaining the same resolution of 24 bits for the digital magnetometer. The ASIC chip consists of a cascaded integrator-comb (CIC) filter decimated by 16, a droop compensation programmable FIR1 filter decimated by 4, a brick-wall programmable FIR2 filter decimated by 2 and a 5th order sigma-delta bit stream generator for built-in-self-testing (BIST). The chip was designed and fabricated based on the GlobalFoundries 0.18µm CMOS process. Its total die size is about 3×3mm2, having 256,000 equivalent logic gates. In a typical working scenario with an input data rate of 128kHz, the measured power consumption of the core powered with 1.8V is about 0.9mW.

An Analog Front-End for a Multifunction Sensor Employing a Weak-Inversion Biasing Technique With 26 nVrms, 25 aCrms, and 19 fArms Input-Referred Noise

An analog front-end (AFE) for a multifunction environmental sensor is proposed. The AFE is designed to be able to sense $1~\mu \text {V}$ , 1 fC, and 1 pA level signals in a low-frequency band around DC, and consists of an instrumentation amplifier (IA), a charge amplifier (CA), and a continuous time delta-sigma (CT- $\Delta \Sigma $ ) ADC. To reduce the low-frequency noise of operational amplifier (OPAMP) which is used for signal path, this paper proposes a weak-inversion biasing technique. The designed IA achieved 26 nVrms input-referred noise (IRN) in the band of 0.1–10 Hz with 0.22 mm2 die area. The designed CA achieved 25 aCrms IRN in charge sensing mode and 19 fArms IRN in current sensing mode in the band of 0.01–1 Hz, respectively, and occupies 0.12 mm2 die area. The AFE has been fabricated in a $0.18~\mu \text {m}$ CMOS process with 4.5 mm2 die area. The current consumption at 2.56 kHz output data rate (ODR) is 2.5 mA, reducing to $2~\mu \text {A}$ at 0.01 Hz ODR.

Dynamic Quantizer Design Under Communication Rate Constraints

Feedback type dynamic quantizers such as delta-sigma modulators are typically effective for encoding high-resolution data into lower resolution data. The dynamic quantizers include a filter and a static quantizer. When it is required to control under a communication rate constraint, the data rate of the quantizer output should be minimized appropriately by quantization. This technical note provides numerical methods for the complete design of a type of dynamic quantizers, including the selection of all the quantizer parameters in order to minimize a specific performance index and satisfy a communication constraint. The design method of the dynamic quantizer is proposed using a particle swarm optimization (PSO) method. A part of the initial quantizers in PSO are designed based on an invariant set analysis and an iteration algorithm. Effectiveness of the system with the proposed quantizer is assessed through numerical examples.

A 72 × 60 Angle-Sensitive SPAD Imaging Array for Lens-less FLIM.

We present a 72 × 60, angle-sensitive single photon avalanche diode (A-SPAD) array for lens-less 3D fluorescence lifetime imaging. An A-SPAD pixel consists of (1) a SPAD to provide precise photon arrival time where a time-resolved operation is utilized to avoid stimulus-induced saturation, and (2) integrated diffraction gratings on top of the SPAD to extract incident angles of the incoming light. The combination enables mapping of fluorescent sources with different lifetimes in 3D space down to micrometer scale. Futhermore, the chip presented herein integrates pixel-level counters to reduce output data-rate and to enable a precise timing control. The array is implemented in standard 180 nm complementary metal-oxide-semiconductor (CMOS) technology and characterized without any post-processing.

Quantum Random Number Generation Using a Quanta Image Sensor.

A new quantum random number generation method is proposed. The method is based on the randomness of the photon emission process and the single photon counting capability of the Quanta Image Sensor (QIS). It has the potential to generate high-quality random numbers with remarkable data output rate. In this paper, the principle of photon statistics and theory of entropy are discussed. Sample data were collected with QIS jot device, and its randomness quality was analyzed. The randomness assessment method and results are discussed.

Achieved Data Rate of Cooperative MIMO in Measured Channels

This paper evaluates the achieved data rate of a cooperative Multiple Input Multiple Output (MIMO) system in real measured channels. The achieved data is computed according to an iterative algorithm, which determines the linear transmit and receive beamforming filters that maximize the sum-rate. This method allows us to design the transmit filter with a simple algorithm. The Channel State Information (CSI) of all channels is assumed to be known at the transmitters, and cooperation between (BSs) in sharing the CSI is considered. MIMO channels in different scenarios were measured in a typical propagation environment using two BSs and four handsets, similar to smartphones, held by different users. Users were located at different distances from each other, and at different orientations with respect to each other. We computed the received data rate for four different groups of handsets at a fixed SNR of 15 dB. Using the algorithm, we investigated how the experimental and theoretical capacity is influenced by cross-correlation between the individual user linkages arising from one antenna at the BS, and by imbalance in the power of the different linkages. The system performs best when the handsets are separated by at least 1 m. Furthermore, both in theory and in practice, the algorithm is more sensitive to power imbalance rather than cross-correlation.

Dual-Comb Architecture for Fast Spectroscopic Measurements and Spectral Characterization

Optical frequency combs (OFCs) generated through the modulation of continuous-wave lasers offer higher power per component, simple comb spacing control, and lower complexity and cost than traditional OFCs. By these reasons, they are an interesting optical source for spectrometers. In this letter, a dual-comb architecture based on two OFCs generated from the same laser using optical phase modulators is presented. The system features a new placement for the spectroscopic sample that increases the versatility, robustness, and stability of the instrument without requiring any reconfiguration for carrying out different types of measurement. Besides this, a self-referenced detection setup based on digital phase sensitive multitone detection improves the SNR of the previous approaches offering more flexibility in its configuration and high data output rate. The proposed architecture is validated by measuring a ro-vibrational absorption feature of HCN at 1544.51 nm and characterizing the spectral response of a fiber-coupled Fabry–Perot filter.

Digital Signal Processing Using Stream High Performance Computing

A “large-N” correlator that makes use of Field Programmable Gate Arrays and Graphics Processing Units has been deployed as the digital signal processing system for the Long Wavelength Array station at Owens Valley Radio Observatory (LWA-OV), to enable the Large Aperture Experiment to Detect the Dark Ages (LEDA). The system samples a [Formula: see text][Formula: see text]MHz baseband and processes signals from 512 antennas (256 dual polarization) over a [Formula: see text][Formula: see text]MHz instantaneous sub-band, achieving 16.8[Formula: see text]Tops[Formula: see text]s[Formula: see text] and 0.236 Tbit[Formula: see text]s[Formula: see text] throughput in a 9[Formula: see text]kW envelope and single rack footprint. The output data rate is 260 MB[Formula: see text]s[Formula: see text] for 9-s time averaging of cross-power and 1[Formula: see text]s averaging of total power data. At deployment, the LWA-OV correlator was the largest in production in terms of N and is the third largest in terms of complex multiply accumulations, after the Very Large Array and Atacama Large Millimeter Array. The correlator’s comparatively fast development time and low cost establish a practical foundation for the scalability of a modular, heterogeneous, computing architecture.

The ONSEN Data Reduction System for the Belle II Pixel Detector

We present an FPGA-based online data reduction system for the pixel detector of the future Belle II experiment. The occupancy of the pixel detector is estimated at 3 %. This corresponds to a data output rate of more than 20 GB/s after zero suppression, dominated by background. The Online Selection Nodes (ONSEN) system aims to reduce the background data by a factor of 30. It consists of 33 MicroTCA cards, each equipped with a Xilinx Virtex-5 FPGA and 4 GiB DDR2 RAM. These cards are hosted by 9 AdvancedTCA carrier boards. The ONSEN system buffers the entire output data from the pixel detector for up to 5 seconds. During this time, the Belle II high-level trigger PC farm performs an online event reconstruction, using data from the other Belle II subdetectors. It extrapolates reconstructed tracks to the layers of the pixel detector and defines regions of interest around the intercepts. Based on this information, the ONSEN system discards all pixels not inside a region of interest before sending the remaining hits to the event builder system. During a beam test with one layer of the pixel detector and four layers of the surrounding silicon strip detector, including a scaled-down version of the high-level trigger and data acquisition system, the pixel data reduction using regions of interest was exercised. We investigated the data produced in more than 20 million events and verified that the ONSEN system behaved correctly, forwarding all pixels inside regions of interest and discarding the rest.

A 160 GHz Pulsed Radar Transceiver in 65 nm CMOS

This paper presents a 160 GHz center frequency pulsed 65 nm CMOS transceiver for short range radar applications. Four phased array transceivers were implemented in a single chip with antennas implemented in a BGA package. The implemented transmitter is capable of producing pulses of 100 ps widths ( >20 GHz RF bandwidth) at a 160 GHz carrier frequency. The measured effective isotropic radiated power (EIRP) is 18.8 dBm for continuous wave outputs. The analog beam forming receiver achieves an overall gain of 42.5 dB, -14 dBm IP1dB, 7 GHz bandwidth, and a noise figure of 22.5 dB. The sliding window time-dilation baseband relaxes the output data rate and subsequent digital processing requirements. Fine grained duty cycling reduces power dissipation. The entire chip consumes 2.2 W from 1.2/1.4 V supplies in a 65 nm digital CMOS process.

A 100-Channel 1-mW Implantable Neural Recording IC

This paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channel by more than 50% compared to the conventional multiplexing neural recording system. A neural amplifier (NA) with current-reuse technique and weak inversion operation is demonstrated, consuming 800 nA under 1-V supply while achieving an input-referred noise of 4.0 μVrms in a 8-kHz bandwidth and a NEF of 1.9 for the whole analog recording chain. The measured frequency response of the analog front-end has a high-pass cutoff frequency from sub-1 Hz to 248 Hz and a low-pass cutoff frequency from 432 Hz to 5.1 kHz, which can be configured to record neural spikes and local field potentials simultaneously or separately. The whole system was fabricated in a 0.18-μm standard CMOS process and operates under 1 V for analog blocks and ADC, and 1.8 V for digital modules. The number of active recording channels is programmable and the digital output data rate changes accordingly, leading to high system power efficiency. The overall 100-channel interface IC consumes 1.16-mW total power, making it the optimum solution for multi-channel neural recording systems.

A 75-µW, 16-Channel Neural Spike-Sorting Processor With Unsupervised Clustering

Energy-efficient spike-sorting DSPs are necessary to allow for the real-time processing of multi-channel, wireless, implantable neural recordings. Online, unsupervised clustering forms an integral part of on-chip spike sorting. However, previous spike-sorting DSPs did not include unsupervised clustering due to the large memory required for its implementation. We demonstrate the first multi-channel spike-sorting DSP chip that includes online, unsupervised clustering. On-chip clustering has been made possible by using a two-stage implementation of an online clustering algorithm, a noise-tolerant distance metric, and selectively clocked high-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> register banks. The 16-channel spike-sorting chip, implemented in a 65-nm CMOS process, has a power dissipation of 75 μW at a supply voltage of 270 mV. The implementation of on-chip clustering provides a 240× reduction in the output data rate, which is 3× higher than the data-rate reduction obtained from previous spike-sorting DSP chips.

An AIPS-based, distributed processing method for large radio interferometric datasets

The data output rates of modern radio interferometric telescopes make the traditional data reduction process impractical in many cases. We report on the implementation of a lightweight infrastructure, named AIPSLite, that enables the deployment of AIPS interferometric processing routines on distributed systems in an autonomous and fault tolerant manner. We discuss how this approach was used to search for sources of 6.7 GHz methanol maser emission in the Cep A region with the European VLBI Network (EVN). The field was searched out to a radius of 1.25 min^(−1) at milli-arcsecond spatial resolution and 1024 frequency channels with 0.088 km s^(−1) velocity resolution. The imaged data was on the order of 30 TB. Processing was performed on 128 processors of the Irish Centre for High End Computing (ICHEC) linux cluster with a run time of 42 h, and a total of 212 CPU days.

A 128$\,\times$128 1.5% Contrast Sensitivity 0.9% FPN 3 µs Latency 4 mW Asynchronous Frame-Free Dynamic Vision Sensor Using Transimpedance Preamplifiers

Dynamic Vision Sensors (DVS) have recently appeared as a new paradigm for vision sensing and processing. They feature unique characteristics such as contrast coding under wide illumination variation, micro-second latency response to fast stimuli, and low output data rates (which greatly improves the efficiency of post-processing stages). They can track extremely fast objects (e.g., time resolution is better than 100 kFrames/s video) without special lighting conditions. Their availability has triggered a new range of vision applications in the fields of surveillance, motion analyses, robotics, and microscopic dynamic observations. One key DVS feature is contrast sensitivity, which has so far been reported to be in the 10-15% range. In this paper, a novel pixel photo sensing and transimpedance pre-amplification stage makes it possible to improve by one order of magnitude contrast sensitivity (down to 1.5%) and power (down to 4 mW), reduce the best reported FPN (Fixed Pattern Noise) by a factor of 2 (down to 0.9%), while maintaining the shortest reported latency (3 μs) and good Dynamic Range (120 dB), and further reducing overall area (down to 30 × 31 μm per pixel). The only penalty is the limitation of intrascene Dynamic Range to 3 decades. A 128 × 128 DVS test prototype has been fabricated in standard 0.35 μm CMOS and extensive experimental characterization results are provided.