Output Compression Point Research Articles

A Ka-Band CMOS Power Amplifier With OP1dB Improvement Employing a Diode-Connected Analog Linearizer

This paper presents a 30-36 GHz CMOS power amplifier (PA) with a diode-connected analog linearizer dedicated to improving the output power and power-added efficiency (PAE) at 1-dB output compression point (OP1dB). The proposed analog linearizer performs a gain expansion, simultaneously introducing little phase distortion. In addition, a design procedure of the matching network between the analog linearizer and PA is analyzed to mitigate the impact of impedance variation caused by the control voltage and input power. As a proof of concept, the circuit is fabricated in a 65-nm CMOS process with a 0.31 mm2 total area. Measured output power and PAE at OP1dB are > 13.4 dBm and > 12.4%, where maximum improvement of 2.2 dB and 5.9% is achieved at 31 GHz when the analog linearizer is active. The saturated output power of > 16.2 dBm is obtained with the saturated PAE of > 21%. Applying a single carrier 256-QAM signal with a bandwidth of 400 MHz and a peak-to-average power ratio (PAPR) of 10.4 dB, the PA with the proposed analog linearizer can achieve the adjacent channel power ratio (ACPR) of -34 dBc at the output power of 6 dBm.

(Digital Presentation) Sub-THz Front Ends for Future Communication and Sensing Technologies in 130nm Sige Bicmos Technology

Introduction: Beyond the-5G technologies are targeting the available bandwidth (BW) in the D-band and J-band. This promises for very high speed communication and sensing accuracy. Although the advantages of operating beyond 100 GHz from the application point of view, it requires a lot of research and development to design a reliable and power efficient chipsets. In this presentation we will go through the design of wideband 240 GHz transmitter (Tx) and receiver (Rx). Firstly an overview about the link budget analysis will be given, then the design of the local carrier signal generator will be discussed. The wideband Txs and Rxs are to be presented with frequency channelizing concept. At the end the results of the wireless links will be demonstrated. Link Budget Analysis: Operating at sub-THz frequencies approaching the transistor fT put a lot of constraints on the system link budget. The elevated noise figure together with the limited maximum Pout of the transistors lead to solutions which might be limited in BW or power efficiency. Hence the design architecture need to be optimized taking into account the elevated power consumption and heat dissipation. Carrier Generation: Several approaches could be followed to generate the sub-THz carrier frequency. For a power efficient solution the fundamental oscillators promise for a power efficient solution but with limited phase noise performance and tuning range. Such a solution is more common for imaging systems operating at a single frequency. In order to achieve wider tuning ranges for multi-channel scenario or FMCW radar systems, the frequency multiplication chains are common, whereas the multiplication factor depends on the system parameters. Sub-THz Rx: Different approaches were followed to realize a wideband sub-THz Rx. For some technologies the transistors ft does not promise the realization of low noise amplifiers (LNA) with reasonable noise figure, gain and BW. Hence the mixer first approach were followed trying to optimize the noise figure of the down conversion mixer as much as possible. This also enhances the input compression point (IP1dB) of the Rx which is better for monostatic radar applications. On the other hand, if the technology in use allows the development of well performing LNA’s, the LNA first approach was followed to enhance the all over NF of the receiver and ease the implementation of IQ Rxs. In our work an LNA was implemented followed by IQ downconversion mixers and baseband chain as presented in [3]. Sub-THz Tx: The Tx main challenging performance parameter in the sub-THz frequency range is to achieve high output compression point across the required BW with as high efficiency as possible. Increasing the power handling capabilities of the power amplifiers (PA) by increasing the transistors sizes of the output stages, leads to low output impedance and hence higher impedance transformation ratios for the matching structures and eventually narrow band designs. Hence the power combining architectures were proposed as an alternative to increase the output power either by combining on-chip or combining in air. In this work a fully integrated IQ Tx is to be presented with on-chip LO chain and 4-way power combined power amplifier. Baseband Signal Generation and Processing The baseband topology depend on the application. For mobile communication or localization use cases a wideband channels are not available directly from the digital processors, a kind of channel bonding is required either in the digital domain or in the analog domain. As a proof of concept we present here 3-IQ frequency interleaving combiner. Wireless Link Demonstrator Two demonstrators are to be presented. The first demonstrator is transmitting a broadband IQ signal generated from an arbitrary wave generator wirelessly utilizing an IQ 240GHz Tx and Rx. Data rates up to 100 Gbps were demonstrated across a 1m of wireless link. The second demonstrator includes the implementation of 3-channel IQ channelizer to create the complex modulated signal at several intermediate frequencies (IFs) and then upconverted to the 240GHz carrier signal. On the Rx side the de-channelizer convert the down modulated signal to three IQ channels. Data rates up to 8Gbps were demonstrated wirelessly with the channelization with potential of further enhancements for more channels integration. Outlook The future of the sub-THz wireless links for high speed communication and localizations goes towards implementing phased array and MIMO systems. This requires the research community to develop novel architectures to develop large scale arrays with acceptable power consumptions and suitable packaging solution. On the baseband side also the channel bonding solutions are still in an early stage, requiring more work to bond modularly larger number of channels.

A Dual-Mode W-Band Eight-Way Parallel–Series Power-Combining PA With +18-dBm P sat and 15.1% PAE in 65-nm CMOS Technology

This letter presents the design of a Dual-mode W-band eight-way power-combining power amplifier (PA) implemented in Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS technology ( $f_{t}$ / $f_{{max}}$ : 210 GHz/240 GHz). A configurable parallel-series-based eight-way power combine technique is proposed to achieve high output power with high power efficiency near half of $f_{t}$ . The eight-way power-combiner is consisted of two transformer-based parallel two-way differential combiners and a coupled-line-based series combiner to achieve high passive efficiency and compact layout. The proposed PA achieves a measured peak gain of 30.9 dB with a bandwidth (BW) of 7.5 GHz. The PA has $P_{{sat}}$ of +18 dBm with an 1dB output compression point (OP1dB) of +13.8 dBm and a peak PAE of 15.1% in high-power mode. In the low-power mode (LPM), the measured $P_{{sat}}$ , OP1dB, and peak PAE are +13.6, +9.1 dBm, and 10.3%, respectively. The PAE is enhanced by 3.4% points at a 6-dB back-off in LPM. The core area of the proposed PA is 0.3 mm².

A 28-GHz SOI-CMOS Doherty Power Amplifier With a Compact Transformer-Based Output Combiner

This article presents a series voltage-combining Doherty power amplifier (PA) achieving high output power ( P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> ) and high power-back-off (PBO) efficiency for 28-GHz fifth-generation (5G) applications. We introduce a new transformer-based series output combiner design method to achieve a true-Doherty load modulation that uses a compact footprint. The output stages of the main PA and the auxiliary PA (aux. PA) both use a differential three-stacked FET topology for high output power without posing a reliability issue. The intermediate-node matching is achieved by using a shunt inductor for voltage waveform alignment and efficiency improvement. A modified differential quadrature hybrid is proposed to achieve the desired quadrature power splitting function without the need for an input balun. For the proof of concept, the proposed PA is implemented in a 22-nm CMOS fully depleted silicon-on-insulator (FD-SOI) technology with a core area of 0.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . At 28 GHz, the measured saturated output power ( P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ), 1-dB output compression point (OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> ), and peak power-added efficiency (PAE) are 22.5 dBm, 21.1 dBm, and 28.5%, respectively. State-of-the-art International Technology Roadmap for Semiconductors (ITRS) figure-of-merit (FOM) and power density are achieved. The measured PAE at 6-dB PBO is 22.1%, which results in an efficiency enhancement ratio of 1.56/3.12 with respect to an ideal class-B and class-A PA. The proposed PA can support 2.4-Gb/s 64-quadratic amplitude modulation (64-QAM) and 0.8-Gb/s 256-QAM signal with a competitive average PAE. Excellent device reliability is validated by operating the implemented PA under 3-dB gain compression point for 12 h with less than 0.06-dB P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> variation. The proposed Doherty PA with a compact footprint is suitable for the integration purpose of future 5G multiple-input multiple-output (MIMO) and phased-array applications.

LO Chain (×12) Integrated 190-GHz Low-Power SiGe Receiver With 49-dB Conversion Gain and 171-mW DC Power Consumption

A 190-GHz mixer-based down-conversion receiver realized in a 130-nm SiGe BiCMOS technology featuring high-speed heterojunction bipolar transistors (HBTs) with ( $f_{\text {T}}$ , $f_{\text {max}}$ ) = (300, 500) GHz is presented. The core part of the receiver consists of a low-noise amplifier (LNA), an active tunable fundamental mixer, an intermediate frequency (IF) buffer amplifier (BA), and an active inverse balun. A wideband, high conversion gain (CG) local oscillator (LO) chain is integrated to make the receiver suitable for applications requiring tunable LO, which contains a multiplier with a multiplication factor of 12 ( $\times 12$ ) and a driver amplifier. To exploit the best possible performance with ultralow dc power consumption ( $P_{\text {dc}}$ ), the mixer and LNA transistors operate at forward-biased base–collector junction voltage ( $V_{\text {BC}}$ ). With a fixed IF frequency at 1 GHz, this receiver exhibits a peak CG of 49 dB with a 14-dB tuning range and a minimum single-sideband noise figure (NF) of 16.5 dB, consuming only 29-mW static dc power for the core part and 171 mW overall, including the LO chain. Within the CG tuning range, this receiver achieves a 6-dB RF bandwidth (BW) from 25 to 32 GHz. Compared with previously reported receivers at similar frequencies, the highest CG and the lowest $P_{\text {dc}}$ with highly competitive performance in terms of BW, CG tuning range, 1-dB output compression point, and NF have been achieved.

12 dBm OCP1dB Millimeter-wave 28 nm CMOS Power Amplifier using Integrated Transformers

This paper describes the design of mm-wave integrated transformers and their application within a power amplifier (PA) in a 28 nm CMOS technology. The PA presents a 2-stage common-source differential topology and uses one transformer at the input and another at the output to perform single-ended to differential conversion, as well as another transformer to perform interstage matching. The baluns are sized to provide low insertion losses and high common-mode rejection rate (CMRR) as well as integrating the input and output matching networks. The designed baluns achieve minimum insertion losses better than 0.8 dB and CMRR superior to 27 dB. The output-stage transistors have a measured 1 dB output compression point (OCP1dB) of 10.2 dBm, 10.1 dB gain and peak power added efficiency (PAE) as high as 35%. Thanks to the transformers, the PA presents a compact implementation, occupying only 0.037 mm² on silicon. The fabricated PA achieves 12 dBm OCP1dB, 15.3 dB gain and peak PAE better than 20%.

Concurrent Tri-band CMOS Power Amplifier Linearized by 3D Improved Memory Polynomial Digital Predistorter

This paper presents the design and post-layout results of a 5G power amplifier (PA) in 130 nm CMOS technology. The circuit incorporates a pre-amplification stage that uses a current reuse technique followed by a power stage. The PA operates in the 2–5 GHz range, with a power gain of 16–20.9 dB, output saturation power of 19.1–21.7 dBm, an output compression point of 15.8–20.4 dBm and maximum power-added efficiency of 9.28–22.4%. A three-dimensional improved memory polynomial (3DIMP) and a three-dimensional harmonic improved memory polynomial (3DHIMP) are introduced to the behavioral modeling and digital baseband predistortion of the designed PA for the cases without and with multiplicity among carriers, respectively. Moreover, an ascendant factor algorithm is presented for selecting the truncation factors. Simulation results adopting IEEE 802.11n at channel 1, LTE at channel 2 and IEEE 802.11ac at channel 3 show that the proposed 3DIMP and 3DHIMP, in comparison with previous three-dimensional multi-band (3DMB) and three-dimensional harmonic memory polynomial (3DHMP) having the same amount of parameters, can improve the normalized mean square error by up to 8.3 dB and 16.6 dB, respectively, when applied to the PA inverse behavioral modeling. Additional reductions in error vector magnitude up to 0.39 p.p. and 1.23 p.p. are also achieved when the 3DIMP and 3DHIMP are responsible for the PA linearization instead of previous 3DMB and 3DHMP, respectively.

S-band hybrid amplifiers based on hydrogenated diamond FETs

The first realizations of S-band hybrid amplifiers based on hydrogenated-diamond (H-diamond) FETs are reported. As test vehicles of the adopted H-diamond technology at microwave frequencies, two designs are proposed: one, oriented to low-noise amplification, the other, oriented to high-power operation. The two amplifying stages are so devised as to be cascaded into a two-stage amplifier. The activities performed, from the technological steps to characterization, modelling, design and realization are illustrated. Measured performance demonstrates, for the low-noise stage, a noise figure between 7 and 8 dB in the 2–2.5 GHz bandwidth, associated with a transducer gain between 5 and 8 dB. The OIP3 at 2 GHz is 21 dBm. As to the power-oriented stage, its transducer gain is 5–6 dB in the 2–2.5 GHz bandwidth. The 1-dB output compression point at 2 GHz is 20 dBm whereas the OIP3 is 33 dBm. Cascading the measured S-parameters of the two stages yields a transducer gain of 15 ± 1.2 dB in the 2–3 GHz bandwidth.

Performance Analysis of a Low-Noise, Highly Linear Distributed Amplifier in 500-nm InP/InGaAs DHBT Technology

This article is an extension of the previous report on an ultrawideband distributed amplifier (DA) in the InP double heterojunction bipolar transistor (DHBT) technology. With the choice of a tricode unit cell, the Miller capacitance is reduced and a larger bandwidth (BW) is obtained. Measured S-parameters show a 3-dB BW of near dc to >170 GHz with a gain of 12 dB. In addition, the circuit operates in low dc bias conditions, thus yielding a low measured noise figure (NF) of 8 dB over the frequency range of 5–50 GHz and 12 dB at 135 GHz. Within the 5–50-GHz frequency range, the NF is only 0.5 dB higher than the NF of a similar DA with cascode unit cell. When the circuit is measured for large-signal condition, it reaches a 1-dB output compression point, $P_{\mathrm {1\,dB}}$ , of 8.4 dBm at 150 GHz, a saturated output power of approximately 10 dBm, and an associated maximum power-added efficiency (PAE) of 6%. This is the best linearity as well as the highest saturated output power and PAE reported at this frequency for DAs. When measured at 20 GHz, the circuit shows a $P_{\mathrm {1\,dB}}$ , of 9 dBm and output referred third-order intercept point of 22 dBm, a saturated output power of 11 dBm, and an associated maximum PAE of 6%, thereby proving its uniform large-signal character within the full band. In short, this circuit brings in the unique combination of low NF, highly linear characteristics, and high PAE simultaneously together over large BW. Furthermore, the circuit consumes 180 mW of dc power only.

Design of a High Range, High Efficiency Spread Spectrum Transmitter for Audio Communication Applications

This work proposes a direct sequence spread spectrum transmitter with high transmission range and efficiency for audio signals. It is shown that by choosing high process gain for spread spectrum signal the data could reach a range of 55km in the 2.4GHz ISM band. By employing a light modulation scheme, we have a relaxed SNR requirement for having a low bit error rate (BER) which translates to relaxed error vector magnitude (EVM) condition. Therefore a switching power amplfier (PA) is used in this work which improves the transmitter’s efficiency while by taking PAs nonidealities into account we extracted the new equations to find the conditions to improve the efficiency compared to conventional zero current and zero current switching conditions. The PA efficiency is equal to 79.5% while having 30dBm output power. The mixer alongside power amplifier used in this work provide a conversion gain of 9 dB while having 16 dBm output compression point. The employed tunable quadrature oscillator has the ability to cancel phase and amplitude errors without comprimising the oscillator phase noise. The transmitter reaches an efficiency of 73.4% and an EVM of -32.75 dB.

Efficient Design and Optimization Method for Distributed Amplifiers

A novel design and optimization method for distributed amplifiers (DAs) is proposed to make the circuit design more convenient and efficient. This method combines artificial intelligence (AI) optimization with manual design by two loops, i.e., outer manual loop and inner AI loop. The layout design is followed by AI optimization to take more influencing factors such as parasitic effect into account for the practicability. A DA with three gain cells is designed and optimized in a standard 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology to verify the proposed method. With a chip area of only 0.55 mm2, the DA provides 9.8 dB average forward gain from 1 to 15.2 GHz. The output power at 1 dB output compression point is more than 7.7 dBm in the 2–14 GHz frequency band and the peak power-added efficiency (PAE) is 10.6%. The measurement results validate the proposed method as a robust DA design procedure for improving circuit performance and design efficiency.

An Intermediate Frequency Amplifier for High-Temperature Applications

This paper presents a two-stage small signal intermediate frequency amplifier for high-temperature communication systems. The proposed amplifier is implemented using in-house silicon carbide bipolar technology. Measurements show that the proposed amplifier can operate from room temperature up to 251 °C. At a center frequency of 54.6 MHz, the amplifier has a gain of 22 dB at room temperature, which decreases gradually to 16 dB at 251 °C. Throughout the measured temperature range, it achieves an input and output return loss of less than −7 and −11 dB, respectively. The amplifier has a 1-dB output compression point of about 1.4 dBm, which remains fairly constant with temperature. Each amplifier stage is biased with a collector current of 10 mA and a base–collector voltage of 3 V. Under the aforementioned biasing, the maximum power dissipation of the amplifier is 221 mW.

A 2–22 GHz CMOS Distributed Power Amplifier With Combined Artificial Transmission Lines

This letter presents a novel compact distributed power amplifier (DPA) implemented in a 0.18-μm CMOS technology. Two three-stage DAs are combined with their input artificial transmission lines (ATLs) shared to work as a preamplifier for broadband impedance matching and gain improvement, while two four-stage DAs are combined with their output ATLs shared to work as a medium-power amplifier for high output power in a wide frequency band. Measurement results show that the DPA provides 11.9-dB average associated gain from 1 to 23.8 GHz. The output power at 1-dB output compression point (OP 1 dB ) is more than 8.9 dBm over the frequency of 2-22 GHz, and the peak power-added efficiency is 10% with the OP 1 dB of 14.5 dBm.

Linear Large-Swing Push–Pull SiGe BiCMOS Drivers for Silicon Photonics Modulators

The analysis, design, and experimental characterization of a novel class of large-swing low output-impedance push-pull SiGe BiCMOS drivers are discussed. The circuits, which employ single- and series-stacked emitter follower (EF) and MOS-HBT cascode topologies, are intended to drive optical modulators with high-order m-pulse-amplitude modulated (PAM) signals, while maximizing energy/bit efficiency. The series-stacked EF version, implemented in a 55-nm SiGe BiCMOS technology with 370 GHz ${f_{\mathrm {MAX}}}$ , achieved the highest linearity with 4.8-Vpp differential output swing, 57.5 GHz bandwidth, and an output compression point of 12 dBm per side. Four-PAM and eight-PAM eye diagrams were measured at 56 GBd for a record data rate of 168 Gb/s. Four-PAM 64-GBd eye diagrams were also demonstrated. The circuit consumes 820/600 mW with/without the predriver and has an energy efficiency of 4.88/3.57 pJ/b.

A 2–22 GHz CMOS wideband distributed power amplifier

AbstractThis article presents a novel wideband distributed power amplifier (DPA) implemented in a 0.18 μm CMOS technology. The DPA consists of a preamplifier and a medium‐power power amplifier (PA), and both of them are respectively composed of two distributed amplifiers (DAs), which have separate input artificial transmission lines (ATLs) but with their output ATLs shared to achieve wide frequency band. In the medium‐power PA, the large‐signal multigated transistor technology is applied to further improve the linear output power. Measurement results show that the DPA achieves 10.2 dB average associated gain from 2.5 to 22 GHz. The output power at 1‐dB output compression point (OP1dB) is more than 8 dBm over the frequency of 2–22 GHz, and the peak OP1dB is 12.6 dBm with the power‐added efficiency of 7.2% at 6 GHz.

Two‐dimensional distributed amplifier for extreme extension of GBW, PAE and OP 1dB

In this study, a new technique is introduced for full power combining in distributed amplifiers which contain multiplicative gain stages. Produced powers from middle stages of multiplicative structures are always wasted in terminating resistors. This study shows that an electrical funnel can be used to combine all produced powers from all stages. To do so, two configurations are considered to terminate middle stages with transistors. It is shown how a typical distributed amplifier can be converted to a two-dimensional distributed amplifier (2D-DA). Analytical expressions for gain calculation are also presented. All inductors and connections of 2D-DA are simulated by advanced design system (ADS) electromagnetic simulator with TSMC 0.18 CMOS layout specifications. Post-layout simulation results show the trueness of the presented relations. The designed 2D-DA shows 17.4 dB gain along 0.7–25.7 GHz bandwidth by consuming 75.2 mW DC power. More than 3.9 dBm output power at 1 dB output compression point (OP1dB) is achieved and the noise figure of the 2D-DA is between 3.6 and 6.4 dB. Using 2D-DA, produced powers from middle stages participate in the outgoing power. This helps to improve gain bandwidth (GBW), power added efficiency (PAE) and OP1dB by 84.3, 143 and 86%.

Effective Design of a 3×4 Two Dimensional Distributed Amplifier Based on Gate Line Considerations

In this paper two dimensional wave propagation is used for power combining in drain nodes of a distributed amplifier (DA). The proposed two dimensional DA uses an electrical funnel to add the currents of drain nodes. The proposed structure is modified due to gate lines considerations. Total gain improvement is achieved by engineering the characteristic impedance of gate lines and also make appropriate variation in the output of gain cells. All variations are done with respect to input and output reflection loss considerations. Analytical expression for the gain of the proposed DA is presented and design considerations for electrical funnel are discussed. Based on two dimensional power combining a wide band DA is simulated using TSMC 0.18 CMOS model in ADS which consumes 49.42 mw from 1.2V power supply. Good agreement between the proposed DA gain and calculated value is achieved. Although one stage DA is used, the final results yield a high figure of merit (FOM) in 0.18 CMOS technology. The final design shows 11.1 dB gain from near DC to 23.6 GHz, noise figure between 3 to 5.2dB and maximum output power of 7.1dBm at 1-dB output compression point (OP1dB).

System simulations of a 1.5\xa0V SiGe 81\u201386\xa0GHz E-band transmitter

This paper presents simulation results for a sliding-IF SiGe E-band transmitter circuit for the 81–86 GHz E-band. The circuit was designed in a SiGe process with fT = 200 GHz and uses a supply of 1.5 V. The low supply voltage eliminates the need for a dedicated transmitter voltage regulator. The carrier generation is based on a 28 GHz quadrature voltage oscillator (QVCO). Upconversion to 84 GHz is performed by first mixing with the QVCO signals, converting the signal from baseband to 28 GHz, and then mixing it with the 56 GHz QVCO second harmonic, present at the emitter nodes of the QVCO core devices. The second mixer is connected to a three-stage power amplifier utilizing capacitive cross-coupling to increase the gain, providing a saturated output power of +14 dBm with a 1 dB output compression point of +11 dBm. E-band radio links using higher order modulation, e.g. 64 QAM, are sensitive to I/Q phase errors. The presented design is based on a 28 GHz QVCO, the lower frequency reducing the phase error due to mismatch in active and passive devices. The I/Q mismatch can be further reduced by adjusting varactors connected to each QVCO output. The analog performance of the transmitter is based on ADS Momentum models of all inductors and transformers, and layout parasitic extracted views of the active parts. For the simulations with a 16 QAM modulated baseband input signal, however, the Momentum models were replaced with lumped equivalent models to ease simulator convergence. Constellation diagrams and error vector magnitude (EVM) were calculated in MATLAB using data from transient simulations. The EVM dependency on QVCO phase noise, I/Q imbalance and PA compression has been analyzed. For an average output power of 7.5 dBm, the design achieves 7.2% EVM for a 16 QAM signal with 1 GHz bandwidth. The current consumption of the transmitter, including the PA, equals 131 mA from a 1.5 V supply.

Two‐dimensional distributed amplifier by 2D‐LC lattice

In this study a new configuration for distributed amplifiers (DAs) is presented for the first time. Using two-dimensional (2D) LC lattices instead of one-dimensional transmission lines leads to 2D wave propagation. This configuration can cover the traditional problem of increasing conventional DA stages by decreasing the distance of power sources to the load. This new additive gain mechanism uses an electrical funnel to add the drain powers. Gain and noise relations are extracted and a broad band, high gain, low noise DA with reasonable DC power consumption is designed. Circuit layout is presented and all inductors and connections are simulated by advanced design system electromagnetic simulator with TSMC 0.18 CMOS layout specifications. Good agreements between post layout simulation results and the presented relations are achieved. The final design shows a 21.8 dB gain along 0.7 to 43.9 GHz band width. The circuit consumes only 183 mw DC power and it shows noise figure less than 7.8 dB. The output power of this circuit at 1-dB output compression point (OP1dB) is more than 8.1 dBm. The proposed technique yields excellent performance in comparison with other design techniques.

Analog Circuit Blocks for 80-GHz Bandwidth Frequency-Interleaved, Linear, Large-Swing Front-Ends

Critical analog electronic circuits for a possible 80-GHz bandwidth, frequency-interleaved, PAM-4 or discrete-multitone (DMT) linear fiber-optic front-end are implemented in a 90-nm SiGe BiCMOS technology. These include a novel vertically coupled, 40–100-GHz bandpass filter, an 80-GHz bandwidth distributed optical modulator driver with a measured output compression point of 13 dBm per side, corresponding to 7 $\text{V}_{\mathrm {pp}}$ output differential swing, and a 125-GHz bandwidth PIN-diode SPST switch with a OP $_{1{-}\mathrm {dB}}$ of 23 dBm, and over 22 dB of isolation up to 160 GHz. The linear modulator driver can also be used as a high linearity (IP $_{1{-}\mathrm {dB}} = \,\, 5$ dBm per side) receiver amplifier in next-generation instrumentation systems.