Output Buffer Research Articles

A High Sensitivity CMUT-Based Passive Cavitation Detector for Monitoring Microbubble Dynamics During Focused Ultrasound Interventions.

Tracking and controlling microbubble (MB) dynamics in the human brain through acoustic emission (AE) monitoring during transcranial focused ultrasound (tFUS) therapy are critical for attaining safe and effective treatments. The low-amplitude MB emissions have harmonic and ultra-harmonic components, necessitating a broad bandwidth and low-noise system for monitoring transcranial MB activity. Capacitive micromachined ultrasonic transducers (CMUTs) offer high sensitivity and low noise over a broad bandwidth, especially when they are tightly integrated with electronics, making them a good candidate technology for monitoring the MB activity through human skull. In this study, we designed a 16-channel analog front-end (AFE) electronics with a low-noise transimpedance amplifier (TIA), a band-gap reference circuit, and an output buffer stage. To assess AFE performance and ability to detect MB AE, we combined it with a commercial CMUT array. The integrated system has 12.3 - [Formula: see text] receive sensitivity with 0.085 - [Formula: see text] minimum detectable pressure (MDP) up to 3 MHz for a single element CMUT with 3.78 [Formula: see text] area. Experiments with free MBs in a microfluidic channel demonstrate that our system is able to capture key spectral components of MBs' harmonics when sonicated at clinically relevant frequencies (0.5 MHz) and pressures (250 kPa). Together our results demonstrate that the proposed CMUT system can support the development of novel passive cavitation detectors (PCD) to track MB activity for attaining safe and effective focused ultrasound (FUS) treatments.

A Low-Power Optoelectronic Receiver IC for Short-Range LiDAR Sensors in 180 nm CMOS.

This paper presents a novel power-efficient topology for receivers in short-range LiDAR sensors. Conventionally, LiDAR sensors exploit complex time-to-digital converters (TDCs) for time-of-flight (ToF) distance measurements, thereby frequently leading to intricate circuit designs and persistent walk error issues. However, this work features a fully differential trans-impedance amplifier with on-chip avalanche photodiodes as optical detectors so that the need of the following post-amplifiers and output buffers can be eliminated, thus considerably reducing power consumption. Also, the combination of amplitude-to-voltage (A2V) and time-to-voltage (T2V) converters are exploited to replace the complicated TDC circuit. The A2V converter efficiently processes weak input photocurrents ranging from 1 to 50 μApp which corresponds to a maximum distance of 22.8 m, while the T2V converter handles relatively larger photocurrents from 40 μApp to 5.8 mApp for distances as short as 30 cm. The post-layout simulations confirm that the proposed LiDAR receiver can detect optical pulses over the range of 0.3 to 22.8 m with a low power dissipation of 10 mW from a single 1.8 V supply. This topology offers significant improvements in simplifying the receiver design and reducing the power consumption, providing a more efficient and accurate solution that is highly suitable for short-range LiDAR sensor applications.

A 128 × 128 SPAD LiDAR sensor with column-parallel 25 ps resolution TA-ADCs

This paper presents a design of single photon avalanche diode (SPAD) light detection and ranging (LiDAR) sensor with 128 × 128 pixels and 128 column-parallel time-to-analog-merged-analog-to-digital converts (TA-ADCs). Unlike the conventional TAC-based SPAD LiDAR sensor, in which the TAC and ADC are separately implemented, we propose to merge the TAC and ADC by sharing their capacitors, thus avoiding the analog readout noise of TAC’s output buffer, improving the conversion rate, and reducing chip area. The reverse start-stop logic is employed to reduce the power of the TA-ADC. Fabricated in a 180 nm CMOS process, our prototype sensor exhibits a timing resolution of 25 ps, a DNL of +0.30/−0.77 LSB, an INL of +1.41/−2.20 LSB, and a total power consumption of 190 mW. A flash LiDAR system based on this sensor demonstrates the function of 2D/3D imaging with 128 × 128 resolution, 25 kHz inter-frame rate, and sub-centimeter ranging precision.

Output buffer glow and its mitigation in H4RG-15 detectors

Output buffer glow and its mitigation in H4RG-15 detectors

39‐1: Invited Paper: An Improved Gate Driver Using Oxide TFTs for Large OLED Displays

In this paper, we present the small area and high reliable gate driver in panels using a‐IGZO TFTs for large OLED displays. The proposed gate driver circuit has a small area structure with multiple output buffers connected to one shift register circuit. To lower the voltage stress of the pull‐down TFTs, which have the highest voltage stress among the TFTs of the gate driver, the initial voltage of those TFTs is set to low and increases according to the threshold voltage shift of TFTs during operation. It could be implemented by sensing the degradation of the TFTs using the programmable DC driving method. With these technologies, we were able to reduce the gate driver design area by 40% and improve the reliability by 30% despite reducing the circuit area. We successfully developed OLED TVs from 42 inches to 97 inches using the proposed gate driver.

A low-power metal–oxide scan driver circuit outputting non-overlapping pulses with DC power-supplied buffer

This paper proposes a novel metal–oxide (MOx) thin-film transistors (TFT)-based scan driver circuit with a DC power-supplied buffer. This circuit has two parts: a ‘carry generation block (CGB)’ and an ‘output generation block (OGB).’ The CGB generates a carry pulse by the bootstrapping effect of pull-up TFT with the aid of clock signal; clock-supplied bootstrapping. Then the OGB is controlled by the carry pulse, and the output pulse is generated by the bootstrapping effect of pull-up buffer TFT with DC power supply; DC-supplied bootstrapping. In the proposed circuit, the pull-up TFT in CGB does not need to have wide dimensions because the carry signal is separated from the large capacitive load in the pixel area. Accordingly, the capacitive load of the clock signal is significantly reduced, and the dynamic power consumption associated with clock toggling decreases remarkably compared with the conventional scan driver circuit that uses the clock-supplied bootstrapping for the wide output buffer TFT. In addition, a bootstrapping inverter in OGB makes the output pulse width the same as the clock-high duration, preventing the output pulses from overlapping, which is required for most of the organic light-emitting diode (OLED) pixel circuits with in-pixel compensation.

Dynamic Job and Conveyor-Based Transport Joint Scheduling in Flexible Manufacturing Systems

Efficiently managing resource utilization is critical in manufacturing systems to optimize production efficiency, especially in dynamic environments where jobs continually enter the system and machine breakdowns are potential occurrences. In fully automated environments, co-ordinating the transport system with other resources is paramount for smooth operations. Despite extensive research exploring the impact of job characteristics, such as fixed or variable task-processing times and job arrival rates, the role of the transport system has been relatively underexplored. This paper specifically addresses the utilization of a conveyor belt as the primary mode of transportation among a set of production machines. In this configuration, no input or output buffers exist at the machines, and the transport times are contingent on machine availability. In order to tackle this challenge, we introduce a randomized heuristic approach designed to swiftly identify a near-optimal joint schedule for job processing and transfer. Our solution has undergone testing on both state-of-the-art benchmarks and real-world instances, showcasing its ability to accurately predict the overall processing time of a production line. With respect to our previous work, we specifically consider the case of the arrival of a dynamic job, which requires a different design approach since there is a need to keep track of partially processed jobs, jobs that are waiting, and newly arrived jobs. We adopt a total rescheduling strategy and, in order to show its performance, we consider a clairvoyant scheduling approach, in which job arrivals are known in advance. We show that the total rescheduling strategy yields a scheduling solution that is close to optimal.

A Ku band low-voltage and low-power CMOS low-noise amplifier with bulk isolation techniques

Abstract In this paper, a broadband(12-18G) low-noise amplifier (LNA) using 65-nm CMOS technology for satellite communication is presented. This LNA was designed in a cascode common source with inductive degeneration topology. In addition, the bulk isolation technique is employed to make the proposed LNA have a higher gain. Furthermore, a two-stage cascaded configuration combined with inductive parallel peaking technology is utilized to make the LNA achieve a wide operating band. For validation, we design this LNA in a 65nm CMOS technology. The simulated results show that S21 of 17.7dB ± 0.5dB, the input/output return loss of -10dB to -33dB and -12dB to -23dB, respectively. It offers the minimum noise figure (NF) performance of 3.33dB, reverse isolation(S12) better than 60dB, and third-order input point (IIP3) of -22.8 dBm obtained over the band of interest. Excluding the output buffer stage, the LNA is consuming 5.1 mW at a supply voltage of 0.8V and its layout area occupies 0.205 mm2.

The Effect of Pixel Design and Operation Conditions on Linear Output Range of 4T CMOS Image Sensors.

We analyze several factors that affect the linear output range of CMOS image sensors, including charge transfer time, reset transistor supply voltage, the capacitance of integration capacitor, the n-well doping of the pinned photodiode (PPD) and the output buffer. The test chips are fabricated with 0.18 μm CMOS image sensor (CIS) process and comprise six channels. Channels B1 and B2 are 10 μm pixels and channels B3-B6 are 20 μm pixels, with corresponding pixel arrays of 1 × 2560 and 1 × 1280 respectively. The floating diffusion (FD) capacitance varies from 10 fF to 23.3 fF, and two different designs were employed for the n-well doping in PPD. The experimental results indicate that optimizing the FD capacitance and PPD design can enhance the linear output range by 37% and 32%, respectively. For larger pixel sizes, extending the transfer gate (TG) sampling time leads to an increase of over 60% in the linear output range. Furthermore, optimizing the design of the output buffer can alleviate restrictions on the linear output range. The lower reset voltage for noise reduction does not exhibit a significant impact on the linear output range. Furthermore, these methods can enhance the linear output range without significantly amplifying the readout noise. These findings indicate that the linear output range of pixels is not only influenced by pixel design but also by operational conditions. Finally, we conducted a detailed analysis of the impact of PPD n-well doping concentration and TG sampling time on the linear output range. This provides designers with a clear understanding of how nonlinearity is introduced into pixels, offering valuable insight in the design of highly linear pixels.

Transmitter for Visible Light Communications based on FPGA’s Output Buffers

Transmitter for Visible Light Communications based on FPGA’s Output Buffers

An Optimized Temperature Compensated Ring Oscillator with Low Power Consumption and Low Variation

In this paper a low power ring oscillator with three differential delay stages and one output buffer stage is designed for Radio Frequency Identification (RFID) applications. The proposed oscillator is designed with neural network model and its parameters are optimized with Teaching–Learning Based Optimization (TLBO) algorithm. The central frequency of the oscillator becomes independent of the temperature with the help of two temperature compensation techniques. In the first technique, the PMOS load transistor of each stage is connected to the NMOS diode connected - in series - transistor. Since these two transistors work in complement of each other, the temperature variation of each stage’s output voltage is decreased. In the second technique, the current variation of oscillator stages versus temperature is reduced since the diode connected transistor is employed in the current source structure. The simulation is done in 0.18 µm Complementary Metal-Oxide Semiconductor (CMOS) technology with the help of Cadence software and the chip area of the layout designed with this software is 19×25 µm2. The designed oscillator exhibits the following parameters: a central frequency of 7.5 MHz, the power dissipation is 238 nW and the frequency deviation is 210 ppm/̊C in the temperature range of 0 to 120ºC, the noise phase and the period jitter are -87.05 dBc/Hz and 0.578 ns (rms), respectively, at 100 KHz offset frequency and 10000 clock cycle.

A Variable-Gain Low-Noise Amplifier for MedRadio Band Applications

A variable-gain 0.18 μm Complementary Metal- Oxide-Semiconductor (CMOS) Low-Noise Amplifier (LNA) for Medical Device Radiocommunications Service (MedRadio) applications has been designed and verified through simulations in Cadence IC5 with Silterra’s C18G CMOS technology Process Design Kit. Unlike other MedRadio LNAs from previous works, this proposed LNA can vary its gain from just above 10 dB to nearly 30 dB. It consists of three stages; the input-matching stage, the interstage buffer, and the gain-varying stage. The input-matching stage provides an input impedance match and drives the initial gain of the LNA. The inter-stage buffer isolates the input-matching stage from the gain-varying stage. The overall gain of the LNA can be varied and is determined by the variable biasing of the driving transistors of the gainvarying stage. On post-layout simulations with a sourcefollower output buffer, this LNA exhibits a wide-ranging gain from 11.2 dB at 0.49 mW DC power consumption to 29.1 dB at 1.34 mW DC power consumption.

A High Efficiency 14–28 Gb/s Tunable Receiver Analog Front-End in 65 nm CMOS Technology

This work presents a tunable receiver analog front-end (AFE) circuit, capable of achieving data rates between 14 Gb/s and 28 Gb/s. The circuit is implemented using the TSMC 65 nm CMOS technology. The circuit incorporates a continuous-time linear equalizer (CTLE), a transimpedance amplifier (TIA) and an output buffer. A [Formula: see text]-boosted technique is employed within the CTLE for bandwidth and gain enhancement, while the TIA leverages a super source follower (SSF) structure to combat parasitic output node issues. By adjusting the tunable structures in the circuit, the proposed AFE can achieve variable DC gain at 14 GHz. Simulation results reveal that the AFE can compensate for the channel loss at the 14 GHz Nyquist frequency, delivering eye diagram spreads of approximately 0.85 UI and 0.78 UI at 14 Gb/s and 28 Gb/s, respectively. The complete post-simulation layout area is only 0.0026[Formula: see text]mm2. Operating with a power consumption of 10.5[Formula: see text]mW, the AFE exhibits an exceptional FoM of 11.8 pJ/bit/dB.

Impact of priority assignment on schedule-based attacks in real-time embedded systems

In this paper, we investigate the impact of priority assignment on schedule-based attacks in fixed-priority real-time systems. Through the schedule-based attacks, attackers may manipulate the input and output buffers of victim tasks, cause instability, and/or steal hidden information. The success of those attacks highly depends on the proper positioning of the malicious task with respect to the victim tasks in the actual schedule. Firstly, we develop an optimal priority assignment algorithm that incorporates the user specified priority preferences that reflect task types (anterior task, posterior task, or victim task), while still meeting all the deadlines. Secondly, we propose a dynamic delaying algorithm to further reduce posterior schedule-based attacks at run-time. Finally, we derive and compare the performance of six attack-aware priority-assignment policies as well as their dynamic extensions through comprehensive simulations. Our results suggest that the well-known RMS algorithm can be easily outperformed in terms of reducing schedule-based attacks, by properly specifying the relative priorities of malicious, anterior, and posterior tasks through our optimal algorithm. In particular, the AMP assignment, which assigns the anterior, malicious, and posterior tasks execution priorities in decreasing order, is shown to offer rather robust and consistent performance even at high system utilizations. Our framework explicitly incorporates the logical execution time and attack effective window constraints to model schedule-based attacks in realistic manner.

W‐band ×8 frequency multiplier in 65 nm CMOS with 25% bandwidth and 4.63 dBm output power

AbstractThis letter presents an ×8 frequency multiplier for the W‐band wireless satellite communication in the 65 nm complementary metal‐oxide‐semiconductor process. To reduce the power consumption, the proposed frequency multiplier employs only one driven amplifier and three stages of doublers. All doublers adopt balanced structures to increase their robustness. The output buffer is introduced to ameliorate the impedance matching of output port so that the output power of the proposed ×8 frequency multiplier can achieve 4.63 dBm. Through the special design of the interstage impedance matching circuit, the relative 3‐dB bandwidth of the proposed frequency multiplier is over 25% (from 74.8 to 96.2 GHz). The chip also has a small size and low power consumption, which is 1.37 × 0.51 mm2 and 125 mW, respectively.

A Comprehensive Large Signal, Small Signal, and Noise Model for IGZO Thin Film Transistor Circuits.

We report a new physics-based model for dual-gate amorphous-indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) which we developed and fine-tuned through experimental implementation and benchtop characterization. We fabricated and characterized a variety of test patterns, including a-IGZO TFTs with varying gate widths (100-1000 μm) and channel lengths (5-50 μm), transmission-line-measurement patterns and ground-signal-ground (GSG) radio frequency (RF) patterns. We modeled the contact resistance as a function of bias, channel area, and temperature, and captured all operating regimes, used physics-based modeling adjusted for empirical data to capture the TFT characteristics including ambipolar subthreshold currents, graded interbias-regime current changes, threshold and flat-band voltages, the interface trap density, the gate leakage currents, the noise, and the relevant small signal parameters. To design high-precision circuits for biosensing, we validated the dc, small signal, and noise characteristics of the model. We simulated and fabricated a two-stage common source amplifier circuit with a common drain output buffer and compared the measured and simulated gain and phase performance, finding an excellent fit over a frequency range spanning 10 kHz-10 MHz.

Thin monolithic pixel sensors with fast operational amplifier output in a 65 nm imaging technology for ALICE ITS3

This work presents results on the Analog Pixel Test Structure (APTS), a 4 × 4 pixel matrix prototype equipped with an output buffer based on the fast individual operational amplifier (OPAMP) of analogue pixel signals to output pads for exploration of pixel timing performance. This work was part of the ALICE ITS3 upgrade and the CERN-EP R&D on monolithic sensors of the TPSCo 65-nm imaging technology. This upgrade will replace the inner layers of the ALICE Inner Tracking System at CERN with ultra-thin flexible wafer-scale monolithic silicon sensors. They will improve the material budget in this region, the tracking precision and the efficiency at low transverse momentum. This paper will show the gain of the signal chain in the APTS and its speed as a function of the configuration parameters, including calibration results with a 55Fe source. Two different pixel structures will be compared to demonstrate the possibility of enhancing the performance in terms of timing and charge collection efficiency by implant modifications in the epitaxial layer. Finally, test beam results planned at the Super Proton Synchrotron at CERN will provide full spatial and time resolution of the APTS OPAMP structures.

Measuring device for systems of technical vibro-diagnosis of power equipment

RELEVANCE. Among the various methods for assessing the technical condition of power equipment, vibration diagnostics occupies an important place. Therefore, improving the quality of hardware for vibration diagnostics is currently extremely important. THE PURPOSE. To develop a vibration sensor with a new principle of operation for systems of technical vibration diagnostics of power equipment, as well as to theoretically substantiate the performance of the proposed sensor. METHODS. When solving the set goal, the main provisions of the theory of vibration diagnostics were applied. RESULTS. A design of the vibration acceleration sensor has been developed, the peculiarity of which is that it is excited by means of constructive coupling capacitors, the first electrode of which is made in the form of a thin-walled metal split cylinder, the role of the second electrodes is performed by the lower row of the winding of each measuring coil, and the function of the inertial element is performed by a screen made in the form of a metal ring fixed on a suspension in the form of a membrane. Based on the electrical equivalent circuit of the sensor, a theoretical substantiation of its operability and efficiency was made. Variants of circuit solutions for the primary and secondary measuring transducers of the measuring device for vibration diagnostics systems have been developed. The primary measuring transducer contains directly a vibration displacement sensor, a sinusoidal voltage source, an input differential measuring amplifier and an analog filter containing a narrow-band filter, a broadband amplifier and a buffer amplifier. The secondary measuring transducer contains a quadrature detector of information signals, an output buffer amplifier and a quadrature reference voltage driver. A block diagram of the hardware solution for the vibration acceleration registration system is also proposed. CONCLUSION. The developed sensor has improved output characteristics and can be used not only for vibration control of power equipment, but also for measuring mechanical vibrations in technical diagnostic systems of various other machines and mechanisms, as well as for tasks of spectral seismic exploration.

Stochastic modelling and analysis of a deteriorating serial production–inventory network

ABSTRACT This study focuses on the stochastic modelling and analysis of a serial production network consisting of two manufacturing stations operating under a make-to-stock inventory policy. The outcome is a single type of product and every manufacturing station includes a machine and an output buffer. Both machines are gradually deteriorating during their operation. Deterioration results in a reduced production rate. Continuous-time Markov chain was used to model all the possible states the network transits over time due to the occurrence of certain events, such as client arrival, deterioration failure, production or repair completion. The structure of the Markov chain was thoroughly studied providing useful information, supporting the effort of numerical solving to determine the steady-state probabilities enabling the calculation of useful performance metrics like equipment availability, down time, idle time, utilisation and average inventory. Through a series of numerical experiments, the behaviour of the serial production network was examined while alternating its parameters. Interesting conclusions emerged regarding the factors affecting the operation of such production systems subjected to gradual deterioration.

Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages

This work presents an improved input–output (IO) buffer model for signal and power integrity simulation, including power/ground supply voltage (PGSV) variations for the buffer’s input and output stages. Both stages are mathematically modeled from a formulation that is derived from nonlinear electrical circuit analysis, an important aspect that grants these models a good level of generality and, simultaneously, high accuracy. The proposed IO buffer model is linear in the parameters and, therefore, extractable through the linear least-squares technique from the signals acquired in an IO buffer characterization setup. Several validation scenarios, supported on two CMOS driver’s transistor technologies, are performed to evaluate the accuracy of the proposed model. In addition, a comparative analysis is provided, confronting the proposed model’s performance against that of the input/output buffer information specification (IBIS) model, evidencing an outstanding modeling improvement provided by the proposed model.