Output Bit Research Articles

Zero-power infrared digitizers based on plasmonically enhanced micromechanical photoswitches.

State-of-the-art sensors use active electronics to detect and discriminate light, sound, vibration and other signals. They consume power constantly, even when there is no relevant data to be detected, which limits their lifetime and results in high costs of deployment and maintenance for unattended sensor networks. Here we propose a device concept that fundamentally breaks this paradigm-the sensors remain dormant with near-zero power consumption until awakened by a specific physical signature associated with an event of interest. In particular, we demonstrate infrared digitizing sensors that consist of plasmonically enhanced micromechanical photoswitches (PMPs) that selectively harvest the impinging electromagnetic energy in design-defined spectral bands of interest, and use it to create mechanically a conducting channel between two electrical contacts, without the need for any additional power source. Our zero-power digitizing sensor prototypes produce a digitized output bit (that is, a large and sharp off-to-on state transition with an on/off conductance ratio >1012 and subthreshold slope >9 dec nW-1) when exposed to infrared radiation in a specific narrow spectral band (∼900 nm bandwidth in the mid-infrared) with the intensity above a power threshold of only ∼500 nW, which is not achievable with any existing photoswitch technologies.

Mixed-Signal Hardware Security: Attacks and Countermeasures for ΔΣ ADC

Mixed-signal integrated circuits (ICs) play an eminent and critical role in design and development of the embedded systems leveraged within smart weapons and military systems. These ICs can be a golden target for adversaries to compromise in order to function maliciously. In this work, we study the security aspects of a tunnel field effect transistor (TFET)-based first-order one-bit delta-sigma ( Δ Σ ) analog to digital converter (ADC) through proposing four attack and one defense models. The first attack manipulates the input signal to the Δ Σ modulator. The second attack manipulates the analog version of the modulator output bit and is triggered by the noise signal. The third attack manipulates the modulator output bit and has a controllable trigger mechanism. The fourth attack manipulates the analog version of the modulator output bit and is triggered by a victim capacitance within the chip. For the defense, a number of signal processing filters are used in order to purge the analog version of the modulator output bit for elimination of the malicious unwanted features, introduced by the attacks. According to the simulation results, the second threat model displays the strongest attack. Derived from the countermeasure evaluation, the best filter to confront the threat models is the robust regression using the least absolute residual computing method.

A Low-Power Three-Tap DFE with Switched Resistor Slicer and CTLE in 0.18μm CMOS Technology

In this paper, a switched resistor slicer is proposed to reduce the power consumption of a decision feedback equalizer (DFE). In the proposed structure, summer circuit that consumes most of the power in a DFE has been eliminated and proper resistors are added as the load of a slicer based on a flip-flop output bit stream. Incorporating the proposed DFE circuit with continuous time linear equalizer (CTLE) at the serial link receiver over a 1[Formula: see text]m NELCO (the NELCO[Formula: see text] N4000-13 series is an enhanced epoxy resin system engineered to provide both outstanding thermal and high signal speed/low signal loss properties) channel can compensate 24[Formula: see text]dB loss at the Nyquist frequency of 2[Formula: see text]GHz. CTLE is adjusted to compensate 6[Formula: see text]dB of channel loss which remains after utilizing a DFE with three taps. The proposed structure has been designed in 0.18[Formula: see text][Formula: see text]m CMOS technology while consuming 13.5[Formula: see text]mW from 1.8[Formula: see text]V supply at 4[Formula: see text]Gb/s with a bit error rate less than 10[Formula: see text]. The proposed equalizer power consumption is reduced by 43% compared to the conventional circuit.

Recovering highly-complex linear recurrences of integer sequences

We suggest a variant of the Berlekamp–Massey algorithm, originally used for recovering a linear shift register from known output bits, for recovering a linear recurrence satisfied by a sequence of natural numbers from known values of the sequence. We present an application of the algorithm to recovering extremely complex recurrences satisfied by the sequences enumerating polyominoes on twisted cylinders.

An improved implementation of hierarchy array multiplier using CslA adder and full swing GDI logic

In this paper, an efficient implementation of a 16 bit array hierarchy multiplier using full swing Gate Diffusion Input (GDI) logic is discussed. Hierarchy multiplier is attractive because of its ability to carry the multiplication operation withi one clock cycle. The existing hierarchical multipliers occupy more area and suffer from accumulation delay of base multiplier output bits. These issues can be addressed by incorporating carry select adder based addition and the multiplier implementation using full swing GDI logic. The basic computation blocks involved in the multiplier are AND gate and carry propagate adder. They are implemented with using full swing GDI logic. Due to their reduced transistor count and less power consumption, this multiplier implementation leads to significant improvement compared with the existing implementations. The designed and existing array multipliers are simulated at 45 nm technology model and their power consumption and delay are calculated from the simulation results. It is validated that the proposed hierarchy array multiplier based on full swing GDI logic has 27% less energy consumption than the existing design. The results confirmed that implemented multiplier has shown better performance and can be used for signal and im age processing.

Construction of resilient S‐boxes with higher‐dimensional vectorial outputs and strictly almost optimal non‐linearity

Resilient substitution boxes (S-boxes) with high non-linearity are important cryptographic primitives in the design of certain encryption algorithms. There are several trade-offs between the most important cryptographic parameters and their simultaneous optimisation is regarded as a difficult task. In this study, the authors provide a construction technique to obtain resilient S-boxes with so-called strictly almost optimal non-linearity for a larger number of output bits m than previously known. This is the first time that the non-linearity bound 2 n−1 − 2 n/2 of resilient (n,m) S-boxes, where n and m denote the number of the input and output bits, respectively, has been exceeded for m>⌊n/4⌋. Thus, resilient S-boxes with extremely high non-linearity and a larger output space compared with other design methods have been obtained.

Yet Another Pseudorandom Number Generator

Abstract We propose a novel pseudorandom number generator based on R¨ossler attractor and bent Boolean function. We estimated the output bits properties by number of statistical tests. The results of the cryptanalysis show that the new pseudorandom number generation scheme provides a high level of data security.

A ± 3 ppm/°C Single-Trim Switched Capacitor Bandgap Reference for Battery Monitoring Applications

A precision bandgap reference has been developed in a $0.18~\mu \text {m}$ BiCMOS process that achieves ±3 ppm/°C temperature drift at ±3 $\sigma $ from −40 °C to 110 °C. The reference is designed to utilize single temperature trim and standard components. A 3.65 V switched capacitor reference voltage is provided to a $2^{{\textrm {nd}}}$ order delta-sigma modulator ADC to digitize a battery cell voltage. The switched capacitor reference utilizes fully differential sampling which reduces the errors from channel charge injection and clock feedthrough introduced by pseudo-differential sampling. A new technique for sampling a $\text {V}_{{\textrm {be}}}$ voltage directly onto the output of the reference’s differential amplifier has been developed that removes the error that would be introduced from differentially sampling the $\text {V}_{{\textrm {be}}}$ and the $\Delta \text {V}_{{\textrm {be}}}$ voltage terms independently. The bandgap reference and ADC combination have an input referred noise spectral density of $4.7~\mu \text {V}/\surd $ Hz from 0.1 to 162 Hz yielding 15 stable output bits.

Mobile cloud computing with a UAV‐mounted cloudlet: optimal bit allocation for communication and computation

Mobile cloud computing relieves the tension between computation-intensive mobile applications and battery-constrained mobile devices by enabling the offloading of computing tasks from mobiles to a remote processors. This study considers a mobile cloud computing scenario in which the `cloudlet' processor that provides offloading opportunities to mobile devices is mounted on unmanned aerial vehicles (UAVs) to enhance coverage. Focusing on a slotted communication system with frequency division multiplexing between mobile and UAV, the joint optimisation of the number of input bits transmitted in the uplink by the mobile to the UAV, the number of input bits processed by the cloudlet at the UAV and the number of output bits returned by the cloudlet to the mobile in the downlink in each slot is carried out by means of dual decomposition under maximum latency constraints with the aim of minimising the mobile energy consumption. Numerical results reveal the critical importance of an optimised bit allocation in order to enable significant energy savings as compared with local mobile execution for stringent latency constraints.

Design of Low-Power Voltage Scalable Arithmetic Units with Perfect Timing Error Cancelation

Many of the existing supply voltage overscaling (VOS) techniques allow an increase in the critical path delay, resulting in the reduction in the throughput rate. On the contrary, the VOS techniques without affecting on the throughput rate induce loss of the system performance by timing errors. In this paper, we propose a perfect timing error cancelation (PTEC) system which not only retains the throughput rate, but also perfectly recovers the system performance. In the arithmetic units whose output bits are sequentially computed, it is observed that timing violations due to VOS occur at some designated highest order output bits, resulting in the large error on the output value. By exploiting this property, a novel timing error cancelation technique is presented by modeling the timing error signal and deriving the condition for the perfect recovery from the impaired signal. The proposed PTEC system is verified with the design example of a 16\(\times \)16 unsigned carry-save multiplier. From simulation results, it is found that the proposed PTEC system with 200 mV overscaling offers 38% power reduction with maintaining the throughput rate as well as the system functionality compared to the conventional design with the nominal supply voltage (=1 V).

Designing S-Box Based on 4D-4Wing Hyperchaotic System

S-box plays an imperative role in designing a cryptographically strong block cipher. Designing S-box based on chaos has attracted lots of attentions because of its distinct characteristics relevant to cryptography. In this paper, a 4D-4wing hyperchaotic system is investigated. Its sophisticated nonlinear behaviors are used to generate two pseudorandom 8-bit integer sequences, which further drive iterative two-position swap on the identical map on GF(28). According to the indicator of typical evaluation criteria including nonlinearity, differential uniformity, strict avalanche criterion, output bits independence criterion and bijective property, the preferred S-box is obtained from all those batch-generated ones. The comparison with the state-of-the-art chaos-based schemes shows that the obtained S-box achieves better cryptographical performance.

E2LEMI:Energy-Efficient Logic Encryption Using Multiplexer Insertion

Due to the outsourcing of chip manufacturing, countermeasures against Integrated Circuit (IC) piracy, reverse engineering, IC overbuilding and hardware Trojans (HTs) become a hot research topic. To protect an IC from these attacks, logic encryption techniques have been considered as a low-cost defense mechanism. In this paper, our proposal is to insert the multiplexer (MUX) with two cases: (i) we randomly insert MUXs equal to half of the output bit number (half MUX insertions); and (ii) we insert MUXs equal to the number of output bits (full MUX insertions). Hamming distance is adopted as a security evaluation. We also measure the delay, power and area overheads with the proposed technique.

Significantly Improved Multi-bit Differentials for Reduced Round Salsa and ChaCha

ChaCha and Salsa are two software oriented stream ciphers that have attracted serious attention in academic as well as commercial domain. The most important cryptanalysis of reduced versions of these ciphers was presented by Aumasson et al. in FSE 2008. One part of their attack was to apply input difference(s) to investigate biases after a few rounds. So far there have been certain kind of limited exhaustive searches to obtain such biases. For the first time, in this paper, we show how to theoretically choose the combinations of the output bits to obtain significantly improved biases. The main idea here is to consider the multi-bit differentials as extension of suitable single-bit differentials with linear approximations, which is essentially a differential-linear attack. As we consider combinations of many output bits (for example 19 for Salsa and 21 for ChaCha), exhaustive search is not possible here. By this method we obtain very high biases for linear combinations of bits in Salsa after 6 rounds and in ChaCha after 5 rounds. These are clearly two rounds of improvement for both the ciphers over the existing works. Using these biases we obtain several significantly improved cryptanalytic results for reduced round Salsa and ChaCha that could not b obtained earlier. In fact, with our results it is now possible to cryptanalyse 6-round Salsa and 5-round ChaCha in practical time.

Significantly Improved Multi-bit Differentials for Reduced Round Salsa and ChaCha

ChaCha and Salsa are two software oriented stream ciphers that have attracted serious attention in academic as well as commercial domain. The most important cryptanalysis of reduced versions of these ciphers was presented by Aumasson et al. in FSE 2008. One part of their attack was to apply input difference(s) to investigate biases after a few rounds. So far there have been certain kind of limited exhaustive searches to obtain such biases. For the first time, in this paper, we show how to theoretically choose the combinations of the output bits to obtain significantly improved biases. The main idea here is to consider the multi-bit differentials as extension of suitable single-bit differentials with linear approximations, which is essentially a differential-linear attack. As we consider combinations of many output bits (for example 19 for Salsa and 21 for ChaCha), exhaustive search is not possible here. By this method we obtain very high biases for linear combinations of bits in Salsa after 6 rounds and in ChaCha after 5 rounds. These are clearly two rounds of improvement for both the ciphers over the existing works. Using these biases we obtain several significantly improved cryptanalytic results for reduced round Salsa and ChaCha that could not b obtained earlier. In fact, with our results it is now possible to cryptanalyse 6-round Salsa and 5-round ChaCha in practical time.

3-Gb/s High-Speed True Random Number Generator Using Common-Mode Operating Comparator and Sampling Uncertainty of D Flip-Flop

True random number generators (TRNGs) are important in data encryption for information security applications. In this paper, we propose a TRNG that utilizes a comparator in the common-mode operation and the sampling uncertainty of a D flip-flop (DFF). The comparator output is affected by the input common-mode noise and the noise that is simultaneously self-induced. A slicer generates an unpredictable and asynchronous pulse to the input of the DFF according to the output-referred noise of the comparator. By sampling the random pulse with a 3-GHz external clock, there is a sampling uncertainty, which helps to increase the random quality. As a result, we use the independent two random sources for TRNG. The area of the designed circuit is 1609 $\mu \text{m}^{\mathrm { {2}}}$ . In spite of the small size, the data rate of the proposed TRNG is 3 Gb/s. We verify that the output bit stream passes all of the National Institute of Standards and Technology test suites. We fabricate the TRNG in a 65-nm CMOS process with a 1.2 V supply voltage. The power consumption of the proposed TRNG is 5 mW, and the energy per bit is 1.6 pJ/b.

Critical Gates Identification for Fault-Tolerant Design in Math Circuits

Hardware redundancy at different levels of design is a common fault mitigation technique, which is well known for its efficiency to the detriment of area overhead. In order to reduce this drawback, several fault-tolerant techniques have been proposed in literature to find a good trade-off. In this paper, critical constituent gates in math circuits are detected and graded based on the impact of an error in the output of a circuit. These critical gates should be hardened first under the area constraint of design criteria. Indeed, output bits considered crucial to a system receive higher priorities to be protected, reducing the occurrence of critical errors. The 74283 fast adder is used as an example to illustrate the feasibility and efficiency of the proposed approach.

An Almost-Optimally Fair Three-Party Coin-Flipping Protocol

In a multiparty fair coin-flipping protocol, the parties output a common (close to) unbiased bit, even when some corrupted parties try to bias the output. Cleve [in Proceedings of the 20th Annual ACM Symposium on Theory of Computing (STOC), ACM, New York, 1986, pp. 364--369] has shown that in the case of dishonest majority (i.e., at least half of the parties can be corrupted), in any $m$-round coin-flipping protocol the corrupted parties can bias the honest parties' common output bit by $\Omega(\frac 1{m})$. For more than two decades the best known coin-flipping protocols against dishonest majority had bias $\Theta(\frac {\ell}{\sqrt{m}})$, where $\ell$ is the number of corrupted parties. This was changed by a recent breakthrough result of Moran, Naor, and Segev [in Theory of Cryptography, Lecture Notes in Comput. Sci. 5444, Springer, Berlin, 2009, pp. 1--18], who constructed an $m$-round, two-party coin-flipping protocol with optimal bias $\Theta(\frac 1 m)$. In a subsequent work, Beimel, Omri, and Orlov [in Proceedings of the 22nd Annual ACM Symposium on Theory of Computing (STOC), ACM, New York, 1990, pp. 503--513] extended this result to the multiparty case in which less than $\frac23$ of the parties can be corrupted. Still, for the case of $\frac23$ (or more) corrupted parties, the best known protocol had bias $\Theta(\frac {\ell}{\sqrt{m}})$. In particular, this was the state of affairs for the natural three-party case. We take a step toward eliminating the above gap, presenting an $m$-round, three-party coin-flipping protocol, with bias $\frac{O(\log^3 m)}m$. Our approach (which we also apply to the two-party case) does not follow the “threshold round" paradigm used in the work of Moran, Naor, and Segev and Beimel, Omri, and Orlov but rather is a variation of the majority protocol of Cleve used to obtain the aforementioned $\Theta(\frac {\ell}{\sqrt{m}})$-bias protocol.

COZMO - A New Lightweight Stream Cipher

This paper deals with the merger of the two lightweight stream ciphers – A5/1 and Trivium. The idea is to make the key stream generation more secure and to remove the attacks of the individual algorithms. The bits generated by the Trivium cipher (output) will act as the input of the A5/1 cipher. The registers used in the A5/1 cipher will be filled by the output bits of the Trivium cipher. The three registers will then be connected to generate an output which will be our required key stream.

Optimal Bitrate Allocation in the Scalable HEVC Extension for the Deployment of UHD Services

Ultra high definition (UHD) is the latest trend in broadcasting area, which enables new services with $3840\times 2160$ resolution and comes with enhanced color-gamut, frame-rate, dynamic range, and better audio system compared to the currently deployed HD services. The UHD format for broadcasting is already under standardization in the digital video broadcasting consortium which plans to introduce UHD services in three phases. The increase in data brought by these services requires more efficient compression and transmission systems. The recent scalable video coding standard scalable High Efficiency Video Coding (SHVC) is a promising candidate to handle these three phases while ensuring backward compatibility. Moreover, delivering such contents over networks needs an accurate control of the output bitrate from encoder engines to match rigid constraints on bandwidth and QoS. Several contributions have already been proposed to jointly encode scalable stream, but without considering the impact of bitrate ratio between layers on the compression performance. In this paper, the impact of the bitrate ratio between layers on the coding performance is first investigated for several UHD scalable schemes including spatial, color-gamut, and SDR-to-HDR scalability in SHVC. Based on this investigation, an adaptive rate control algorithm which dynamically allocates the bitrate between two layers is proposed to optimize the performance under quality and bitrate constraints. The algorithm has been implemented in the SHVC reference software (SHM9.0) and tested over 15 video sequences under two industrial use-cases. The performance shows an average BD-BR improvement of 7.51% and 3.35% for these two use-cases.

A novel method of S-box design based on discrete chaotic map

A new method for obtaining random bijective S-boxes based on discrete chaotic map is presented. The proposed method uses a discrete chaotic map based on the composition of permutations. The obtained S-boxes have been tested on the number of criteria, such as bijection, nonlinearity, strict avalanche criterion, output bits independence criterion, equiprobable input/output XOR distribution and maximum expected linear probability. The results of performance test show that the S-box presented in this paper has good cryptographic properties. The advantage of the proposed method is the possibility to achieve large key space, which makes it suitable for generation of $$n\times n$$ S-boxes for larger values of n. Also, because this method uses discrete chaotic map based on the composition of permutations which has finite space domain, there is no need for discretization of continuous values of chaotic map, so the process of generation of S-boxes is not affected by approximations of any kind.