Output Back-off Research Articles

Design and Experimental Validation of a High-Efficiency Sequential Load Modulated Balanced Amplifier

The purpose of this paper is to present a detailed design procedure for a highly efficient sequential load-modulated balanced amplifier (SLMBA) to provide an in-depth analysis of this complex power amplifier (PA) architecture. SLMBA’s basic theory is presented and discussed. An SLMBA with a frequency range from 2.45 GHz to 2.65 GHz was implemented and then measured in order to validate the proposed design methodology. In both saturation and back-off states, the fabricated SLMBA exhibits extremely high efficiency and output power. It delivers a maximum output power of 43~44.4 dBm and a drain efficiency (DE) of 71.6~75% at saturation, a DE of 63.5~66% at 6 dB output back-off (OBO) state, a DE of 61.8~66% at 10 dB OBO state, and a DE of more than 51% at 12 dB OBO state in the targeted frequency band. The achieved results demonstrate the effectiveness of the proposed design procedure.

Analysis and design of hybrid Doherty-Outphasing power amplifier

This paper theoretically analyzes the network phase solution space under Doherty, Outphasing, and hybrid modes. A dual-input wideband Doherty-Outphasing power amplifier (DOPA) design method is proposed. This method can ensure that the output back-off (OBO) amount is further increased based on the OBO amount of Doherty power amplifier. To prove the reliability of the proposed method, a hybrid DOPA power amplifier in the band of 1.7–2.4 GHz with an OBO amount of 12 dB is designed. The experimental results also show that the output power of the hybrid DOPA is 48.6–49.5 dBm in the band of 1.7–2.3 GHz, and the saturation efficiency is 57%–63%. The efficiency at 12 dB, 9 dB and 6 dB OBO is 42%–50%, 46%–59% and 50%–63% respectively. The digital pre-distortion correction is carried out at 1.8, 2.1 and 2.3 GHz frequency points, and the adjacent channel power ratio is lower than -47.7 dBc. Simulation and experiment results can verify the effectiveness and correctness of the proposed method. To the best of our knowledge, it is the first time to achieve such a wide bandwidth to the hybrid DOPA with the proposed design method.

Asymmetric Doherty power amplifier design considering the effects of peaking power amplifier early conduction

During the design of a Doherty power amplifier (DPA), the phenomenon of peaking PA turning on in advance is commonly observed. This is mainly due to the feedback of the main PA signal to the gate of the peaking PA through the gate-drain feedback capacitor, which results in an increase in its gate voltage. As a result, the overall efficiency of the back-off region is significantly reduced. This paper first describes the phenomenon of peaking PA turning on in advance. The formula for the voltage (referred to as the feedback gate voltage, FGV) imposed on the gate of the peaking PA by the main PA signal is then deduced. On this basis, the FGV is analysed numerically. For verification, an asymmetric DPA with a 9 dB output back-off (OBO) power level is designed and fabricated in this paper using GaN CGH40010F and CGH40025F transistors. According to the measurement results, the saturated drain efficiency of the DPA is 53.5%–63.3% in the 0.75–1.25 GHz band, the efficiency at the 9 dB OBO level is between 45.5%–54%, and the saturated output power is between 45 dBm–45.7 dBm, with a saturation gain of more than 8 dB.

Power characteristics of a high-performance helix traveling wave tube

Traveling Wave Tubes (TWT) are most widely used in civil, defense, and space applications as power amplifiers over a wide range of frequency. When a TWT works at a higher bandwidth, it suffers from nonlinearities, which affects the overall performance of the tube and hence the required results aren't achieved. So, optimization of a TWT is required, mainly in terms of its power characteristics. Power characteristics of the TWTs are specified in terms of output power at different input drive levels, AM/PM transfer and AM/PM conversions, input, and output back-off, gain at saturation, etc. Some of the linearity factors like 3rd order inter modulation product (IMP), and the 1 dB compression point are also optimized. An exhaustive study has been made to achieve the optimum performance of a 140W TWT in Ku-Band. The result has been validated by experimental results.

Extension of Output Backoff Range in Three-Stage Load Modulated Balanced Amplifier Using Asymmetric Coupling and Non-$Z_{0}$ Load

Extension of Output Backoff Range in Three-Stage Load Modulated Balanced Amplifier Using Asymmetric Coupling and Non-$Z_{0}$ Load

Development Review of Highly Efficient Sequential Power Amplifier with Extended Back-Off Range for Broadband Application

Similar to a Doherty power amplifier (DPA), a sequential power amplifier (SPA) is mainly composed of a main amplifier, an auxiliary amplifier and a combiner. However, SPA breaks the bandwidth limitation of the impedance inverter in the DPA, and also simplifies the design procedure. Since the main amplifier has no load modulation, it is easy for the SPA to realize broadband operation and improve the output back-off (OBO) power range. Therefore, SPA has great advantages and potential in expanding bandwidth, improving drain efficiency and expanding the back-off range of a power amplifier simultaneously. This paper describes the evolution and classification of the SPA. First, the basic theory of the SPA is reviewed. Then, some two-way SPAs using coupler and circulator as a power combiner are discussed. Thirdly, the latest popular sequential load modulated balanced amplifier is overviewed.

A GaN MMIC Load-Modulated Balanced Amplifier With Modified Output Coupler for Efficiency Enhancement Over a Larger Power Back-Off Range

This brief firstly presents a monolithically microwave integrated circuit (MMIC) load-modulated balanced amplifier (LMBA) developed in 0.15um GaN process. In this brief, the asymmetric output coupler is applied for further enhancing output power and output back-off (OBO) efficiency over a larger OBO range. This MMIC LMBA operating mode is dependent on a three-ways active load modulation process by modified the coupling coefficient of output coupler which can provide more design parameters and freedom. To validate the proposed LMBA at millimeter wave (mm-wave), a 24.7-25.7 GHz MMIC LMBA is demonstrated, fabricated and tested. Measurements show that this MMIC LMBA can deliver a 35.2-dBm saturated output power with a peak drain efficiency of 37.7%. At 6-dB/8-dB/10-dB OBO, 23.8-30 %, 24.2-27 % and 20-24% power added efficiencies (PAE) can be obtained, respectively. The measured S21 is 15-dB with a 1 0.4-dB gain variation. When driven by a 100MHz 64-QAM OFDM modulation signal with a PAPR of 9.2-dB, the measured ACPR is improved to -45.04 dBc with DPD. In this case, the PA achieves an average efficiency of 25.2% and a 26.2-dBm average output power.

A High Efficiency 100-W E-Band Continuous Wave Traveling Wave Tube

A continuous wave (CW) E-band traveling wave tube (TWT) is developed to meet the demand of broadband, high power and high efficiency amplifiers for future wireless communications. Several methods are combined to improve the TWT performance, in particular the efficiency, including: increase of the interaction impedance by setting operation point near the cutoff frequency, use of the folded waveguide (FWG) slow wave structure (SWS) with modified circular bends (MCBs) and the phase velocity jumping (PVJ) technique. A novel dual-mode asymmetry multistage depressed collector is used to significantly improve the recovery efficiency without the return of electrons. The first prototype tube has been assembled and tested. A total efficiency of 43% with an electronic efficiency of 9.8%, output power of 120 W and gain of 41 dB is achieved in 81-86GHz where the beam voltage is 15.8kV and the beam current is 77mA. The tube shows very flat output characteristics in saturation state and provides high linear power and efficiency. The -1dB compression point output is over 50W with the linear (output back off 4dB) total efficiency up to 26.4%.

A Comparative Analysis of Doherty and Outphasing MMIC GaN Power Amplifiers for 5G Applications.

A comparison between a fully integrated Doherty power amplifier (DPA) and outphasing power amplifier (OPA) for fifth Generation (5G) wireless communications is presented in this paper. Both amplifiers are integrated using pHEMT transistors from the OMMIC's 100 nm GaN-on-Si technology (D01GH). After a theoretical analysis, the design and layout of both circuits are presented. The DPA uses an asymmetric configuration where the main amplifier is biased in class AB and the auxiliary amplifier is biased in class C, while the OPA uses two amplifiers biased in class B. In the comparative analysis, it has been observed that the OPA presents a better performance in terms of maximum power added efficiency (PAE), while the DPA provides higher linearity and efficiency at 7.5 dB output back-off (OBO). At a 1 dB compression point, the OPA exhibits an output power of 33 dBm with a maximum PAE of 58.3% compared to 44.2% for the DPA for an output power of 35 dBm, and at 7.5 dB OBO, the DPA achieves a PAE of 38.5%, while the OPA achieves 26.1%. The area has been optimized using absorbing adjacent component techniques, resulting in an area of 3.26 mm2 for the DPA and 3.18 mm2 for the OPA.

A 5-W GaN Doherty Amplifier for Ka-Band Satellite Downlink With 4-GHz Bandwidth and 17-dB NPR

This letter presents the design and experimental characterization of a GaN–Si monolithic Doherty power amplifier (PA) for the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Ka$ </tex-math></inline-formula> -band satellite downlink. The fabricated amplifier favorably compares with the current state of the art, achieving from 16.3 to 20.3 GHz (4 GHz, 22% relative bandwidth), a record band to date, 36.6–37.7-dBm output power, 23%–31% power-added efficiency, 18–22-dB gain at saturation, and around 20% power-added efficiency at 6-dB output back-off. At 18.8 GHz, the amplifier shows a noise-to-power ratio higher than 17 dB at all power levels, making it suitable for satellite applications where additional linearization is usually unfeasible.

Dual-Band Three-Way Doherty Power Amplifier Employing Dual-Mode Gate Bias and Load Compensation Network

This article presents a new method to design dual-band three-way Doherty power amplifiers (DPAs). A novel modified load modulation network (LMN) is constructed for enabling dual-mode Doherty operation with three-way configuration, providing enhanced high efficiency range in both modes. Moreover, a parallel load compensation network (LCN) is employed in the proposed three-way DPA to provide wideband performance in each operation band. A three-way dual-mode DPA using commercial gallium nitride high electron mobility transistors (GaN HEMTs) is then designed and manufactured to verify the proposed architecture. Frequency bands of 1.45&#x2013;1.9 GHz in Mode I and 0.75&#x2013;1.0 GHz in Mode II are achieved by the DPA, respectively. The fabricated DPA has a 9-dB output back-off (OBO) efficiency of 42.8&#x0025;&#x2013;57.7&#x0025; and a saturated efficiency of 55.4&#x0025;&#x2013;70.1&#x0025;. When driven by a 20-MHz long term evolution (LTE) modulated signal with 8-dB peak-to-average ratio (PAPR), the adjacent channel power ratio (ACPR) of the fabricated DPA is better than &#x2212;49.9 dBc after digital predistortion at 0.9 and 1.7 GHz with average efficiency of 45.7&#x0025; and 54.6&#x0025;.

Broadband Class-J GaN Doherty Power Amplifier

This paper presents a broadband 3–3.7 GHz class-J Doherty power amplifier exploiting second harmonic tuning in the output network. Furthermore, the output impedance inverter is eliminated and its effect is embedded in the main device’s output matching network, thus trading off among bandwidth, efficiency, and gain. The proposed amplifier adopts two 10 W packaged GaN transistors, and it achieves in measurement 60–74%, and 46–50% drain efficiency at saturation and 6 dB output back-off, respectively, with a saturated output power of 43–44.2 dBm and a small-signal gain of 10–13 dB. The proposed DPA exhibits a simulated adjacent channel power ratio less than −30 dBc at 36 dBm average output power, when a 16-QAM modulation with 5 MHz bandwidth is applied to the 3.5 GHz carrier.

A Dual-Band and Dual-State Doherty Power Amplifier Using Metal-Integrated and Substrate-Integrated Suspended Line Technology

In this article, a novel design method of dual-band and dual-state (DBDS) Doherty power amplifier (DPA) is proposed. Considering the actual parasitic parameters, the DPA can be designed by using the impedance transformation of saturation and back-off points at dual frequency bands of DBDS as well as second harmonic matching. The DBDS DPA for dual-band (DB) 5G application, i.e., 3.4 and 4.9 GHz band are designed and implemented, for the first time, by using metal-integrated and substrate-integrated suspended line (MI-SISL) technology, which has advantages of high performance and self-packaging. The fabricated DBDS DPA achieves the measured 44 and 43.2 dBm saturated power at 3.4 and 4.9 GHz bands, respectively. For the 3.4 and 4.9 GHz bands, the measured drain efficiency (DE) is 70.7% and 70.4% at peak power levels and 38% and 42% at a 6-dB output back-off, respectively. When driven by a 20- and 100-MHz modulated signal with 6-dB peak-to-average power ratio (PAPR), the adjacent channel leakage ratio is better than −27 dBc at operating frequencies. The average output power of 38 and 37 dBm with an average efficiency of 37.9% and 40.9% is achieved at 3.4 and 4.9 GHz, respectively.

A Compact CMOS Broadband Bidirectional Digital Transceiver Frontend With Capacitor Bank and Transformer Matching Network Reuse

This article presents a fully integrated bidirectional class-G digital Doherty switched capacitor transmitter (TX) and N-path Quadrature receiver (RX) in CMOS. Through sharing on-chip capacitor banks, typically occupying a major portion of the digital TX or RX chip area, as well as the RF passive matching networks, the overall size can be radically reduced. Moreover, the overall performance could be further improved by eliminating the need for an integrated T/RX switch and its corresponding loss and area overhead. The class-G operation is used within the Doherty TX to increase the output power and backoff efficiency, while the capacitive stacking technique is used in the RX to increase the voltage gain. A transformer network is used to present the optimum impedance for both the parallel Doherty TX and RX mode of operation, as well as the class-G Doherty active load modulation. As a proof-of-concept, the joint bidirectional class-G digital Doherty switched-capacitor TX and N-path Quadrature RX through capacitor bank sharing is implemented in a 45-nm CMOS SOI process. The TX demonstrates a P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> 1dB bandwidth (BW) of 1.6-3.1 GHz, a fractional BW >63%, and peak output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> ) of 22.5dBm at 2.4GHz. The peak drain efficiency (DE) of the TX is 49.5% at 1.8GHz and 41.5%/38.7%/31.6%/18.1% for the peak/2.5/6/12dB power back off (PBO) at 2.4GHz. The DE improvement compared to class-B PA is 1.24×/1.51×/1.72× at 2.5/6/12dB PBO. The TX is measured using 64-QAM/20MHz modulation without the use of AM-PM pre-distortion or pattern based DPD. It achieves an excellent -27.1dB EVM, -31.31dBc ACLR, 14.6dBm average P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> and 25.8% average DE at 1.6GHz. The RX achieves a noise figure (NF) of 7.6dB at 2.2GHz and a conversion gain of 17dB with a 12 MHz bandwidth. In addition, the proposed RX front-end achieves < -60 dBm LO leakage over the operating frequency range.

복소결합부하를 이용한 3.5 GHz 대역의 고효율 비대칭 도허티 전력증폭기 설계

In this study, a high-efficiency asymmetric Doherty power amplifier (DPA) based on a complex combining load (CCL) is presented. The CCL method extends the range of output back-off (OBO). This article provides a graphical design method using the Smith chart for the CCL-DPA load network. The proposed asymmetric DPA is designed using 6 and 10 W GaN-HEMTs for carrier and peaking amplifiers, respectively. With 3.5～3.6 GHz continuous-wave signal excitations, the implemented asymmetric CCL DPA exhibits a DE of 60.0～64.7 % and a PAE of 54.8～59.9 % at a maximum output power of 42.0～43.0 dBm. In addition, it has a DE of 51.3～51.6 %, and a PAE of 46.7～47.6 % at an output power of 35.0 dBm. Using an LTE signal with a PAPR of 7.5 dB and a signal bandwidth of 20 MHz, a power gain of 10.7～11.5 dB, a PAE of 44.0～45.1 %, a DE of 48.1～48.5 %, and an ACLR of −31.1 dBc are achieved. Using DPD linearization, ACLR is improved to −49.3/−50.4 dBc at an average power of 35.0 dBm.

확장된 백오프 출력에서 고효율 동작을 위한 최적화된 대칭 이단 도허티 전력 증폭기 설계

This article presents a symmetric two-stage Doherty power amplifier (DPA) for the extended output power back-off level, which can be attained even with a reduced circuit size by changing the output impedance of the peaking amplifier to be inductive without the offset line. The ABCD matrix is employed to design the output matching network of the peaking amplifier with a simple transmission line. Consequently, we can reduce the design complexity by applying the same circuit to the carrier amplifier as the DPA is symmetric. To deal with reduced output power of the class-C peaking amplifier, a two-stage DPA structure was applied. The power amplifier exhibited a drain efficiency (DE) of 63.5 %, and a power added efficiency (PAE) of 50.6 % at 7.5 dB output backoff was obtained using the 3.5 GHz pulsed continuous wave (CW) signal. Furthermore, a DE of 53.3 %, a PAE of 43.2 % and a power gain of 18 dB were obtained at the power level of 41 dBm using a 20 MHz LTE signal with a peak-to-average power ratio of 7.5 dB.

Peak-Current-Ratio-Enhanced Compact Symmetrical Doherty Amplifier Design by Using Active Harmonic Control

This article proposes a new and compact symmetrical Doherty power amplifier (DPA) configuration that provides extended output-back-off (OBO) and enhanced load modulation. The concept of active harmonic control (AHC) is introduced to remedy the reduced-conduction-angle operation of the class-C auxiliary device, providing enhanced auxiliary current and power capability. Semianalytical study based on generalized load-modulation theory and large-signal simulation reveal that an optimal AHC can offer increased peak current ratio, improved load modulation, boosted output power, and power utilization factor (PUF). Besides, a new output combiner, with the inclusion of parasitic effect, is devised for ultracompactness and simplicity. For verification, a 11-dB-OBO 2-GHz symmetrical DPA based on GaN HEMT transistors is designed, fabricated, and measured. Excellent performance with drain efficiency of 74% (52%) is obtained at saturation (back-off of 11 dB). Moreover, a saturation power of 42.98 dBm is achieved, corresponding to an uplifted PUF of 1.25 (compared with conventional symmetrical DPA design). Under 20-MHz modulated signal (peak-to-average power ratio of 11 dB) excitation, the prototype exhibits average efficiency of 53.2% at an average output power of 32 dBm. The adjacent channel leakage power ratio (ACLR) is found to be −27.5 and −50.9 dBc before and after digital predistortion, respectively.

Watt-Level 21–25-GHz Integrated Doherty Power Amplifier in GaAs Technology

This letter presents the design and characterization of a Doherty power amplifier for K-band applications based on the GaAs 150-nm pseudomorphic HEMT (pHEMT) technology of Qorvo. For the output power combiner, a wideband design approach, based on embedding the output capacitance of the active devices in the combiner, is applied. A state-of-the-art bandwidth of 4 GHz is achieved: in the 21–25-GHz range, the output power is above 29.5 dBm, with an associated power added efficiency (PAE) higher than 30%. At 6-dB output back-off, the PAE is above 19% while the corresponding gain is higher than 10 dB.

A 8–12 GHz, 44.3 dBm RF output class FF−1 DPA using quad-mode coupled technique for new configurable front-end 5G transmitters

This paper presents a high-efficiency Class $${\mathrm{FF}}^{-1}$$ DPA using the quad-mode coupled technique for new configurable front-end 5G transmitters. The proposed DPA consists of carrier PA, main PA, input–output matching network and hybrid power network (HPN). The HPN includes a quad-mode coupled technique which is four-section U-shaped transmission line. The HPN is used for even–odd mode impedance analysis to ensures the high-selectivity of output power and achieve a wideband response in the presence of harmonic control conditions. The optimum harmonic impedance is analyzed for the desired band to achieve high output power and efficiency. The DPA circuit is fabricated by using 0.25 µm GaN HEMT on silicon nitride monolithic microwave integrated circuit die process. At maximum output power level of 44.3 dBm, the delivered power-added efficiency (PAE) of 64.3–67.3% and drain efficiency (DE) of 71.7–73.7% at even–odd mode operation are achieved with a gain of 13.0–14.3 dB. For the output power level of 39.045 dBm corresponding to 9 dB output back-off (OBO), the drain efficiency lies between 55–62% with 73% fractional bandwidth. All the demonstrated transmission parameters are working in the band of 8–12 GHz. The size of the chip is 2.8 × 1.9 mm2 and it occupies less die area as compared to the existing DPAs.

Fully integrated three-way LDMOS Doherty PAs for 1.8–2.2 GHz dual-band and 2.6 GHz m-MIMO 5G applications

AbstractThis paper presents a fully integrated three-way Doherty architecture to address the challenges of 5G applications using laterally-diffused metal-oxide semiconductor (LDMOS) technology. By using the so-called CDS cancelation method for the Doherty combiner design, a wideband impedance transformation is achieved, that combined with the three-way Doherty power amplifier (DPA) architecture allows for high efficiency in deep back-off, with a reduced load modulation for high bandwidth. Throughout this paper, the design approach and realization are described, while multiple critical design challenges will be addressed such as low frequency drain resonance optimization, impact of in-package coupling effects, and linearity versus efficiency tradeoff. Two state-of-the-art three-way fully integrated LDMOS DPA monolithic microwave integrated circuit (MMICs) are presented to demonstrate how these measures have been successfully applied to different power amplifier (PA) line-up components for 5G base station systems. First, a 60 W 1.8–2.2 GHz multi-stage device for driver application in true dual-band operation is presented. The circuit design pays special attention to extended PA video bandwidth thanks to integrated passive device. After digital pre-distortion (DPD) in dual-band operation, this highly linear device achieves an outstanding adjacent channel leakage ratio (ACLR) of −56 dBc for a 2cLTE 20 MHz 8 dB peak-to-average ratio signal spaced by 345 MHz, thus 385 MHz instantaneous bandwidth (IBW), with 29% efficiency at 35 dBm, 12 dB output back-off (OBO). Second, the simulation and measurement results of a 55 W 2.6 GHz multi-stage DPA for massive-MIMO final stage application are presented, which yields an excellent linearized efficiency of 49% using a 200 MHz 10cLTE signal with an ACLR lower than −47.5 dBc. For 8cLTE 20 MHz (160 MHz IBW), the device yields 50% efficiency with −50.7 dBc ACLR linearized after DPD. The achieved efficiency is well comparable to published GaN DPAs. These results were achieved by improved simulation techniques to minimize frequency dispersion and thus allow high efficiency operation over wide bandwidth. Both devices show that LDMOS is not only a mature technology which allows those PAs to be reliable and low-cost for mass production in very compact packages, but also provide best-in-class RF performance according to the needs of 5G base station systems.