Out Of Order Research Articles

BBR-based and fairness-guaranteed congestion control and packet scheduling for MPQUIC over heterogeneous networks

Multipath QUIC (MPQUIC) enables concurrent transmission over multiple paths, making it attractive to enhance the delivery performance of smartphones with multiple interfaces. Nevertheless, several issues in the current MPQUIC specification remain inadequately addressed. Congestion control in MPQUIC primarily relies on packet loss and favors paths with lower drop rates, which results in significant throughput degradation, especially in heterogeneous wireless networks with frequent random packet loss and varying path characteristics. Additionally, network fairness principles limits its performance, even in scenarios with independent and non-shared bottleneck paths. A final issue is that packet scheduling in dynamic and asymmetric paths poses a significant challenge, potentially causing out-of-order (OFO) arrivals and Head-of-Line (HoL) blocking if not appropriately managed. Inspired by Google’s BBR algorithm, this paper introduces a novel scheme called Shared Bottleneck and BBR-based Congestion Control (S2B2C) to address the above issues. It identifies subsets of subflows that share common bottlenecks within the MPQUIC connection based on the BBR’s internal mechanism. The scheme dynamically adjusts the pacing rate of these subflows to enhance goodput while preserving fairness with legacy single-path flows. Then, to mitigate inter-stream and intra-stream HoL blocking caused by OFO arrivals over asymmetric paths, we present a fine-grained Stream-path-bounded Priority-based Packet Scheduler (S2PS), which includes a stream dependency tree, a priority-based queuing, and a packet scheduling algorithm that uses a mixed-integer program formulation. Experimental results show that S2B2C achieves higher throughput while maintaining bottleneck fairness, and S2PS effectively mitigates HoL blocking with fewer OFO arrivals and shorter flow completion time compared to existing MPQUIC schemes in heterogeneous networks.

Enhancing MPTCP performance in wireless networks with PRS-MPTCP

In recent years, there has been a significant increasing demand for wireless networks, particularly mobile communication. Additionally, smart devices like mobile phones and tablets are able to use multiple interfaces simultaneously. In this regard, the concept of Multipath TCP (MPTCP) has been introduced, enabling the utilization of multiple interfaces for concurrent communication. However, packet loss and subflow heterogeneity, especially in wireless networks, cause an increase in Out-of-Order (OfO) packets at the receiver node, which leads to a decrease in the total MPTCP throughput. To address these performance-related challenges, numerous schedulers have been proposed. However, most existing methods have primarily focused on improving performance without adequately considering the impact of packet loss. This research paper provides a comprehensive overview of MPTCP schedulers. Subsequently, we propose a Practical and Robust Scheduler for MPTCP (PRS-MPTCP) with the specific aim of minimizing OfO packets to improve MPTCP performance in wireless systems. The PRS-MPTCP scheduler takes into account various characteristics of each subflow, including RTT, CWND, and the number of packet losses, to effectively decide which packets should be assigned to which subflow. By using Mininet-WiFi emulation, fair comparisons between PRS-MPTCP and the state-of-the-art schedulers have been conducted, considering throughput, the number of OfO packets, and retransmission rates as performance metrics. The evaluation results reveal the profound impact of selected parameters on the behavior of the schedulers and the overall performance of MPTCP. Ultimately, the results demonstrate that PRS-MPTCP guarantees acceptable throughput and achieves lower retransmission rates and fewer OfO packets compared to other methods. In the PRS-MPTCP, the number of OfO packets has decreased by 38 %, 37 %, 45 %, and 44 % compared to BLEST, ECF, RR, and the Default scheduler, respectively.

A Low-Latency MPTCP Scheduler for Live Video Streaming in Mobile Networks

It is a known issue that low-latency communication is hard to achieve when using multiple network interfaces with asymmetric capacity and delay (e.g., LTE and WLAN) simultaneously. A main underlying cause of this issue is that the packets with lower sequence number are stalled on a high-latency path, thus the early arriving packets with higher sequence number become “out-of-order (OFO)” packets. These OFO packets may excessively consume receiver’s buffer, causing long reordering delay and unnecessary packet retransmission. In this paper, we present a novel design of packet scheduling for Multipath TCP (MPTCP), called OverLapped Scheduler (OLS), able to tackle the OFO-packet problem more effectively. OLS can guarantee sufficient throughput on demand of upper layer applications, and utilizes the remaining bandwidth to reduce OFO-packets. To do so, OLS schedules packets according to their arrival time and sends a controlled number of redundant packets to avoid the impact of inaccurate arrival-time estimations due to network jitter. We implement OLS in a Linux kernel, and the experiments show that in asymmetric networks with or without jitter, OLS can effectively reduce OFO-packets and transmission latency while maintaining a sufficient throughput, which makes it fully capable to meet the requirements of applications such as live video streaming.

Loss-Aware Throughput Estimation Scheduler for Multi-Path TCP in Heterogeneous Wireless Networks

Multi-path TCP (MPTCP) is increasingly popular with the widespread usage of multihomed devices. MPTCP allows data streams to be delivered across multiple simultaneous connections, providing higher bandwidth aggregation and throughput in comparison with single-path TCP. However, due to the path heterogeneity and packet losses, the occurrence of Out-of-Order (OFO) packets is inevitable for MPTCP. Although many approaches have been proposed to mitigate OFO, most of them focused on compensating path delay differences but not considered the impact of packet loss. In this paper, we take the first step towards analyzing the impact of packet loss on OFO, and propose Loss-Aware Throughput Estimation scheduler, LATE. LATE comprehensively considers each subflow's path characteristics and protocol parameters including Round Trip Time (RTT), congestion window (cwnd), and loss rate, to predict the data amount that can be sent over each subflow at a given time and determine wisely which segments should be allocated to which subflows. Experimental results show that LATE achieves a gain of 5.13% in mean goodput with long-lasting flows while reducing the completion time of short flows by about 26.68% compared to the state-of-the-art scheduler for MPTCP.

BBR-Based Congestion Control and Packet Scheduling for Bottleneck Fairness Considered Multipath TCP in Heterogeneous Wireless Networks

Aiming at improving the performance of Multipath TCP (MPTCP) in heterogeneous wireless network environments, in this paper, by taking the advantages Bottleneck Bandwidth and Round-trip propagation time (BBR) and considering bottleneck fairness, we propose BBR-based Congestion Control and Packet Scheduling scheme, called BCCPS. The proposed BCCPS first considers a BBR-based congestion control algorithm, MPTCP-BBR, for MPTCP by adaptively adjusting the sending rate of each subflow according to the real probing rate rather than the loss information to enhance the goodput while keeping bottleneck fairness with regular TCP. Then, considering that the different sending rates of the subflows in heterogeneous wireless networks will result in the problem of out-of-order (OFO) delivery, a fine-grained packet scheduling scheme is proposed to keep in-order delivery and so as to reduce the application layer completion time. The performance of the proposed scheme is evaluated via both NS-3 and real network scenarios. Experimental results show that our proposed scheme far outperforms existing MPTCP schemes in heterogeneous wireless environment.

Network adapter architectures in network on chip: comprehensive literature review

Network on Chip (NoC) is a new distributed, scalable, packet switched-based on chip which has been suggested as perfect solution for traditional centralized, non-scalable bus-based systems on chip (SoC) to handle issues like out-of order transactions, higher latencies, and end-to-end flow control. The NoC provides parallel and multi-core processing platform and is constructed from a set of Routers (R), Links (L), Intellectual Property (IP) cores, and Network Adapters (NA). The NA as individual hardware entity makes it possible IP cores with different data width and frequency connected to NoC. In other words, by decoupling computation from communication the NA allows IP Core modules and interconnects to be designed independently from each other. The design of NA impacts directly on NoC based SoCs critical parameters such as power dissipation, latency, throughput, and silicon area. This paper presents the comprehensive review of state-of-the-art architectures and the developments of NA which have been proposed in literature. Moreover, three type of parameters namely design (design goal, building components, Quality of Service (QoS), Core Interface Protocol (CIP), Security consideration, and Design for Test (DfT)), performance (power dissipation, latency, area, and throughput), and evaluation parameters (evaluation platform, clock frequency, technology scale) which have impact on NA architectures are evaluated and highlighted in comparative tables and figures. Furthermore, all the concepts that are considered in the design of NA is classified. Finally, concluding remarks and future research direction are provided.

The Effect of Real Workloads and Synthetic Workloads on the Performance of Job Scheduling for Non-Contiguous Allocation in 2D Mesh Multicomputers

The performance of non-contiguous allocation has been traditionally carried out by means of simulations based on synthetic workloads, and also it can be significantly affected by the job scheduling strategy used for determining the order in which jobs are selected for execution. To validate the performance of the non-contiguous allocation algorithms, there has been a need to evaluate the algorithm's performance based on a real workload trace. In this paper, the performance of the well-known Greedy Available Busy List (GABL) non-contiguous allocation strategy for 2D mesh-connected multicomputers is revisited considering several important job scheduling strategies based on a real workload trace, and the results are compared to those obtained from using a synthetic workload. The scheduling strategies used are the First-Come-First-Served (FCFS), Out-of-Order (OO), and Window-Based job scheduling strategies. These strategies have been selected because they are common and they have been used in related works (Ababneh & Bani-Mohammad, 2011). Extensive simulation results based on synthetic and real workload models indicate that the Window-Based job scheduling strategy can improve both overall system performance and fairness (i.e., maximum job waiting delays) by adopting a large job scheduling window. Moreover, the relative performance merits of the scheduling strategies when a real workload trace is used are in general compatible with those obtained when a synthetic workload is used.

A seamless handover scheme in IPv6-based mobile networks

With the rapid development of wireless technologies, the need to support moving hosts of IPv6-based mobile networks in ubiquitous is growing. Various well-known approaches to optimising the handover latency have been proposed in the literature: MIPv6, FMIPv6, HMIPv6 and F-HMIPv6. However, these approaches are inefficient in packet loss, out-of order problem, dependency of exact predictive information and a sudden disruption of the link. In this paper, we propose a seamless handover scheme with temporal reuse of Care of Addresses (CoAs) and Packet Buffering Point (PBP) in IPv6-Based mobile networks.

Processor Allocationand Job Scheduling on 3D Mesh Interconnection Networks

Contiguous allocation of parallel jobs usually suffers from the degrading effects of fragmentation, because it requires that the allocated processors be contiguous and have the same topology as the network topology connecting these processors. This paper suggests two non-contiguous processor allocation strategies, referred to as Paging and Greedy-Available respectively, for the 3D mesh network and compares their performance using software simulation against the well-known contiguous First Fit strategy. The comparative evaluation is conducted for two job scheduling strategies, notably first-come-first-served (FCFS) and out-of-order (OO). The results reveal that our proposed non-contiguous strategies exhibit superior performance properties despite the added contention that results from non-contiguity. The results also reveal that the scheduling and allocation strategies both have substantial effect on the performance of contiguous and non-contiguous allocation in that the OO scheduling strategy leads to much better performance than its FCFS counterpart in the 3D mesh.

Request Reordering to Enhance the Performance of Strict Consistency Models

Advances in ILP techniques enable strict consistencymodels to relax memory order through speculative execution ofmemory operations. However, ordering constraints still hinderthe performance because speculatively executed operationscannot be committed out of program order for the possibility ofmis-speculation. In this paper, we propose a new technique whichallows memory operations to be non-speculatively committed outof order without violating consistency constraints.

A 600-MHz superscalar floating-point processor

The floating-point unit of a 600-MHz, out-of order, superscalar RISC Alpha microprocessor is described. The unit achieves 59 SpecFP95 and can transfer register data at up to 9.6 GB/s. It has two independent pipelines for multiply and add/subtract operations, with iterative divide and square-root circuits, and is fabricated in a 2.2-V, 0.35-/spl mu/m CMOS process.

The MC88110 implementation of precise exceptions in a superscalar architecture

This paper describes the precise exception model of the MC88110 symmetric superscalar microprocessor. The MC88110 is a superscalar, pipelined processor that contains multiple exection units and allows out-of order execution of instructions. The MC88110 implements fully precise exceptions and presents the architecturally correct state to an exception handling routine in a manner that minimizes exception response latency. The interrupt latency timings in the MC88110 are described, and several examples of short and long latencies are provided.