Origin Of Threshold Voltage Shift Research Articles

Suppression of threshold voltage shift due to positive bias stress in GaN planar MOSFETs by post-deposition annealing

Threshold voltage instability (shift) due to positive bias stress in GaN planar-gate MOSFETs was investigated. Gate dielectric (SiO2) was formed by remote-plasma-assisted CVD on homoepitaxial Mg-doped p-type GaN layers with Si-implanted n-type source and drain regions. The threshold voltage shift of 5.8 V was observed after a stress voltage of 30 V for a sample without post-deposition annealing (PDA). The threshold voltage shift was significantly reduced to 1.4 V for a sample with PDA (800 °C for 30 min). Stress time dependences up to 6000 s were measured, revealing that the main origin of the threshold voltage shift is electron trapping into near interface traps (NITs). These results suggest that PDA is effective for the reduction of the NITs.

Origin of the improved stability under negative gate-bias illumination stress in various sputtering power fabricated ZnSnO TFTs

In this work, we report the influence of ZnSnO channel layer sputtering power in the stability of ZnSnO TFTs under negative gate-bias illumination stress (NBIS). The origin of threshold voltage shift results from combined effect of two factors between the little defect-induced trap densities originated from oxygen vacancies and better channel–insulator interface. The kinetic energy of the ions at a proper rf sputtering power is responsible for less defect-induced trap density and better channel–insulator interface. Therefore, the ZnSnO TFT fabricated at 75 W sputtering power shows a better NBIS stability. In addition, the trap density is extracted by temperature-dependent field-effect measurements and it is consistent with the change of stability under NBIS and thermal stress.

Origin of threshold voltage shift by interfacial trap density in amorphous InGaZnO thin film transistor under temperature induced stress

Effect of trap-density of amorphous InGaZnO thin film transistors (a-IGZO TFTs) were studied using different analysis of x-ray photoelectron spectroscopy (XPS) depth profile and density of states (DOSs). To change trap-densities systematically, rf-power was varied to cause different effect on the initial growth stage of a-IGZO layer grown on gate insulator. The interfacial trap-density was confirmed to be dominant effect on the performance and the threshold voltage shift of a-IGZO TFT by observing the variation of O1s binding energy from XPS. The relation between temperature stress induced and trap-density in deep level was investigated by analyzing DOSs.

Effect of channel thickness on density of states in amorphous InGaZnO thin film transistor

We report on the origin of threshold voltage shift with the thickness of amorphous InGaZnO channel layer deposited by rf magnetron sputter at room temperature, using density of states extracted from multi frequency method and falling rates of activation energy, which of trends are entirely consistent each other in respect of the reduction of total traps with increasing the channel thickness. Furthermore, we shows that the behavior of ΔVth under the positive gate bias stress and thermal stress can be explained by charge trapping mechanism based on total trap variation.

Stability of polymer thin-film transistors based on poly(2-methoxy-5-(2′-ethyl-hexyloxy)-1,4-phenylene vinylene)

Polymer thin-film transistors (PTFTs) based on poly(2-methoxy-5-(2′-ethyl-hexyloxy)-1,4-phenylene vinylene) (MEH-PPV) semiconductor are fabricated by spin-coating process and characterized. In the experiments, solution preparation, deposition and device measurements are all performed in air for large-area applications. Hysteresis effect and gate-bias stress effect are observed for the devices at room temperature. The saturation current decreases and the threshold voltage shifts toward the negative direction upon gate-bias stress, but carrier mobility hardly changes. By using quasi-static C– V analysis for MOS capacitor structure, it can be deduced that the origin of threshold-voltage shift upon negative gate-bias stress is predominantly associated with hole trapping within the SiO 2 gate dielectric near the SiO 2/MEH-PPV interface due to hot-carrier emission.