Organic Printed Circuit Board Research Articles

Concepts for realizing High-Voltage Power Modules by Embedding of SiC Semiconductors

Today’s power electronics modules typically consist of a ceramics substrate (DBC – Direct Bond Copper), carrying IGBTs, diodes or MOSFETs. These semiconductors are soldered or sintered to the ceramics and their top sides are interconnected by thick Al wires. An integration of further components or functions on the DBC substrate is difficult or even not possible. Therefore, driver circuits and controllers have to be mounted to a separate substrate, typically an organic Printed Circuit board (PCB). The PCB has to be connected to the DBC by wires or pins. The mechanical integration of the whole system requires a bulky housing. Embedding of power semiconductors like SiC MOSFET allows a significant size reduction, improved electrical performance and a high degree of reliability of such modules. In the last years, the capability of PCB embedding technology for the realization of low and high voltage power modules was demonstrated. Fraunhofer IZM together with partners from the industry demonstrated the feasibility for different applications, from single die SiC packages to high voltage automotive traction inverters. In this paper, a general overview about innovative power module technologies will be given and the embedding of power semiconductors will be introduced in detail. It will address all most relevant point, like the demands on the semiconductor, the thermal and electrical considerations as well as the demands on the used materials. To address the integration of the required driver circuits and controllers, the idea of modularization such electronics systems will also be presented. Here already packaged components will be used and embedded into PCB layers too. As a result, a modular approach to form a complete system will be developed. Different functional layers, e.g. power switches, logic modules, will be formed and finally stacked und connected to form the system. The concept and first realized demonstrators will be discussed.

Fine-pitch Copper Pillar Flip Chips in High Reliability Applications

Abstract To keep up with the demands for smaller antennas with increased performance and decreased costs, most next generation architectures mandate higher IC (integrated circuit) chip integration. Compared to conventional packaging configurations, advanced chip packaging technologies, such as 2.5D and 3D, offer greater chip compatibility and lower power consumption. Given these advantages, the adoption of advanced packaging is inevitable. Within advanced packaging, the copper pillar interconnect is a key enabling technology, and the next logical step. This technology offers several benefits, including improved electromigration resistance, improved electrical and thermal conductivity, simplified underbump metallization (UBM), and higher I/O (input/output) density. The fine pitches that copper pillars allow helps the technology to supersede solder bump technology, which reaches its lowest pitch around 40 microns. Finer pitches allow for a higher I/O count, which increases performance. In this work, assembly of ultra-thin MMIC (monolithic microwave integrated circuit) GaN (Gallium Nitride) fine-pitch copper pillar flip chip assemblies on high density interposers was successfully demonstrated. Using 150μm pitch copper pillar flip chip, the assembly processes for both organic PCB (printed circuit board) and silicon interposers were evaluated, with both an ENIG (Electroless Nickel Immersion Gold) and eutectic tin-lead solder pad finish evaluated. For the 2D/2.5D/3D assembly process development, a standard in-house pick and place tool was used, followed by mass solder reflow, finished with an underfill for reliability test. The interconnect robustness was determined by die pull strengths, a flux stamping investigation, and cross-sections. Complete reliability and qualification test data on GaN copper pillar flip chip 2D assembly was completed, including 700 temperature cycles and UHAST (unbiased highly accelerated temperature/humidity stress test).

Hybrid photonic system integration using thin glass platform technology

Demand for high integration of optoelectronic and micro-optical components into micro-electronic systems for communication, computing, medical, and sensing applications is increasing. Advanced hybrid packaging technologies are used to enhance glass-based substrates featuring electrical, thermal, and optical functionalities with laser diodes, modulators, isolators, photonic integrated circuits (PIC), beam-splitting components, and micro-lenses. Such glass-based substrates can be thin glass layers on large panels or more mini-bench-like boards that can be embedded into organic printed circuit boards (PCBs). Optical fiber interconnects, connectors, and electrical–optical integration platforms are used for higher level system integration and need to be miniaturized on module and board level to fulfill decreasing channel pitch requirements. We provide background on and discuss thin glass as a suitable base material for ion exchanged waveguide panels and interposers, precise glass structuring for posts and holders, the related high precision assembly techniques, and advanced fiber interconnects. Some examples of PCB photonic integration, micro-bench optical sub-assemblies, including PIC, and 3D optical resonator packages that combine most of these approaches will be shown.

A Fully Integrated 384-Element, 16-Tile, $W$ -Band Phased Array With Self-Alignment and Self-Test

This paper describes the design and implementation of a scalable $W$ -band phased-array system, with built-in self-alignment and self-test, based on an RFIC transceiver chipset manufactured in the TowerJazz 0.18- $\mu \text{m}$ SiGe BiCMOS technology with $f_{T}/f_{\text {MAX}}$ of 240/270 GHz. The RFIC integrates 24 phase-shifter elements (16TX/8RX or 8TX/16RX) as well as direct up- and down-converters, phase-locked loop with prime-ratio frequency multiplier, analog baseband, beam lookup memory, and diagnostic circuits for performance monitoring. Two organic printed circuit board (PCB) interposers with integrated antenna sub-arrays are designed and co-assembled with the RFIC chipsets to produce a scalable phased-array tile. Tiles are phase-aligned to one another through a daisy-chained local oscillator (LO) synchronization signal. Statistical analysis of the effects of LO misalignment between tiles on beam patterns is presented. Sixteen tiles are combined onto a carrier PCB to create a 384-element (256TX/128RX) phased-array system. A maximum saturated effective isotropic radiated power (EIRP) of 60 dBm (1 kW) is measured at boresight for the 256 transmit elements. Wireless links operating at 90.7 GHz using a 16-QAM constellation at a reduced EIRP of 52 dBm produced data rates beyond 10 Gb/s for an equivalent link distance in excess of 250 m.

A 16-Element W-Band Phased-Array Transceiver Chipset With Flip-Chip PCB Integrated Antennas for Multi-Gigabit Wireless Data Links

This paper describes the design and implementation of a W-band phased-array system with printed circuit board (PCB) integrated antennas in two polarizations capable of multi-gigabit spectrally efficient wireless communication. The chipset is manufactured in a 0.18-μm SiGe BiCMOS technology with f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</sub> of 240-/270-GHz and is flip-chipped onto a lowcost organic PCB with integrated antenna arrays. Each chip is equipped with 16-transmit/4-receive or 16-receive/4-transmit calibrated phase shifter elements and direct upand downconverters plus a half-rate phase-locked loop. The different system tradeoffs required to establish a multi-Gb/s wireless link at millimeter waves are carefully studied. Built-in element failure detectors, power detectors, and digital interface enable factory calibration and self-test capability. Each transceiver chip operates from 1.5and 2.5-V supplies and consumes 5.5 and 4.5 W in transmit and receive mode, respectively. The peak transmitter effective isotropic radiation power is 34 dBm in each polarization with a measured receiver noise figure of 6.5 dB at 94 GHz. At a distance of 1 m, a maximum wireless data rate of 30 Gb/s (per polarization) using 64-QAM can be achieved and at 20 m, 8 Gb/s (dual polarization) can be established using QPSK modulation.

Improvement of Thermo-Mechanical Reliability of Wafer-Level Chip Scale Packaging

Due to low cost and good electrical performance, wafer-level chip scale packaging (WLCSP) has gained more attention in both industry and academia. However, because the coefficient of thermal expansion (CTE) mismatches between silicon and organic printed circuit board (PCB), WLCSP technology still faces reliability challenges, such as the solder joint fragile life issue. In this paper, a new WLCSP design (WLCSP-PN) is proposed, based on the structure of WLCSP with Cu posts (WLCSP-P), to release the stress on the solder joints. In the new design, there is a space between the Cu post and the polymer which permits NiSn coating on the post sidewall. The overcoating enhances the solder–post interface where cracks were initiated and enlarges the intermetallic compounds (IMC) joint area to enhance the adhesion strength. Design of experiment (DOE) with the Taguchi method is adopted to obtain the sensitivity information of design parameters of the new design by the three-dimensional (3D) finite element model (FEM), leading to the optimized configuration. The finite element analysis results demonstrate that compared to WLCSP-P, the proposed WLCSP-PN reduces the package displacement, equivalent stress, and plastic strain energy density and thus improves the fatigue life of solder joints.

Hygrothermal aging of flip-chip assembled MOEMS

Low cost and miniaturized solutions for assembly of optical microelectromechanical systems (MOEMS) are critical for increased exploitation of optical sensors and devices in consumer applications. Examples of applications based on optical sensors and devices already near or on the market are auto-focus lenses and pico-projectors for mobile phones, physiology measurement units for wearables, and high bandwidth free-space optical communication links for our homes. In addition, extensive use of photonic integrated circuits is predicted to be mandatory in order to answer to the future needs for high data transfer rates in data centers. However, the main limitation for several of these applications is the complexity, the related cost of assembly, and the unknown reliability of several lower cost assembly solutions; polymer-based solutions are e.g. prone to fail particularly fast in humid and warm conditions. In this work, a part of a European project called Lab4MEMS II, we study the feasibility of reducing the footprint, complexity and cost of assembly of silicon micro-machined mirrors directly to organic printed circuit boards, without jeopardizing the reliability of the system. We demonstrate flip-chip assembly using novel isotropic conductive adhesives (ICAs) with a particularly low content of silver that earlier indicated stable behaviour during exposure to hygrothermal aging [1]. The new solution removes the earlier needed space around the component for wire bonds, and the assembly is simplified as electrical and mechanical joints are formed in a single step. Dummy mirrors were designed with two different pad layouts that were either optimized for a large pitch (the pads are distributed evenly around the active area) or for mechanical compliance (the pads are concentrated into three groups that are oriented in a triangle). There are 12 pads in total for each design. The outer dimension of the dies is 7 x 7 mm and the diameter of the region reserved for an active area is 5 mm. The dummy samples represent mirrors that are controllable through the inclusion of a 2 Âμm lead zirconate titanate (PZT) piezo-electrical thin film. The PZT film and the bottom (Ti/Pt) and top (TiW/Au) electrode layers are included in the dummy samples for a good representation of the actual surfaces to be bonded, both their materials and their topography. A 100 nm layer of alumina was deposited for passivation. The passivation layer was opened in the contact holes by wet etching. The layout includes both Kelvin structures and daisy chains. A commercially available and widely used ICA, Epotek H20E, was selected as a reference material for two novel ICAs, Mosaic A and Mosaic B. The Epotek material contains solid Ag particles whereas the Mosaic materials contain metal coated polymer spheres with a diameter of 10 Âμm and a Ag layer coating of 140 nm. The ICAs were stencil printed onto boards having ENIG surface finish. The dummy mirror dies were flipped and aligned, and bonded by applying a tool pressure corresponding to 9 MPa as calculated based on the nominal contact hole areas. Curing was performed for one or two hours at 150 °C, depending on the recommendations from the material providers. A total of 14 boards, with 6 dummy mirrors bonded onto each, were assembled for characterization and reliability testing. The assemblies are presently measured electrically in-situ as they are exposed to hygrothermal aging. The humidity level is 85% RH in all tests, whereas the temperature is either 65, 75 or 85 °C to enable recording of lifetime distribution curves at three different temperature loads. No failures have occurred yet, illustrating already the high potential of this assembly solution, but all samples will be run to failure. Curve fitting will be used to identify distribution functions to enable lifetime predictions, but the failures will be analysed using cross-sectioning, light microscopy and scanning electron microscopy, to identify failure modes and thereby verify the correctness of accelerated testing.

High-Temperature Storage Testing of ACF Attached Sensor Structures.

Several electronic applications must withstand elevated temperatures during their lifetime. Materials and packages for use in high temperatures have been designed, but they are often very expensive, have limited compatibility with materials, structures, and processing techniques, and are less readily available than traditional materials. Thus, there is an increasing interest in using low-cost polymer materials in high temperature applications. This paper studies the performance and reliability of sensor structures attached with anisotropically conductive adhesive film (ACF) on two different organic printed circuit board (PCB) materials: FR-4 and Rogers. The test samples were aged at 200 °C and 240 °C and monitored electrically during the test. Material characterization techniques were also used to analyze the behavior of the materials. Rogers PCB was observed to be more stable at high temperatures in spite of degradation observed, especially during the first 120 h of aging. The electrical reliability was very good with Rogers. At 200 °C, the failures occurred after 2000 h of testing, and even at 240 °C the interconnections were functional for 400 h. The study indicates that, even though these ACFs were not designed for use in high temperatures, with stable PCB material they are promising interconnection materials at elevated temperatures, especially at 200 °C. However, the fragility of the structure due to material degradation may cause reliability problems in long-term high temperature exposure.

고온고습 전압인가(Biased HAST) 시험에서 인쇄회로기판의 이온 마이그레이션 불량 메커니즘

By the trends of electronic package to be smaller, thinner and more integrative, organic printed circuit board is required to be finer Cu trace pitch. This paper reports on a study of failure mechanism for PCB with fine Cu trace pitch using biased HAST. In weibull analysis of the biased HAST lifetime, it is found that the acceleration factor (AF) of between 135 o C/90%RH/3.3V and 130 o C/85%RH/3.3V is 2.079. A focused ion beam (FIB) was used to polish the cross sections to reveal details of the microstructure of the failure mode. It is found that CuxO/Cu(OH)2 colloids and Cu dendrites were formed at anode (+) and at cathode (�), respectively. Thus, this gives the evidence that Cu dendrites formed at cathode by Cu 2+ ion migration lead to a short failure between a pair of Cu nets.

Future paper based printed circuit boards for green electronics: fabrication and life cycle assessment

A multilayer printed circuit board (PCB) can be fabricated using commercially available printing paper, which shows comparable functionalities with the conventional organic PCBs but 100 times lower environmental impact.

Characterization of Compressive Die Stresses in CBGA Microprocessor Packaging Due to Component Assembly and Heat Sink Clamping

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials (TIMs), second level ceramic ball grid array (CBGA) solder joints, organic printed circuit board, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high coefficient of thermal expansion (CTE) ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, test chips containing piezoresistive stress sensors have been used to measure the buildup of mechanical stresses in a microprocessor die after various steps of the flip chip CBGA assembly process. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state at each sensor site being monitored by the data acquisition hardware. Special test fixtures were developed to eliminate any additional stresses due to clamping effects. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, and lid attachment). The experimental observations from this study show clearly that large area array flip chips are subjected to relatively large compressive in-plane normal stresses after solder reflow. We also observed that the majority of the die compressive stress is accumulated during the underfilling assembly step. Typical increases in the stress magnitude were on the order of 300% (relative to the stresses due to solder joint reflow only). As a general “rule of thumb,” approximately two-thirds (∼66%) of the final die stress magnitudes were observed to be developed during the underfill dispense and cure, with the second largest contribution coming from the die attachment, and the smallest contribution coming from lid attachment. The experimental test chip stress measurements were correlated with finite element simulations of the packaging process. A sequential modeling approach has been utilized to predict the build-up of compressive stress. The utilized method incorporates precise thermal histories of the packaging process, element creation, and nonlinear temperature and time dependent material properties. With suitable detail in the models, excellent correlation has been obtained with the sensor data throughout all packaging processes. Finally, CBGAs with the stress sensing chips were soldered to organic printed circuit board (PCB) test boards. A simulated heat sink loading applied, and the stresses were measured as a function of the clamping force. Compressive stress changes of up to − 60 MPa were observed for a 1000 N applied clamping force. The experimental test chip stress measurements were correlated with finite element simulations of the clamping process. With suitable detail in the models, excellent correlation has been obtained for the stress changes occurring during simulated heat sink clamping.

Pressure leaching of metals from waste printed circuit boards using sulfuric acid

Printed circuit boards (PCBs) are essential components of electronic equipments which contain various metallic values. This paper reports a hydrometallurgical recycling process for waste PCBs, which consists of the novel pretreatment consisting of organic swelling of PCBs followed by sulfuric acid leaching of metals from waste PCBs. To recycle the waste PCBs, experiments were carried out for the recovery of copper from the crushed and organic swelled materials of waste PCBs using sulfuric acid leaching in presence of hydrogen peroxide under atmospheric and pressure condition. The leaching of PCBs at 90°C, pulp density 100 g/L under atmospheric condition, using 6M sulfuric acid resulted in the dissolution of a minor amount of copper due to the presence of plastic coating on the surface of metallic layers. On the other hand, when the liberated metal sheets from organic swelled PCBs were treated with dilute sulfuric acid of concentration 2M along with hydrogen peroxide in an autoclave under oxygen atmosphere, the percentage recovery of copper was found to increase from 59.63% to 97.01% with an increase in hydrogen peroxide concentration from 5 to 15% (v/v) keeping constant pulp density 30 g/L.

Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs

Micro-springs for integrated circuit test and packaging are demonstrated as soldered flip chip interconnects in a direct die to printed circuit board package. The spring interconnects are fabricated with thin film metallization as the last step in a wafer-scale process. The z-compliance of the interconnects can be used to test and/or burn-in parts in wafer form. After the parts are diced from the wafer, the springs then become the first-level (and often the last-level) interconnect between the chip and the board. The xy-compliance of the interconnect enables considerably large die to be soldered to an organic printed circuit board without underfill using a surface mount compatible process. To demonstrate this concept, daisy chain test vehicles were fabricated on die measuring 11.5 mm times 6.5 mm with 48 spring contacts on a 0.8 mm times 0.65 mm grid array, each spring measuring 400 mum times 100 mum. The parts were placed onto organic boards with screen printed solder paste using a pick and place machine. The parts were reflowed to complete the solder connection to each spring using eutectic and lead-free solder. Assembled parts have undergone >20 000 hot plate thermal cycles and >1000 oven thermal cycles without failure.

A Study on the Thermal Reliability of Cu/SnAg Double-Bump Flip-Chip Assemblies on Organic Substrates

The Cu/SnAg double-bump structure is a promising candidate for fine-pitch flip-chip applications. In this study, the interfacial reactions of Cu (60 μm)/SnAg (20 μm) double-bump flip chip assemblies with a 100 μm pitch were investigated. Two types of thermal treatments, multiple reflows and thermal aging, were performed to evaluate the thermal reliability of Cu/SnAg flip-chip assemblies on organic printed circuit boards (PCBs). After these thermal treatments, the resulting intermetallic compounds (IMCs) were identified with scanning electron microscopy (SEM), and the contact resistance was measured using a daisy-chain and a four-point Kelvin structure. Several types of intermetallic compounds form at the Cu column/SnAg solder interface and the SnAg solder/Ni pad interface. In the case of flip-chip samples reflowed at 250°C and 280°C, Cu 6 Sn 5 and (Cu, Ni) 6 Sn 5 IMCs were found at the Cu/SnAg and SnAg/Ni interfaces, respectively. In addition, an abnormal Ag 3 Sn phase was detected inside the SnAg solder. However, no changes were found in the electrical contact resistance in spite of severe IMC formation in the SnAg solder after five reflows. In thermally aged flip-chip samples, Cu 6 Sn 5 and Cu 3 Sn IMCs were found at the Cu/SnAg interface, and (Cu, Ni) 6 Sn 5 IMCs were found at the SnAg/Ni interface. However, Ag 3 Sn IMCs were not observed, even for longer aging times and higher temperatures. The growth of Cu 3 Sn IMCs at the Cu/SnAg interface was found to lead to the formation of Kirkendall voids inside the Cu 3 Sn IMCs and linked voids within the Cu 3 Sn/Cu column interfaces. These voids became more evident when the aging time and temperature increased. The contact resistance was found to be nearly unchanged after 2000 h at 125°C, but increases slightly at 150°C, and a number of Cu/SnAg joints failed after 2000 h. This failure was caused by a reduction in the contact area due to the formation of Kirkendall and linked voids at the Cu column/Cu 3 Sn IMC interface.

A Novel Design Structure for WLCSP With High Reliability, Low Cost, and Ease of Fabrication

Wafer level chip scale packaging (WLCSP) has some advantages, such as real die size packaging, high electrical performance, and low manufacturing cost. However, because the mechanical reliability of a large die can not be guaranteed due to the coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB), WLCSP technology is still not fully accepted. We have developed a new solder joint protection-WLCSP (SJP-WLCSP) structure with a delamination layer interposed between the top layer of the chip and the bottom insulating layer of the metal redistribution traces. The stress on the solder joints can be released by the cracks forming in the delamination layer, which protects the solder joints from cracking. Since the cracking of the delamination layer is irrelevant to the electrical circuits of the packaging, the packaged integrated circuits (IC) device remains functional. One of the possibilities for processing the SJP-WLCSP was implemented and validated successfully in the SiLK-wafer samples. The board level packaging samples, using the daisy chain resistance measurement passed 1000 cycles of the temperature cycling testing.

A novel crack and delamination protection mechanism for a WLCSP using soft joint technology

PurposeThe coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB) materials causes a reliability issue for ball grid array type electronic packages. This makes it difficult for conventional wafer level chip scaled packaging (WLCSP) with large die to satisfy the reliability requirements. Therefore, in this study a novel solder joint protection‐WLCSP (SJP‐WLCSP) structure is proposed to overcome the reliability issue.Design/methodology/approachThe SJP‐WLCSP makes use of a delaminating layer to reduce the problem of CTE mismatch. In the SJP‐WLCSP, a delaminating layer is interposed between the top layer of the chip and the bottom insulating layer of the redistribution copper metal traces. As a result, the stress on the solder joints can be released by allowing cracks to form in the delaminating layer.FindingsTo elucidate the thermo‐mechanical behaviour of tin‐lead eutectic solder joints and copper traces, a non‐linear analysis, based on a 3D finite element (FE) model, under accelerated thermal test loadings was carried out. The maximum equivalent stress/strain in the solder joints predicted by the FE simulation were found to diminish significantly when applying the delaminating layer. In addition, parametric FE analysis was also applied in this study, and based on the design concepts within this study, a robust novel SJP‐WLCSP could be achieved.Originality/valueIn this work, a new packaging concept with high reliability, low cost and easy fabrication was developed to reduce the shear stress in the solder joints due to the CTE mismatch between silicon chips and organic PCBs.

Reducing bonding cycle time of adhesive flip chip process

Flip chip assembly using anisotropic conductive adhesives offers an interesting alternative for making high‐density interconnections. The use of conventional organic printed circuit boards makes this technique even more attractive. However, a low‐cost adhesive flip chip bonding process will require a reduced bonding cycle time or the use of multi‐head joining equipment. Adhesive flip chip bonding is characterized by a long bonding cycle time due to the relatively long curing time of adhesives and the need for simultaneous application of pressure during the curing process. In soldered flip chip techniques, the bonding time per assembly is shorter, because all the chips on the substrate can be soldered in a reflow oven at the same time. In this study, the minimum pre‐curing time needed to make a reliable adhesive joint was determined using one commercial anisotropic conductive adhesive film used on FR‐4 substrates. The results are promising, since bonding time reduction from 40 s to 10 s does not reduce the joint reliability.

Effects of metallization characteristics on gold wire bondability of organic printed circuit boards

Organic printed circuit boards (PCBs) with Au/Ni plates on bond pads are widely used in chip-on-board (COB), ball grid array (BGA), and chip-scale packages. These packages are interconnected using thermosonic gold wire bonding. The wire bond yield relies on the bondability of the Ni/Au pads. Several metallization parameters, including elemental composition, thickness, hardness, roughness, and surface contamination, affect the success of the solid state joining process. In this study, various characterization and mechanical testing techniques are employed to evaluate these parameters for different metallization schemes with varying Ni and Au layer thicknesses. The pull force of Au wires is measured as a function of plasma treatment applied before wire bonding to clean the bond pads. Close correlations are established between metallization characteristics and wire bond quality.

Reworkable no-flow underfills for flip chip applications

Underfill is a polymeric material used in the flip-chip devices that fills the gap between the integrated circuit (IC) chip and the substrate (especially on the organic printed circuit board), and encapsulates the solder interconnects. This underfill can dramatically enhance the reliability of the flip-chip devices as compared to the nonunderfilled devices. No-flow (compress-flow) underfill is a new type of underfill that allows simultaneous solder bump reflow and underfill cure, which leads to a more efficient no-flow underfilling process as compared to the standard capillary-flow underfilling process. Reworkable underfill is another type of underfill that allows the faulty chips to be replaced individually. It is the key material to address the nonreworkability issue of the current flip-chip devices. Reworkability is especially important to the no-flow underfill because electrical test of the assembled chips can only be done at the end of the no-flow underfilling process. The goal of this study is to demonstrate the feasibility of a no-flow reworkable underfill. Two approaches are taken to develop this new type of underfill. The first one is to add a special additive into a standard no-flow underfill formulation (underfill 0) to make it reworkable, called underfill 1. The second approach is to develop a no-flow underfill based on a new thermally degradable epoxy resin that decomposes around 240/spl deg/C, called underfill 2. Comparing to underfill 0, these two underfills have similar properties including glass transition temperature (T/sub g/), coefficient of thermal expansion (CTE) and modulus. Underfill 1 has similar curing and fluxing capability as underfill 0. Underfill 2 cures faster than underfill 0, and it has slightly weaker fluxing capability than underfill 0, but it still allows 100% of solder bumps wetting and collapsing on the copper board. Moreover, underfill 1 and underfill 2 allow the flip chips to be reworked using a developed rework process while underfill 0 does not.

The importance of material selection for flip chip on board assemblies

Flip Chip On Board (FCOB) technology, where the unpackaged silicon chip is assembled directly to an organic substrate, provides an unique interconnect structure that significantly reduces the substrate area required by traditional through hole or surface mount integrated circuit packages. Without the protection for the chip that a package body affords however, reduced mechanical robustness and a decrease in reliability performance are potential concerns. In addition, the inherent thermal mismatch between the chip and substrate, particularly with an organic printed circuit board, will produce an accumulation of stress in the solder joints under normal operating conditions that can result in relatively premature failures due to solder fatigue. Coupling the chip and substrate together with an encapsulation material under the chip face has successfully overcome these mechanical and reliability issues. However, the success of the encapsulation is dependent on many factors. Among these are the encapsulant's material properties, and the compatibility with the chip and substrate surfaces. Thus, the selection of the basic materials to be used in the FCOB assembly are interrelated and critical to achieving the desired performance from the completed assembly. This paper highlights the key considerations involved in the identification of suitable materials for each of the basic constituent elements: printed circuit board (PCB), silicon chip and encapsulation material.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>