Organic Circuit Board Research Articles

Reliability of plastic-encapsulated electronic components in supersaturated steam environments

Medical steam sterilizers use rapid cycles of temperature, humidity, and pressure to sterilize medical instruments. These cycles represent an exceptionally harsh environment for electronics and, currently, only metal can devices with high-reliability electronic components can be used to electronically monitor and verify the completeness of sterilization. The work presented in this paper has allowed the identification of a material set that allows plastic-encapsulated electronic modules with commercial-off-the-shelf electronic components and sensors, assembled on organic circuit boards, to survive over 100 sterilization cycles. In the course of the work, the failure mechanisms of the plastic-encapsulated modules and the deterioration of encapsulant adhesion over multiple sterilization cycles have been characterized. This opens the possibility of using plastic-encapsulated embedded electronics in smart medical and biomedical devices, which need resterilization after every use.

Analysis of Dynamic Moisture Diffusion in Packaging Materials During Steam Sterilization

We present a model, verified by experiment, for predicting the moisture absorption and desorption of a range of plastic encapsulant and organic circuit board materials under both nonsaturated and supersaturated steam conditions. This paper was carried out as part of the development of embedded plastic-encapsulated modules (PEMs) for monitoring the internal atmosphere parameters of medical steam sterilizers (autoclaves). The rapid cycles of temperature, pressure, and humidity that are a feature of autoclave operation present unique challenges for the reliability of embedded PEMs. Analysis of moisture absorption and desorption in candidate encapsulant and circuit board materials was, therefore, required for prediction of both moisture ingress and of hygroscopic swelling. This analysis was carried out at three different temperature/humidity/pressure levels (85 °C/85%RH/atmospheric, 121 °C/100%RH/2 bar, and 134 °C/100%RH/3 bar), while desorption was analyzed at both ambient temperature/pressure and in a vacuum oven (0.6 and 0.3 bar) at 85 °C, 121 °C, and 134 °C. Interval weighing was used to monitor the moisture diffusion in the samples and to identify when saturation/desiccation was reached. The moisture diffusion coefficients and the saturated moisture concentrations of the materials were extracted from the test results and a model, verified by experiment, was developed to predict these values for any temperature and humidity combination between 85 °C/85%RH and 134 °C/100%RH. Measurements of hygroscopic swelling were also carried out as part of the analysis. This is believed to be the first detailed analysis of moisture diffusion in these types of materials over this range of parameters.

Packaging technologies for high temperature control electronics

Current low temperature electronics (<175°C) with logical functions (CPUs, MCUs) have exceptional levels of reliability in terms of packaging, stemming from decades of research. However, electronics that operate at higher temperatures (>175°C) for prolonged periods of time require packaging technologies that have to tackle many new problems. At high temperatures traditionally used materials such as organic circuit boards, adhesives and standard solders degrade rapidly or undergo changes in structure and properties. An even more critical issue than high-temperature survivability is resistance to temperature cycling. Thermal mismatch between organic boards and semiconductor dies leads to high thermomechanical strains during swings from high to low temperature extremes, which can make an otherwise high temperature resistant assembly fail after a relatively low number of cycles. This work focuses on the packaging technologies for high temperature control modules, those with logical and signal conditioning applications. Although control modules share many similarities with power modules, they present their own unique design challenges, such as significantly higher complexity and a limitation of compatible materials. Here, recent research on substrates, die attach technologies and wirebond interconnects suited for high temperature ICs are presented along with packaging technologies for discrete components (capacitors and resistors) with the aim of identifying the current best solutions. Test vehicles for the various technologies were constructed and were subjected to high temperature storage at temperatures higher than 200°C. They were analysed in terms of degradation (i.e. loss in shear strength, pull strength, change in resistance, etc.). In parallel, a separate set of samples were subjected to temperature cycles from −20°C to 180°C and then analysed using the same tests as before for comparison. The combined data allow a recommendation to be made on how to assemble a viable control module such as one based on an SOI microcontroller designed at EPFL to operate at high temperatures.

Long-term stability of Ag and Cu thin films on glass, LTCC and alumina substrates

Silver (Ag) and copper (Cu) are regarded as advanced material for metallization systems in microelectronic devices because of their high electrical conductivity and enhanced electromigration resistance. Typically, organic circuit boards as well as ceramic and glass–ceramic substrates use galvanic deposited Cu films or screen-printed metallization for this purpose. When applying the latter approach, however, the lateral resolution in the μm-region being required e.g. for novel high frequency applications can not be guaranteed. Hence, sputter deposition is envisaged for the realization of thin film metallization systems. The reliability of 300 nm thick Cu and Ag thin films is comparatively investigated under accelerated aging conditions, utilizing a test structure which consists of parallel lines stressed with current densities up to 2.5 × 106 A cm−² at temperatures up to 300°C on Si/SiO2, glass, LTCC (low temperature co-fired ceramics) and alumina substrates. To detect the degradation via the temporal characteristics of the current signal a constant voltage is applied according to the overall resistance of the test structure. Knowing the mean time to failure (MTF) and the activation energy at elevated temperatures conclusions on the migration mechanism can be drawn. Whereas on LTCC substrates the activation energy Ea is about 0.75 eV for both Ag and Cu thin films, the higher activation energies of about Ea ~ 1 eV measured for Cu on glass and alumina indicate a suppression of back diffusion especially at enhanced temperature levels. This effect is predominantly caused by a stable oxide layer which is formed at high temperatures and which acts as passivation layer. Therefore, the overall electromigration resistance is lower compared to Ag.

A Single-Chip CMOS-Based Parallel Optical Transceiver Capable of 240-Gb/s Bidirectional Data Rates

We report here on the design, fabrication, and high-speed performance of a parallel optical transceiver based on a single CMOS amplifier chip incorporating 16 transmitter and 16 receiver channels. The optical interfaces to the chip are provided by 16-channel photodiode (PD) and VCSEL arrays that are directly flip-chip soldered to the CMOS IC. The substrate emitting/illuminated VCSEL/PD arrays operate at 985 nm and include integrated lenses. The complete transceivers are low-cost, low-profile, highly integrated assemblies that are compatible with conventional chip packaging technology such as direct flip-chip soldering to organic circuit boards. In addition, the packaging approach, dense hybrid integration, readily scales to higher channel counts, supporting future massively parallel optical data buses. All transmitter and receiver channels operate at speeds up to 15 Gb/s for an aggregate bidirectional data rate of 240 Gb/s. Interchannel crosstalk was extensively characterized and the dominant source was found to be between receiver channels, with a maximum sensitivity penalty of 1 dB measured at 10 Gb/s for a victim channel completely surrounded by active aggressor channels. The transceiver measures 3.25times5.25 mm and consumes 2.15 W of power with all channels fully operational. The per-bit power consumption is as low as 9 mW/Gb/s, and this is the first single-chip optical transceiver capable of channel rates in excess of 10 Gb/s. The area efficiency of 14 Gb/s/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> per link is the highest ever reported for any parallel optical transmitter, receiver, or transceiver reported to-date.

Warpage-induced lithographic limitations of FR-4 and the need for novel board materials for future microvia and global interconnect needs

The effect of warpage on lithographic capabilities of organic circuit boards with multilayered thin film buildup was investigated. Two to six epoxy layers were built on various candidate boards to characterize the warpage and correlate it with analytical models. Underlying mechanisms were investigated and novel parameters defined to correlate warpage with photodefinition of ultrafine lines and vias on the board. Based on the experiments, warpage specifications for the multifunctional multilayered requirements in a proposed system-on-package (SOP) structure were defined. Experimentally validated FEM models were used to estimate the warpage during the multilayered buildup. Results show that FR-4 is not suitable for future high-density packaging needs and underscore the need for stiffer ceramic-based circuit board materials as replacement for FR-4