Order Sigma-delta Modulator Research Articles

Design and Implementation of Decimation Filter for 13-bit Sigma-Delta ADC Based on FPGA

A 13 bit Sigma-Delta ADC for a signal band of 40K Hz is designed in MATLAB Simulink and then implemented using Xilinx system generator tool. The first order Sigma-Delta modulator is designed to work at a signal band of 40 KHz at an oversampling ratio (OSR) of 256 with a sampling frequency of 20.48 MHz. The proposed decimation filter design is consists of a second order Cascaded Integrator Comb filter (CIC) followed by two finite impulse response (FIR) filters. This architecture reduces the need for multiplication which is need very large area. This architecture implements a decimation ratio of 256 and allows a maximum resolution of 13 bits in the output of the filter. The decimation filter was designed and tested in Xilinx system generator tool which reduces the design cycle by directly generating efficient VHDL code. The results obtained show that the overall Sigma-Delta ADC is able to achieve an ENOB (Effective Number Of Bit) of 13.71 bits and SNR of 84.3 dB.

Digital Sine Oscillators Based on Higher Order Sigma–Delta Modulation

In this paper, a new class of digital sine oscillators based on higher-order multibit sigma-delta modulation is presented. The samples of a given pure sine signal are quantized, resulting in a pulse-code modulated (PCM) sequence. A numeric condition for oscillation (NCO) based on the PCM signal is disclosed. If the NCO is fulfilled, a system constant <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</i> with a finite bit width can be derived and a hardware-efficient practical realization of a digital oscillator based on <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> -order sigma-delta modulation is possible. The oscillator output sequence is an <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> -times differentiated version of the PCM signal and thus the PCM signal can be reconstructed by <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> -subsequent accumulations. All signals are absolutely periodic and are represented by binary numbers with well-defined finite bit widths. Initial conditions for the registers of the oscillator are determined. An example for the generation of a high-purity PCM signal with 2048 samples per period is demonstrated. The noise spectrum of this signal is white and the ratio between the mean noise amplitude and the signal amplitude is about one over one billion. The resulting oscillator requires a third order sigma-delta modulator. The chip size is estimated for the oscillator being integrated in a commonly used CMOS technology.

A low-power CT 2nd order Delta Sigma modulator using a new design methodology for biomedical applications

This paper presents a low-power second-order continuous-time (CT) Delta-Sigma Modulator (DSM) using a new design methodology for biomedical applications. The proposed design methodology first implements a target block with the highest power consumption at a transistor level before optimizing the DSM coefficients. We are also able to reduce the area usage by appropriate limitations on the DSM range in the proposed design process. The DSM was implemented using the genetic algorithm (GA) and appropriate chopping techniques in our design process. The design was implemented in 0.18um CMOS technology by using a 0.083 mm2 layout, with a maximum SNDR and dynamic range of 94.28 and 100 dB, respectively, for a 2 kHz bandwidth and 32.34uW power consumption.

Low-Noise Readout Circuit for an Automotive MEMS Accelerometer

This paper presents a charge-balanced readout circuit for MEMS capacitive accelerometers. The focus of this work is a design with a low-noise and low area consumption while ensuring the essential linearity and electromagnetic compatibility (EMC) for automotive applications. The readout circuit is composed of a charge-balanced single-ended input C/V stage followed by a second order sigma-delta modulator. The C/V stage uses a Gm stage combined with an integrator to reduce its noise contribution. The measurement results of the readout circuit show a noise floor of 62 $\mu g/{\sqrt {\mathrm{ Hz}}}$ and a temperature dependent offset smaller than ±0.6 mg after compensation. The measured dynamic range of the complete interface, including readout circuit and sensor, is 95.5 dB. The measured EMC is below 2 mg. The accelerometer readout circuit has been designed in a 130nm technology. Its power and area consumption is 1.4 mW and 0.26mm2.

Sigma-Delta ADC on SOI Technology for Working at High Temperatures

We consider the integrated circuit design and the measurement results of test crystals for the 12-bit sigma-delta analog-to-digital converter (ADC) based on 180 nm silicon-on-insulator (SOI) technology from X-FAB. The ADC processes input signals in the frequency range up to 100 kHz in the temperature range of –40…+175 °C with the supply voltage equal to 3.3 V and the modulator clock frequency equal to 10 MHz. The circuit consists of the 5-th order switched-capacitor low-pass pre-filter to limit the input signal spectrum, the cascade connection of the second order sigma-delta modulators, and the digital decimation filter to reduce the clock frequency by 48 times. The main blocks of cutoff filter and modulator are assembled according to the balanced scheme on integrators based on operational transconductance amplifiers with the unity gain bandwidth of 63 MHz. The dynamic element matching circuit is used to expand the dynamic range of converter. It reduces the level of nonlinear distortions in digital-to-analog converters in the feedback circuits of modulator. The value of the SINAD parameter is not worse than 68 dB for converting the signal with the differential amplitude equal to 500 mV at the frequency of 100 kHz.

36 μW fourth order sigma-delta modulator using single operational amplifier

ABSTRACT This paper presents a single loop fourth-order Discrete-Time Sigma-Delta Modulator (ΣΔM) using single Operational Amplifier (Op-Amp). Proposed ΣΔM utilises delay-based discrete-time integrators and an Op-Amp to implement all the integrators. Op-Amp reuse helps in saving power. A switched-capacitor based proposed design is simulated in standard 180 nm CMOS technology with an effective resolution of 12.04 bits. The proposed ΣΔM achieves a Signal to Noise Distortion Ratio (SNDR) of 74.24 dB with 78 dB of Dynamic Range (DR). An input signal of −4 dBFS magnitudes and 1.125 kHz of frequency is sampled at a sampling frequency of 320 kHz. The proposed circuit is designed for 10 kHz Bandwidth (BW) with Oversampling Ratio (OSR) of 16. The proposed modulator achieves Figure-of-Merit (FOM) of 158.68 dB/0.427 (pJ/conversion-step) with a total power consumption of 36 µW at 1.8 V supply voltage. The layout area of the proposed circuit is 134 µm ×134 µm.

A DROIC Based on PFM ADCs Employing Over-Integration for Error Shaping

This paper presents a digital readout integrated circuit (DROIC) for small pitch medium-wave infrared (MWIR) starring focal plane arrays (FPAs). To overcome the limited in-pixel resolution of such DROICs, the concept of error shaping is introduced in pulse frequency modulation (PFM)-based pixels. Multiple integration operations are performed in a single frame and the residue charge from each integration phase is retained and injected into the next charge packet. This over-integration routine provides a high pass noise transfer function (NTF) equivalent to what is obtained in a first order sigma delta modulator. The concise structure of a PFM analog-to-digital converter (ADC) lends itself well to such an operation inside the pixel, while consuming low power. Along with a theoretical analysis of the technique, a prototype based on a $16\times 16$ array and sinc decimation filters is developed to demonstrate the performance of the proposed DROIC. With an in-pixel resolution of 5 bits and over-integration ratio (OIR) of 128, 395 noise electrons are demonstrated at full-well fill from the test array fabricated in a 90 nm bulk-CMOS process.

Experimental characterization of Sigma Delta Radio over fiber system for 5G C-RAN downlink

Abstract Radio over Fiber is a promising technology for the 5G Cloud Radio Access Network. We demonstrate experimentally Sigma Delta Radio over Fiber by means of Sigma Delta Modulator (SDM) subsequently replacing expensive digital to analog converters. A second order SDM is proposed for LTE 20 MHz signal having 256 QAM modulation on a carrier frequency of 3.5 GHz for 10 Km of fiber length. The performance is reported in terms of error vector magnitude, adjacent channel leakage ratio and eye-opening penalty. The results show that the proposed architecture performance is cost and power efficient solution for next-generation wireless networks.

A Fractional-Order Noise-Shaping Integrator for Sigma-Delta Modulator

A novel fractional-order Sigma-Delta modulator, which can improve the signal to noise ratio (SNR) and is of robust stability of a high order Sigma-Delta modulator, is presented in the paper. Traditional Sigma-Delta modulator mainly focused on forming an integer high order integrator to improve the SNR, whereas the paper presents a fractional-order integrator instead to obtain higher SNR and better stability. Specifically, a 4th order digital integrator and a fractional-order PIλ controller are inserted between the AFE and the quantizer. The 4th order digital integrator increases overall loop order to produce much higher SNR for Sigma-Delta modulator and the fractional-order PIλ controller allows fine tuning accuracy in seeking the coefficients for Sigma-Delta modulator and provides stability in the placement of poles and zeros for compensating the phase delays caused by system nonlinearity. The parameters of PIλ controller are optimized by using swarm intelligent optimization algorithm. The stability of the proposed fractional-order Sigma-Delta modulator is analyzed and the robustness of the proposed fractional-order Sigma-Delta modulator is demonstrated. Further simulation from the fractional-order Sigma-Delta modulator, results of SNR>145dB and the noise floor under -190dB are obtained in frequency range of [5-150Hz].

Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator

A second-order sigma delta modulator that uses an operational transconductance amplifier as integrator and latch comparator as quantizer. The proposed technique where a low power high gain OTA is used as integrator and another circuit called dynamic latch comparator with two tail transistors and two controlling switches are used to achieve high speed, low power and high resolution in second order delta sigma modulator. It enhances the power efficiency and compactness of the modulator by implementing these blocks as sub modules. A second order modulator has been designed to justify the effectiveness of the proposed design. Technology 180nm CMOS process is used to implement complete second order continuous time sigma delta modulator. We introduce the sub threshold three stage OTA, which is a way of achieving low distortion operation with input referred noise at 1 KHz is equal to the 2.2647pV/ and with low power consumption of 296.72nW. A high-speed, low-voltage and a low-power Double-Tail dynamic comparator is also proposed. The proposed structure is contrasted with past dynamic comparators. In this paper, the comparator’s delay will be investigated and systematic analysis are inferred. a novel comparator using two tail transistor is proposed, here circuitry of a customized comparator having two tail is changed for low power dissipation and also it operates fast at little supply voltages. By maintaining the outline and by including couple of transistors, during the regeneration strengthening of positive feedback can be maintained, this results in amazingly diminished delay parameter. It is investigated that in proposed design structure of comparator using two tail transistors, power consumption is reduced and delay time is also diminished to a great extent. The proposed comparator is having maximum clock frequency that is possibly expanded up to 1GHz at voltages of 1 V whereas it is dissipating 10.99 µW of power, individually. By using sub threshold three stage OTA and dynamic standard two tail latch comparator, designed second order sigma delta ADC will consume 29.95µW of power.

A ± 3 ppm/°C Single-Trim Switched Capacitor Bandgap Reference for Battery Monitoring Applications

A precision bandgap reference has been developed in a $0.18~\mu \text {m}$ BiCMOS process that achieves ±3 ppm/°C temperature drift at ±3 $\sigma $ from −40 °C to 110 °C. The reference is designed to utilize single temperature trim and standard components. A 3.65 V switched capacitor reference voltage is provided to a $2^{{\textrm {nd}}}$ order delta-sigma modulator ADC to digitize a battery cell voltage. The switched capacitor reference utilizes fully differential sampling which reduces the errors from channel charge injection and clock feedthrough introduced by pseudo-differential sampling. A new technique for sampling a $\text {V}_{{\textrm {be}}}$ voltage directly onto the output of the reference’s differential amplifier has been developed that removes the error that would be introduced from differentially sampling the $\text {V}_{{\textrm {be}}}$ and the $\Delta \text {V}_{{\textrm {be}}}$ voltage terms independently. The bandgap reference and ADC combination have an input referred noise spectral density of $4.7~\mu \text {V}/\surd $ Hz from 0.1 to 162 Hz yielding 15 stable output bits.

Improving performance of mobile fronthaul architecture employing high order delta-sigma modulator with PAM-4 format.

An improved high-order delta-sigma modulator with multi-level quantizer is proposed to enable carrier aggregation of 4G-LTE signals in mobile fronthaul. Different from conventional delta-sigma modulation-based digital mobile fronthaul, a 2-bit quantizer is employed to reduce the quantization noise, which enabling the transmission via PAM-4 based IM-DD channel. Moreover, we employ the 4th-order high-pass filter (HPF) to replace the 1st-order HPF in the conventional delta-sigma modulator, resulting in a much better noise shaping performance. In the experiment, a PAM-4 based mobile fronthaul transmission of 32 aggregated 4G-LTE signals with a CPRI equivalent data rate of 39.32-Gb/s is demonstrated in a single-λ 10-Gb/s IM-DD channel. Significant improvement of 68% is achieved in the average EVM performance compared to the previous delta-sigma modulation-based digital mobile fronthaul.

A novel low order delta–sigma modulator without harmonic distortion

The paper discusses a novel delta---sigma (ΔΣ) modulator structure, which compensates for the influence of a higher harmonic distortion to achieve a high resolution of up to 16 bits for the OSR = 100. The proposed approach combines the advantages of single-bit quantizer ΔΣ modulators with those provided by multi-bit ΔΣ devices. In the initial part of the article, we present the novel second-order structure, verify its correct functioning via the MATLAB simulation environment, and examine the requirements for a partial block. The related sections of the paper then analyze the design of a ΔΣ converter comprising the novel modulator structure and utilizing both the switched capacitor technique and the ONSemi I3T25 (350 nm) technology. The advantages and disadvantages of the discussed solution are evaluated, and the structure is compared with common versions of the ΔΣ modulator. The value of SNDR = 86 dB (ENOB = 14 bits) was achieved in the entire bandwidth.

Two-path all-pass based half-band infinite impulse response decimation filters and the effects of their non-linear phase response on ECG signal acquisition

Abstract This paper is based on the novel use of a very high fidelity decimation filter chain for Electrocardiogram (ECG) signal acquisition and data conversion. The multiplier-free and multi-stage structure of the proposed filters lower the power dissipation while minimizing the circuit area which are crucial design constraints to the wireless non-invasive wearable health monitoring products due to the scarce operational resources in their electronic implementation. The decimation ratio of the presented filter is 128, working in tandem with a 1-bit 3 rd order Sigma Delta (ΣD) modulator which achieves 0.04 dB passband ripples and −74 dB stopband attenuation. The work reported here investigates the non-linear phase effects of the proposed decimation filters on the ECG signal by carrying out a comparative study after phase correction. It concludes that the enhanced phase linearity is not crucial for ECG acquisition and data conversion applications since the signal distortion of the acquired signal, due to phase non-linearity, is insignificant for both original and phase compensated filters. To the best of the authors’ knowledge, being free of signal distortion is essential as this might lead to misdiagnosis as stated in the state of the art. This article demonstrates that with their minimal power consumption and minimal signal distortion features, the proposed decimation filters can effectively be employed in biosignal data processing units.

An All-Digital Fast Tracking Switching Converter with a Programmable Order Loop Controller for Envelope Tracking RF Power Amplifiers.

This paper presents a step down, switched mode power converter for use in multi-standard envelope tracking radio frequency power amplifiers (RFPA). The converter is based on a programmable order sigma delta modulator that can be configured to operate with either 1st, 2nd, 3rd or 4th order loop filters, eliminating the need for a bulky passive output filter. Output ripple, sideband noise and spectral emission requirements of different wireless standards can be met by configuring the modulator's filter order and converter's sampling frequency. The proposed converter is entirely digital and is implemented in 14nm bulk CMOS process for post layout verification. For an input voltage of 3.3V, the converter's output can be regulated to any voltage level from 0.5V to 2.5V, at a nominal switching frequency of 150MHz. It achieves a maximum efficiency of 94% at 1.5 W output power.

PROGRAMMABLE PARALLEL FBD SIGMA DELTA ADC RECONSTRUCTION STAGE DESIGN FOR SOFTWARE DEFINED RADIO RECEIVER

Today’s bottleneck of signal processing in multistandard software defined radio (SDR) receiver is the analog-to-digital converter (ADC). Therefore, the authors present in this paper the design and simulation results of a programmable parallel frequency band decomposition (FBD) architecture for ADC. The designed parallel architecture is composed of six parallel branches based on discrete-time (DT) 4th order sigma delta modulators using single-bit quantizers. Each branch processes a sub-bandwidth of the received signal. Only needed branches are selected according to the chosen standard. The parallel sigma delta modulators’ outputs are handled by a demodulation-based digital reconstruction stage in order to provide the FBD sigma delta-based ADC output signal. The digital reconstruction stage differs from one communication standard to another. In this paper, its design is discussed for the UMTS use case. The objective is to propose a digital reconstruction design with optimized complexity. In fact, the authors propose a comparative study between some configurations of demodulation, decimation and filtering processes. Technical choices and simulation results are discussed. For UMTS use case, the proposed FBD sigma delta-based ADC architecture ensures a computed signal-to-noise ratio (SNR) over 74 dB.

위상고정루프를 이용한 낮은 지터 성능을 갖는 스마트 오디오 디바이스용 이중 출력 주파수 합성기 설계

A Low jitter dual output frequency synthesizer for smart audio devices is described in this paper. It has been fabricated in a 1.8 V Dongbu CMOS process. Output frequency is controlled by 3 rd order Sigma-Delta Modulation and digital divider. The frequency synthesizer has a size of , frequency range of 0.6-200 MHz, loop bandwidth of 350 kHz, and rms jitter of 11.4 ps-21.6 ps.

Design and Implementation of Decimation Filter for 13-bit Sigma-Delta ADC Based on FPGA

A 13 bit Sigma-Delta ADC for a signal band of 40K Hz is designed in MATLAB Simulink and then implemented using Xilinx system generator tool. The first order Sigma-Delta modulator is designed to work at a signal band of 40 KHz at an oversampling ratio (OSR) of 256 with a sampling frequency of 20.48 MHz. The proposed decimation filter design is consists of a second order Cascaded Integrator Comb filter (CIC) followed by two finite impulse response (FIR) filters. This architecture reduces the need for multiplication which is need very large area. This architecture implements a decimation ratio of 256 and allows a maximum resolution of 13 bits in the output of the filter. The decimation filter was designed and tested in Xilinx system generator tool which reduces the design cycle by directly generating efficient VHDL code. The results obtained show that the overall Sigma-Delta ADC is able to achieve an ENOB (Effective Number Of Bit) of 13.71 bits and SNR of 84.3 dB

2개의 증폭기를 이용한 가변 구조 형의 4차 델타 시그마 변조기

본 논문에서는 생체 신호 처리를 위한 14비트 이상의 고 해상도를 갖는 A/D 변환기 설계를 위하여 공급 전압이 1.8V인 CMOS 델타-시그마 변조기를 설계하였다. 본 논문에서 제안하는 4차 델타 시그마 변환기는 타임 인터리빙 기술을 이용하여 회로를 시간에 따라 재구성해 연산증폭기를 재사용하는 구조를 통해 차수에 따라 4개의 연산증폭기가 필요한 회로를 2개의 연산증폭기 만으로 구동 시켰다. 또한 스위치드 커패시터 적분기 구조상의 특징인 샘플링 시간과 적분 시간의 동작에 따라 샘플링 커패시터의 크기를 조절함으로서 저항 성분으로부터 발생하는 열잡음인 KT/C 잡음을 감소시킬 수 있는 회로를 제안하였다. 제안한 델타-시그마 변조기는 Magna 0.18㎛ CMOS n-well 1 폴리 6메탈 공정을 이용하여 제작되었으며 제작된 칩의 측정 결과 전력소모는 1.8V 전원 전압에서 828㎼이고 샘플링 및 입력 주파수가 256㎑, 1㎑일 때 최대 SNDR은 75.7㏈, DR은 81.3㏈로 측정되었다. KT/C 잡음 저감 회로가 적용되지 않은 회로에서는 최대 SNDR이 72.1㏈ 로 측정되어 KT/C 잡음 저감 회로가 적용되었을 때 약 3㏈정도의 성능 향상을 나타내었다. 회로의 FOM은 41pJ/step 과 142㏈로 계산되었다.

연산증폭기 공유 기법을 이용한 145μW, 87dB SNR을 갖는 저전력 3차 Sigma-Delta 변조기

In this paper, a , 87dB SNR, Low power 3rd order Sigma-Delta Modulator with Op-amp sharing is proposed. Conventional architecture with analog path and digital path is improved by adding a delayed feed -forward path for disadvantages that coefficient value of the first integrator is small. Proposed architecture has a larger coefficient value of the first integrator to remove the digital path. Power consumption of proposed architecture using op-amp sharing is lower than conventional architecture. Simulation results for the proposed SDM designed in CMOS technology with power supply voltage 1.8V, signal bandwidth 20KHz and sampling frequency 2.8224MHz shows SNR(Signal to Noise Ratio) of 87dB, the power consumption of .