Abstract
Today’s bottleneck of signal processing in multistandard software defined radio (SDR) receiver is the analog-to-digital converter (ADC). Therefore, the authors present in this paper the design and simulation results of a programmable parallel frequency band decomposition (FBD) architecture for ADC. The designed parallel architecture is composed of six parallel branches based on discrete-time (DT) 4th order sigma delta modulators using single-bit quantizers. Each branch processes a sub-bandwidth of the received signal. Only needed branches are selected according to the chosen standard. The parallel sigma delta modulators’ outputs are handled by a demodulation-based digital reconstruction stage in order to provide the FBD sigma delta-based ADC output signal. The digital reconstruction stage differs from one communication standard to another. In this paper, its design is discussed for the UMTS use case. The objective is to propose a digital reconstruction design with optimized complexity. In fact, the authors propose a comparative study between some configurations of demodulation, decimation and filtering processes. Technical choices and simulation results are discussed. For UMTS use case, the proposed FBD sigma delta-based ADC architecture ensures a computed signal-to-noise ratio (SNR) over 74 dB.
Highlights
Software defined radio (SDR) technology is a state-of-the-art technology solution proposed by scientists to achieve a feasible multistandard receiver [1]
The mixer is followed by a non-programmable 6th order Butterworth anti-aliasing filter (AAF) that passes all signals in the IEEE802.11a bandwidth and attenuates blockers around sampling frequency
Starting from system level specifications according to the communication standards handled by the SDR receiver, an frequency band decomposition (FBD) ƩΔ-based analog-to-digital converter (ADC) architecture design is presented
Summary
Software defined radio (SDR) technology is a state-of-the-art technology solution proposed by scientists to achieve a feasible multistandard receiver [1]. In the literature, there is no such a fully-integrated ADC that fulfills SDR constraints [6,7] To overcome this problem, the authors propose the use of parallel architectures based on Σ∆ modulators that ensure high dynamic range while extending signal conversion bandwidth [8]. The proposed FBD architecture is composed of six programmable branches based on discrete-time (DT) 4th order modulators [17]. An FBD -based ADC architecture that is a generic parallel architecture composed of ten 3rd order continuous-time (CT)- modulators This architecture operates at 800 MHz-sampling frequency with a total conversion bandwidth of 80. Afterwards, the obtained FBD -based ADC with the optimized digital reconstruction stage is implemented on MATLAB/SIMULINK environment and section 4 deals with simulation results.
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