Abstract
This paper presents the study of phase mismatch in parallel frequency band decomposition (FBD)-based analog-to-digital converter (ADC). This architecture is designed for analog-to-digital conversion of wireless communication signals in a software defined radio (SDR) receiver. It is composed of 6 parallel branches based on discrete-time (DT) ΣΔ modulators using single-bit quantizers. The parallel branches operate on different sub-bandwidths and only needed branches are activated according to the selected standard. The division of the signal channel bandwidth on different sub-bandwidths and the digitization of each sub-bandwidth by one of the parallel branches lead to phase mismatching at the frequency boundaries between the adjacent branches. This paper focuses on the phase mismatch study and its correction in the FBD ΣΔ-based ADC architecture.
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