Order Continuous-time Research Articles

Design of FOPID controller for fractional-order plants with experimental verification

In this paper, a design method is proposed for a robust stabilizing fractional order proportional integral derivative (FOPID) controller for One Non-Integer Order Plus Time Delay plant (NIOPTD-I). The NIOPTD-I model is obtained after reducing the higher order continuous time process model. The FOPID controller is designed by using stability boundary locus method, which satisfies user defined frequency domain specifications phase margin and the gain crossover frequency. A robust control system is designed against gain variations by achieving flat phase condition which is due to zero slope at the gain crossover frequency of the phase plot. Thus robust stabilizing FOPID controller for NIOPTD-I fractional order plant is designed. The applicability of the proposed method is illustrated with simulation example and experimental validation with the liquid level control system.

Power and area efficient continuous time ΣΔ modulator based on local feedback

This paper presents an area efficient implementation of a second order continuous time (CT) sigma-delta (ΣΔ) modulator. In the proposed implementation, traditional operational amplifiers (op-amps) have been replaced by a low-complexity current mode structure based on local feedback to obtain power and area efficiency. The ΣΔ modulator specifications have been set for a passive RFID tag with sensing capability application, so that achieving minimum active area and very low power consumption are the main goals of the presented design. Experimental results show 8.75 bits of Effective-Number-Of-Bits (ENOB) in a 25kHz signal bandwidth with only 3.8μW of power consumption operating at 1.7V of supply voltage. A Figure Of Merit (FOM) of 175 fJ/level has been achieved with total area occupancy (without pads) of 150μm×125μm in a 0.35μm CMOS technology.

A Low Cost Design of Time Division Multiplexing Based 3rd Order Continuous-Time Incremental ΣΔ Modulator with Excess Loop Delay

A Low Cost Design of Time Division Multiplexing Based 3rd Order Continuous-Time Incremental ΣΔ Modulator with Excess Loop Delay

Design of Linear CMOS Transconductance Elements for Alpha-Power Law Based Mosfets and an Automatic Compensation Technique for Temperature

A model on alpha-power law MOSFETs based source-coupled differential pair (SCDP) is discussed and a simple design procedure for realizing a linear CMOS SCDP transconductance element is proposed. The proposed or modified SCDP circuit using this procedure is an alternative to that of conventional SCDP and the circuit discussed has superior linearity for a wide range ±(0-300mv) of input differential voltage at a supply voltage of 1.2v. The modified SCDP also includes the circuitry needed to suppress the variation in the quiescent current with respect to input common-mode voltage noise. The SPICE results are used to verify theoretical predictions. The results show close agreement between the predicted model behavior and the simulated performance. The simulated result on Total Harmonic Distortion (THD) shows that the modified SCDP circuit is better than the conventional SCDP by about four times at input differential voltage amplitude of ±100mv. An example circuit, a second order continuous time gm-C band-pass filter is constructed using the fully differential modified SCDP and the fully differential conventional SCDP circuit and the result shows that the modified transconductor circuit is better in linearity (THD) than the conventional SCDP by about two times at the input differential voltage amplitude of ±100mv. An automatic digital compensation scheme for temperature is also presented and the temperature coefficient of output current is reduced by about eight times to 250ppm/deg. C after compensation for the maximum change in temperature of 150deg.C and at the input differential voltage of 100mv.

Synteza obserwatorów funkcyjnych liniowych ciągłych układów niecałkowitego rzędu

The paper presents a problem of synthesis of functional observers for fractional order continuous-time linear systems. It has been shown that this problem can be formulated and solved by the use of linear matrix inequalities (LMI) method. Necessary and sufficient conditions for solvability of the problem for computation of an unknown matrices of asymptotic stable observers have been given. The proposed approach is illustrated by a numerical example.

A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW

This paper presents a single loop, third order continuous time ΔΣ modulator with an internal 4 bit quantizer sampled at 500 MHz with only an oversampling ratio of 10. Since multi-bit operation commonly suffers from DAC non-linearities, and dynamic element matching is ineffective at low oversampling, an alternative auxiliary DAC linearization is proposed for ΔΣ modulators. The unit element mismatches are digitally estimated based on a cross correlation of a binary test signal with the modulator output and represent the measured DNL of DAC1. The corresponding INL is calculated and stored in an 15×8 lookup-table which is applied to the 8 bit auxiliary DAC to linearize DAC1. Moreover, a design centering approach for amplifier finite gain bandwidth compensation within the loop filter is presented which allows for large bandwidth mismatch with negligible effect on loop filter stability. This results in a robust architecture over temperature, supply, and excess loop delay variations. The presented ΔΣ modulator achieves an SNDR of 67.5 dB, DR of 72 dB, and SFDR of 79 dB over a 25 MHz bandwidth and is implemented in a 1.2 V, 90 nm CMOS process. The modulator occupies an active area of 0.19 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and has a power consumption of 8.5 mW. It achieves a figure of merit of 88 fJ/conv-step which is one of the best published for multi-bit ΔΣ modulators.

Finite-Time Control of a Quadrotor System

This paper deals with the finite-time control of a quadrotor unmanned aerial vehicle about the hovering position by converting the linearized model to its Brunovský canonical form. It is shown that all the sliding surfaces have relative degree five or three. Simulations are carried out using higher order continuous finite time controllers.

Design of an ultra low power third order continuous time current mode ΣΔ modulator for WLAN applications

This paper presents a third order continuous time current mode ΣΔ modulator for WLAN 802.11b standard applications. The proposed circuit utilized feedback architecture with scaled and optimized DAC coefficients. At circuit level, we propose a modified cascade current mirror integrator with reduced input impedance which results in more bandwidth and linearity and hence improves the dynamic range. Also, a very fast and precise novel dynamic latch based current comparator is introduced with low power consumption. This ultra fast comparator facilitates increasing the sampling rate toward GHz frequencies. The modulator exhibits dynamic range of more than 60dB for 20MHz signal bandwidth and OSR of 10 while consuming only 914μW from 1.8V power supply. The FoM of the modulator is calculated from two different methods, and excellent performance is achieved for proposed modulator.

A Low-Power CT Incremental 3rd Order &lt;formula formulatype="inline"&gt; &lt;tex Notation="TeX"&gt;$\Sigma\Delta$&lt;/tex&gt;&lt;/formula&gt; ADC for Biosensor Applications

This paper proposes a 3rd order single-loop continuous-time incremental sigma-delta analogue-to-digital converter (ADC) for time-multiplexed signals. Incremental sigma-delta modulation is used to address medium to high resolution requirements of multi-channel applications, while a 3rd order continuous-time implementation is investigated as an alternative for low-power solutions. A prototype of the proposed modulator, running at 320 kHz, has been fabricated in a 0.15-μm CMOS technology, while the synchronization circuitry to allow incremental operation was built on-board. Measurement results show that the ADC achieves 65.3 dB peak SNR, 64 dB peak SNDR and 68.2 dB dynamic range over a 2 kHz bandwidth. The modulator's power dissipation is 96 μW from a 1.6 V power supply. This translates into the best figure-of-merit when compared to recently published continuous-time alternatives, while being competitive with respect to state-of-the-art discrete-time counterparts.

A CMOS Gas Sensor Array Platform With Fourier Transform Based Impedance Spectroscopy

A CMOS gas sensor array platform with digital read-out containing 27 sensor pixels and a reference pixel is presented. A signal conditioning circuit at each pixel includes digitally programmable gain stages for sensor signal amplification followed by a second order continuous time delta sigma modulator for digitization. Each sensor pixel can be functionalized with a distinct sensing material that facilitates transduction based on impedance change. Impedance spectrum (up to 10 KHz) of the sensor is obtained off-chip by computing the fast Fourier transform of sensor and reference pixel outputs. The reference pixel also compensates for the phase shift introduced by the signal processing circuits. The chip also contains a temperature sensor with digital readout for ambient temperature measurement. A sensor pixel is functionalized with polycarbazole conducting polymer for sensing volatile organic gases and measurement results are presented. The chip is fabricated in a 0.35 μm CMOS technology and requires a single step post processing for functionalization. It consumes 57 mW from a 3.3 V supply.

Partial Pole Placement with Controller Optimization

An arbitrary subset (n - m) of the (n) closed loop eigenvalues of an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> order continuous time single input linear time invariant system is to be placed using full state feedback, at pre-specified locations in the complex plane. The remaining m closed loop eigenvalues can be placed anywhere inside a pre-defined region in the complex plane. This region constraint on the unspecified poles is translated into a linear matrix inequality constraint on the feedback gains through a convex inner approximation of the polynomial stability region. The closed loop locations for these m eigenvalues are optimized to obtain a minimum norm feedback gain vector. This reduces the controller effort leading to less expensive actuators required to be installed in the control system. The proposed algorithm is illustrated on a linearized model of a 4-machine, 2-area power system example.

Reliability aware design of low power continuous-time sigma–delta modulator

Circuit reliability has become a major bottleneck due to ageing degradation. In this paper, reliability-aware methodology and ageing analysis of low power sigma–delta (ΣΔ) modulator are presented. HCI and NBTI are considered as the dominating ageing effects. A second order continuous-time (CT) ΣΔ modulator is implemented for medical application. Ageing estimation is performed at both behavioral and transistor level. Results at behavioral level and transistor level show that the feedback loop in CT ΣΔ modulator is more sensitive and less reliable than the analog loop filter. Comparing with HCI, NBTI is the dominating ageing effect in the designed CT ΣΔ modulator.

Partial Pole Placement and Controller Norm Optimization over Polynomial Stability Region

AbstractAn arbitrary subset (n – m) of the n closed loop eigenvalues of an nth order continuous time single input linear time invariant (LTI) system is to be placed using full state feedback, at pre-specified locations in the complex plane. The remaining m closed loop eigenvalues can be placed anywhere inside a pre-defined region in the complex plane. This region constraint on the unspecified poles is translated into an ellipsoidal constraint on the characteristic polynomial coefficients through a convex inner approximation for polynomial stability regions. The closed loop locations for these m eigenvalues are chosen through an explicit minimization of the feedback gain vector norm leading to an efficiently solvable semidefinite program. The required controller effort is thus minimized leading to less expensive actuators.

A Fully Integrated $\Delta \Sigma$ ADC in Organic Thin-Film Transistor Technology on Flexible Plastic Foil

In this work we present a fully integrated first order continuous-time ΔΣ ADC made in a pentacene-based dual-gate organic thin-film transistor technology on flexible plastic foil. The ADC achieves a precision of 26.5 dB at a clock speed of 500 Hz and draws 100 μA from a 15 V power supply. As sub-blocks of the ADC, we also present a Vt -insensitive single-stage differential amplifier with 10 kHz GBW, a 3-stage operational amplifier, an integrator, a comparator and a level shifter. The circuits are designed following a strict Vt -insensitive design strategy and use high-pass filters for offset cancellation. The active area is 13 × 20 mm2.

Desired Order Continuous Polynomial Time Window Functions for Harmonic Analysis

An approach for the construction of a family of desired order continuous polynomial time window functions is presented without self-convolution of the parent window. The higher order of continuity of the time window functions at the boundary of the observation window helps in suppressing the spectral leakage. Closed-form expressions for window functions in the time domain and their corresponding Fourier transform are derived. The efficacy of these new window functions in discerning the weak signal is demonstrated by computer simulations.

Closed form ℒ 2/ℋ2-optimising of zeros for model reduction of linear continuous time systems

Closed form expressions of transfer function responses are applied in this article to model reduction of nth order continuous time systems with respect to the location of zeros for a given location of poles. Explicit closed form formulae are derived for the numerator coefficients in the transfer function of the reduced system that minimise the integrated square deviation from the original system with respect to the impulse response or higher order responses, i.e. effective ℒ2 or ℋ2-optimisation. The relative degree of the reduced model can be selected freely, e.g. as the original model's one, by selecting the number of numerator coefficients. Constraints are dealt with by introducing a vector of Lagrange multipliers corresponding to the response order. The formulae are also related to solutions of Lyapunov and Sylvester equations based on the companion matrices of the original and reduced systems. The formulae derived can be used to enhance the results obtained from other reduction techniques such as those based on balanced Grammian reduction and singular value decomposition for mid-sized systems. Two examples, demonstrating this, are presented. The formulae can also be used as a basis for a more general optimisation approach, where the optimisation with respect to the numerator coefficients or the zeros, resulting in the solution of a linear system of equations, is combined with non-linear optimisation with respect to the denominator coefficients or the poles.

Modeling of integrator leakage in a continuous time ΔΣ-modulator using Matlab

This work focuses on simulation and modeling of integrator leakage in a continuous time (CT) ΔΣ-modulator. The resolution of a ΔΣ-modulator is affected by the integrator leakage that limits the noise characteristics in the low frequency range and at DC. The model describes charge injection and charge sharing when the polarity of the I-DAC (current digital to analog converter) alternates or when the first integrator is chopped for noise and offset cancellation. Charge sharing and charge injection is simulated with Spice. The result of the integrator leakage is an increased noise level at low frequencies and a dead zone at zero input level. A Matlab model describing the charge errors on the first integration capacitor was developed to model the integrator leakage and to estimate the width of the dead zone for small input signals. The simulation model is compared with measurements done on a 3rd order continuous time ΔΣ-modulator.

PREDICTIVE CONTROL OF CONTINUOUS CHAOTIC SYSTEMS

In this paper, a predictive control method is suggested for chaos control in continuous-time systems. This method combines the delayed feedback control of high order continuous-time chaotic systems with the prediction-based method of discrete-time chaotic systems. Moreover, we give necessary and sufficient conditions for exponential stabilization of unstable fixed points by the proposed method. Both control performance and system sensitivity to initial conditions of this approach are demonstrated by numerical simulations.

Microgyroscope control system using a high-order band-pass continuous-time sigma-delta modulator

The paper presents a novel 6th order continuous-time, force-feedback band-pass sigma-delta modulator control system for the detection mode of micromachined vibratory gyroscopes. Compared with the architecture using a low-pass sigma-delta modulator, this band-pass solution uses a much lower sampling frequency for the sigma-delta modulator and thus reduces the requirement for frequency response of the detection interface and control electronics. In this work, the sigma-delta modulator operates at only four times of mechanical resonant frequency, which allowed its implementation in a continuous-time circuit using discrete electronic components on a PCB; this has the advantage of simple prototyping and can improve the signal anti-aliasing characteristics.

O sobre-sinal e a resposta inversa em sistemas de controle lineares contínuos no tempo

Este trabalho trata da determinação dos extremos que podem ocorrer na resposta a uma entrada degrau unitário de sistemas lineares contínuos no tempo, com pólos e zeros reais. Apresentam-se condições necessárias e suficientes para avaliar extremos, sobre-sinal e resposta inversa na resposta a uma entrada degrau unitário de sistemas de ordem n &gt; 2 com um zero real e pólos reais distintos. Todos os resultados são apresentados em termos das localizações de pólos e zeros da correspondente função de transferência.