Order Bits Research Articles

An Iterative Fusion Technique for Dynamic Side Information Refinement in Pixel Domain Distributed Video Coding

Distributed video coding (DVC) technology has been considered to be capable of reducing the processing complexity of the encoder immensely, while majority of the computational overheads are taken over by the decoder. In the common DVC framework, the pictures are decoded using the Wyner-Ziv encoded bit stream received from the encoder and the side information estimated using previously decoded information. As a result, accuracy of the side information estimation is very critical in improving the coding efficiency. In this paper we propose a novel side information refinement technique for DVC using multiple side information streams and sequential motion compensation with luminance and chrominance information involving iterative fusion of parallel information streams. In the bit plane wise coding architecture, previously decoded higher order bit planes are incrementally used to perform the motion estimation jointly in luminance and chrominance spaces to estimate multiple redundant bit streams for iterative fusion to produce more improved side information for subsequent bit planes. Simulation results show significant objective quality gain can be achieved at the same bit rate by utilizing the proposed refinement algorithms.

Energy-Aware Dual-Rail Bit-Wise Completion Pipelined Arithmetic Circuit Design

Energy-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Because of the encoding format and operating sequence, dual-rail encoding circuits do not naturally energy aware to the changing of input precisions. A novel technique named Zero Insertion for designing energy-aware arithmetic circuits in dual-rail encoding logic is developed. By using Null to replace the redundant Data 0’s in high order bits, the designed circuits have significant energy savings as well as latency reduction at different input precisions while maintaining speed-independency. Parallel adders, multipliers, and a rank-order filter, have been designed and simulated to demonstrate the effectiveness of this technique. The overhead and additional costs in the control circuit are also discussed.

An automatic coefficient design methodology for high-order bandpass sigma-delta modulator with single-stage structure

An automatic coefficient design method for synthesis of bandpass sigma-delta modulators (BPSDMs) is presented in this brief. Single-stage BPSDM structures, cascade-of-resonator with distributed feedback, cascade-of-resonator with distributed feedforward, and a new structure with lower coefficient spread, are all used to fit the synthesized coefficients. The automatic coefficient design method is realized in an easy-to-use computer program. Even for inexperienced designers, reliable and high-tolerance BPSDM coefficients for various applications can be automatically and efficiently generated. The methodology covers many design concerns including BPSDM coefficient tolerance for circuit component mismatch, design tradeoffs among in-band noise suppression, oversampling ratio, modulator order and quantizer bit number. Finally, design examples with orders of 6 and 8, and quantizer bit number of 1-bit and 3-bit, respectively, are used for the verification of the proposed automatic coefficient design method.

Exploiting Narrow Values for Soft Error Tolerance

Soft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. In this paper we propose simple mechanisms that effectively reduce the vulnerability to soft errors In a processor. Our designs are generally motivated by the fact that many of the produced and consumed values in the processors are narrow and their upper order bits are meaningless. Soft errors canted by any particle strike to these higher order bits can be avoided by simply identifying these narrow values. Alternatively soft errors can be detected or corrected on the narrow values by replicating the vulnerable portion of the value inside the storage space provided for the upper order bits of these operands. We offer a variety of schemes that make use of narrow values and analyze their efficiency in reducing soft error vulnerability of level-1 data cache of the processor

Spectral prefetcher

Effective data prefetching requires accurate mechanisms to predict embedded patterns in the miss reference behavior. This paper proposes a novel prefetching mechanism, called the spectral prefetcher (SP), that accurately identifies the pattern by dynamically adjusting to its frequency. The proposed mechanism divides the memory address space into tag concentration zones (TCzones) and detects either the pattern of tags (higher order bits) or the pattern of strides (differences between consecutive tags) within each TCzone. The prefetcher dynamically determines whether the pattern of tags or strides will increase the effectiveness of prefetching and switches accordingly. To measure the performance of our scheme, we use a cycle-accurate aggressive out-of-order simulator that models bus occupancy, bus protocol, and limited bandwidth. Our experimental results show performance improvement of 1.59, on average, and at best 2.10 for the memory-intensive benchmarks we studied. Further, we show that SP outperforms the previously proposed scheme, with twice the size of SP, by 39% and a larger L2 cache, with equivalent storage area by 31%.

A new approach to greedy multiuser detection

We propose a new suboptimum multiuser detector for synchronous and asynchronous multiuser communications. In this approach, a greedy strategy is used to maximize the cost function, the maximum-likelihood (ML) metric. The coefficients of the ML metric are utilized as weights indicating in which order bits can be estimated. The complexity of the algorithm is approximately K/sup 2/ log K per bit, where K is the number of users. We analyze the performance of the greedy multiuser detection in the additive white Gaussian noise channel as well as in the frequency-nonselective Rayleigh fading channel, and compare it with the optimum detector and several suboptimum schemes such as conventional, successive interference cancellation, decorrelator, sequential, and multistage detectors. The proposed greedy approach considerably outperforms these suboptimum schemes, especially for moderate and high loads in low and moderate signal-to-noise ratio regions. The results show that when there is a significant imbalance in the values of the coefficients of the ML metric due to moderate to high noise, fading, and asynchronous transmission, near-optimum performance is achieved by the greedy detection.

Mobile Internet protocol

The Internet works on a simple principle. The two endpoints are essentially stationary computers. The IP routes the packets of data from source to destination with the help of routers. This forwarding of packets by the routers is done depending upon the contents of their router tables. The router tables maintain the out-bound network interface (i.e., the next hop) information for each destination IP address according to the number of networks to which that IP address is connected. The network number is derived from the IP address by masking off some of the low order bits. The working of the mobile Internet protocol is discussed. This is illustrated as a journey from a source to a destination.

Theoretical analysis of word-level switching activity in the presence of glitching and correlation

This paper presents a novel analytical approach to compute the switching activity in digital circuits at the word level in the presence of glitching and correlation. The proposed approach makes use of signal statistics such as mean, variance, and autocorrelation. It is shown that the switching activity /spl alpha//sub f/ at the output node f of any arbitrary circuit in the presence of glitching and correlation is computed as /spl alpha//sub f/=/spl Sigma//sub i=1//sup S-1//spl alpha/(f/sub i,i+1/)=/spl Sigma//sub i=1//sup S-/ /sup 1/p(f/sub i+1/)(1-p(f/sub i/))(1-/spl rho/(f/sub i,i+1/)) (1) where /spl rho/(f/sub i,i+1/)=/spl rho/(f/sub i,i+1/)=(E[f/sub i/(Sn)f/sub i+1/(Sn)]- p(f/sub i/)p(f/sub i+1/))/(/spl radic/(p(f/sub i/)-p(f/sub i/)/sup 2/)(p(f/sub i+1/)- p(f/sub i+1//sup 2/))) (2). S number of time slots in a cycle; /spl rho/(f/sub i/,+1) time-slot autocorrelation coefficient; E[x]=expected value of x; p/sub x/=probability of the signal x being one. The switching activity analysis of a signal at the word level is computed by summing the activities of all the individual bits constituting the signal. It is also shown that if the correlation coefficient of the higher order bits of a normally distributed signal x is /spl rho/(x/sub c/), then the bit P/sub 0/ where the correlation begins and the correlation coefficient is related hy /spl rho/(x/sub c/)=erfc{(2(P/sub 0/-1)-1)/(/spl radic/2/spl sigma//sub x/)} where erfc(x)=complementary error function; /spl sigma//sub x/=variance of x. The proposed approach can estimate the switching activity in less than a second which is orders of magnitude faster than simulation-based approaches. Simulation results show that the errors using the proposed approach are about 6.1% on an average and that the approach is well suited even for highly correlated speech and music signals.

Joint source and channel decoding of compressed still images

A joint source-channel decoding approach is described, which utilizes the residual redundancy in the bit stream of a source-coded image by employing a modified APRI-SOVA (a priori soft-output Viterbi algorithm) at the channel decoder. The source coders used are the nonadaptive discrete cosine transform (DCT) coding and subband coding with Lloyd-Max quantization. The log-likelihood ratio describing the a priori information is linearized. The reliability of the current bit is computed as a proper linear combination of the soft values characterizing statistical dependency of the zeroth order (probability of 1's or 0's) and the first order (bit correlation among neighboring samples). Substantial subjective and objective performance gains can be obtained by using this method. It is demonstrated that especially in a noisy environment, it may be better to keep the residual redundancy in the data and use it at the receiver side in order to achieve a more reliable decoding, rather than to further remove it by using a variable length coding. The trade-off between the allocation of bits for source and channel coding is also addressed.

Optoelectronic thyristor-based photonic smart comparator for analog-to-digital conversion

A new photonic comparator approach to optoelectronic A/D conversion is demonstrated using an optoelectronic thyristor. The comparator has both digital optical output (since the thyristor itself is a laser in the "on" state) and electrical output that is analog or digital. The electrical output subtracts from the input and passes the result to the comparator input of the next lower order bit. High-speed operation is expected due to the elimination of stored charge in the thyristor structure. The thyristor characteristics are measured and the predicted comparator operation is verified using discrete devices at low frequencies.

Classified VQ codebook index assignment for communication over noisy channels

In this paper, an improved index assignment procedure is proposed to reduce the channel error effect in a communication system employing classified vector quantization (CVQ). The proposed algorithm consists of two parts: inner index assignment (IIA) and cross index assignment (CIA). The IIA reduces the distortion resulting from the error in order bits, presenting the identity of each code vector in a subcodebook. The CIA modifies the indexes assigned by the IIA in such a way that the effect of the channel error occurring in class bits, indicating the class information of the code vector can be minimized. Simulation results show that the proposed algorithms enable a reliable communication over noisy channels even without employing the channel encoding.

An optoelectronic thyristor-based analog-to-digital converter for parallel processing

A single pixel optoelectronic analog-to-digital converter is described which is suitable for two-dimensional (2D) arrays as would be required for a digital optical signal processor. The conversion is based upon the use of an optoelectronic thyristor in the form of the double heterostructure optoelectronic switch as a comparator. Using the switch configured as a VCSEL and one field-effect transistor load device, the comparator delivers the binary output optically and, at the same time, provides an electrical output to combine with the input signal to determine the next lower order bit. The function is similar to the algorithmic electrical converter with several optoelectronic advantages. Resolution of 10 bits is expected at speeds of 100 MHz with scaled transistor technology. The compact size of the circuit and the algorithm suggest a viable approach for conversion of 2D data arrays in real time.

Asynchronous analogue-to-digital converter for single-electroncircuits

An analogue-to-digital conversion scheme based on the e-periodic transfer characteristics of an SET inverter is proposed. The authors demonstrate the 4 bit analogue-to-digital converter performance using Monte-Carlo simulation in which an SET inverter implements a binary quantiser and encoder for one significant bit. This scheme can be easily extended to higher order bits.

Preserving radiometric resolution in remotely sensed data with lossy compression

Recent advances in imaging technology make it possible to obtain remotely sensed imagery data of the Earth at high spatial, spectral, and radiometric resolutions. The rate at which the data is collected from these satellites can far exceed the channel capacity of the data downlink. Reducing the data rate to within the channel capacity can often require painful trade-offs in which certain scientific returns are sacrificed for the sake of others. The authors focus on the case where radiometric resolution is sacrificed by dropping a specified number of lower order bits (LOB) from each data pixel. To limit the number LOBs dropped, they also compress the remaining bits using lossless compression. They call this approach truncation followed by lossless or TLLC. They then demonstrate the suboptimality of this TLLC approach by comparing it with the direct application of a more effective lossy compression technique based on the JPEG algorithm. This comparison demonstrates that, for a given channel rate, the method based on JPEG lossy compression better preserves radiometric resolution than does TLLC.

Partial resolution in branch target buffers

Branch target buffers, or BTBs, are small caches for program branching information. Like data caches, addresses are divided into equivalence classes based on their low order bits. Unlike data caches, however, complete resolution of a single address from within an equivalence class is not required for correct execution. Substantial savings are therefore possible by employing partial resolution, using fewer tag bits than necessary to uniquely identify an address. We present the relationship between the number of tag bits in a branch target buffer and prediction accuracy, based on dynamic simulations of the SPECINT92 benchmark suite. For a 512 entry BTB, on average only two tag bits are necessary to obtain 99.9 percent of the accuracy obtainable with a full tag; no more than nine tag bits are required to obtain identical prediction accuracy. This suggests that microprocessors can achieve substantial area savings in their BTB tag stores by employing partial resolution.

Distributed directory tags

This paper concerns a new directory scheme that can be used as an alternative to the current three types of directory schemes; direct mapped, set associative and fully associative. Both direct mapped and fully associative cache directories can be considered as a special case of the set associative directory since in the direct mapped case there are N congruent classes with a set size of 1 while in the fully associative case there are N sets and only 1 congruent class. However, irrespective of which class of directory scheme is used, since memory or cache directories generally provide a many-to-one mapping of a large address space to a small fast storage, a tag field must be associated with each element to identify one of the many addresses which actually map to the current value in the cache element. Thus, there are as many tags as there are total elements in the directory. The Distributed Directory Tag scheme described here uses the direct mapping of the addresses and distribution of the tags over the directory elements and thereby reduces the storage requirement for the directory tags by a significant factor. Our early findings indicate that addresses from application programs follow a particular distribution, with a strong bias towards less frequent change in the higher order bits. It is this observation that is exploited in the scheme described in this paper. The actual savings depend on the particular distribution chosen for an implementation, but in general, a factor of three reduction can be obtained while providing a hit ratio comparable to the other directory schemes. This savings in the tag bits is achieved while still providing set associativity within each congruent class. This scheme is particularly useful when cost/performance tradeoffs are a consideration. Thus, this novel directory design adds another type to the three existing cache directory schemes.

Randomness of Low-Order Bits in Random Number Generators

Pseudo-random numbers are widely used in Operations Research and applied mathema tics. With the growth in power of computers and languages, there is some tendency to use lower-significant bits within the pseudo- random number. Theoretical and empirical tests have not been sufficient to assess the randomness of these low-order bits. We show here for two generators that the low- order bits can be empirically tested, after first undertaking a bit-level transformation of the numbers.

An Expanded Set of Correlation Tests for Linear Congruential Random Number Generators

An analytic study is made of the correlation structure of Tausworthe and linear congruential random number generators. The former case is analyzed by the bit mask correlations recently introduced by Compagner. The latter is studied first by an extension to word masks, which include spectral test coefficients as special cases, and then by the bit mask procedure. Although low order bit mask coefficients vanish in both cases, the Tausworthe generator appears to produce a substantially smaller non-vanishing correlation set for large masks – but with larger correlation values – than does the linear congruential.

Ultrasonic bloodstream diagnostic apparatus with dual displays of velocity profiles and average flow velocity

A ultrasonic bloodstream diagnostic apparatus wherein the frequencies of Doppler shift ultrasound information are analyzed by a frequency analyzer to derive a power spectrum represented by N-bit data. The N-bit data comprises (K+M+L) bits, where K represents the number of binary 0's in the highest order bit positions and varies in the range between zero and N-M, M represents a fixed number of significant bits immediately following the binary 0's and L represents the number of insignificant bits in the lowest order bit positions immediately following the M significant bits, where K+L equals N-M. A data compression technique is employed to conver the N-bit data to (m+l)-bit data by a data conversion circuit, with the m bits respectively identical to the M bits and l bits being a binary representation of the number of the L bits. A microprocessor derives a signal representing the average frequency of the power spectrum from the (m+l)-bit output data signal. The (m+l)-bit output data signal is converted by a conversion memory to a form suitable for display by an algorithm which reconverts it to N-bits and logarithmically compresses the latter.

Reconstructing Truncated Integer Variables Satisfying Linear Congruences

We propose a general polynomial time algorithm to find small integer solutions to systems of linear congruences. We use this algorithm to obtain two polynomial time algorithms for reconstructing the values of variables $x_1 , \cdots ,x_k $ when we are given some linear congruences relating them together with some bits obtained by truncating the binary expansions of the variables. The first algorithm reconstructs the variables when either the high order bits or the low order bits of the $x_i $ are known. It is essentially optimal in its use of information in the sense that it will solve most problems almost as soon as the variables become uniquely determined by their constraints. The second algorithm reconstructs the variables when an arbitrary window of consecutive bits of the variables is known. This algorithm will solve most problems when twice as much information as that necessary to uniquely determine the variables is available. Two cryptanalytic applications of the algorithms are given: predicting linear congruential generators whose outputs are truncated and breaking the simplest version of Blum’s protocol for exchanging secrets.