Optoelectronic VLSI Research Articles

An OE-VLSI for parallel optical interconnection

This paper presents a prototype OE-VLSI (Optoelectronic-VLSI) with 12-channel input and output ports for optical parallel link applications. The OE-VLSI comprises of a 12-channel parallel VCSEL (Vertical Cavity Semi-conductor Laser) array and a 12-channel parallel Photo Diode array, a CPU, a 12-channel VCSEL driver array and a 12-channel optical front-end amplifier. The 12×10Gbps VCSEL driver array and the optical front-end amplifier array are fabricated in 0.18μm CMOS technology. The chip was partitioned into 12 parallel channels to demonstrate chip-to-chip interconnection functions appropriate for applications of OE-VLSI technology. The OE-VLSI chip has been validated on an optical parallel transmission system with bit-error-rate BER less than 10−12 and an aggregate 120Gpbs bandwidth.

Orthogonal drawings and crossing numbers of the Kronecker product of two cycles

An orthogonal drawing of a graph is an embedding of the graph in the plane such that each edge is representable as a chain of alternately horizontal and vertical line segments. This style of drawing finds applications in areas such as optoelectronic systems, information visualization and VLSI circuits. We present orthogonal drawings of the Kronecker product of two cycles around vertex partitions of the graph into grids. In the process, we derive upper bounds on the crossing number of the graph. The resulting upper bounds are within a constant multiple of the lower bounds. Unlike the Cartesian product that is amenable to an inductive treatment, the Kronecker product entails a case-to-case analysis since the results depend heavily on the parameters corresponding to the lengths of the two cycles.

ICs in very short reach optical interconnection

Closely integrated with photonic devices and VLSI electronics,ICs in very short reach(VSR) optical interconnection provide multiple high-performance optical input and output signals,with aggregated data-rates up to hundreds of Gb/s and even exceeding Tb/s.The basic structure of Optoelectronic-VLSI(OE-VLSI) is introduced in this paper.Moreover,the up-to-date applied research and progress of OE-VLSI in very short reach optical interconnection from home and abroad are presented,including the VSR optical transmission system,optical source and detector,multi chip mode packaging technology,as well as key high speed circuits.In the end,an outlook of OE-VLSI in very short reach optical interconnection is made.

Design and implementation of a modulator-based free-space optical backplane for multiprocessor applications.

Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 optical transmitters (implemented as dual-rail multiple quantum-well modulators) and 256 optical receivers. A rigid free-space microoptical interconnection system that interconnects the transceiver chips in a 512-channel unidirectional ring is implemented. Full design, implementation, and operational details are provided.

Implementation of a compact, four-stage, scalable optical interconnect for photonic backplane applications.

We report on the implementation of a dense 512-beam free-space optical interconnect linking four optoelectronic VLSI chips at the backplane level. The system presented maximizes the positioning tolerances of the components by use of slow f-number (f/16) Gaussian beams and oversized apertures. A beam-clustering scheme whereby a 4 x 4 array of beams is transmitted by each minilens is used to provide a high channel density. A modular approach is used to decrease the number of degrees of freedom in the system and achieve passive alignment of the modules in the final integration phase. A design overview as well as assembly and experimental results are presented.

Practical realization of massively parallel fiber–free-space optical interconnects

We propose a novel approach to realizing massively parallel optical interconnects based on commercially available multifiber ribbons with MT-type connectors and custom-designed planar-integrated free-space components. It combines the advantages of fiber optics, that is, a long range and convenient and flexible installation, with those of (planar-integrated) free-space optics, that is, a wide range of implementable functions and a high potential for integration and parallelization. For the interface between fibers and free-space optical systems a low-cost practical solution is presented. It consists of using a metal connector plate that was manufactured on a computer-controlled milling machine. Channel densities are of the order of 100/mm(2) between optoelectronic VLSI chips and the free-space optical systems and 1/mm(2) between the free-space optical systems and MT-type fiber connectors. Experiments in combination with specially designed planar-integrated test systems prove that multiple one-to-one and one-to-many interconnects can be established with not more than 10% uniformity error.

Architectures and technologies for an optoelectronic VLSI

Abstract The article discusses the possibilities of using short-distance optical interconnects in digital computing systems. It is postulated that high-dense optical free-space optical interconnects in the chip-to-chip area offer the possibility to overcome the serious pin limitation problem for VLSI circuits. The current investigated technologies for an optoelectronic three-dimensional VLSI are briefly presented. It is pointed out that the possible high channel density offered by optoelectronic interconnect technology is only exploited if the processor architecture supports this. The author presents a list of eight features an architecture should largely fulfil to guarantee an efficient use of high-dense optical interconnects. Examples for such architectures are presented. In a parallel optoelectronic digital signal processing unit an increase in the throughput performance about a factor of 70 compared with pure electronic solutions is achievable due to a parallel optical processor-memory coupling. Investigations of a prototype circuit show that three magnitudes better configuration times can by achieved by using optics in dynamically reconfigurable hardware compared to pure electronics. In closing a solution for a noise robust receiver circuit is presented to realise smart detector circuits in cost-effective standard CMOS processes.

Triggered receivers for optoelectronic VLSI

A ‘triggered’ transimpedance digital optical receiver is described which is usable in noisy environments typical of dense mixed-signal circuits. Results show enhanced immunity to supply variations compared to conventional transimpedance receivers.

Two-dimensional parallel pipeline smart pixel array cellular logic (SPARCL) processors-chip design and system implementation

We describe the chip design and system implementation of an optoelectronic parallel pipeline processing system composed of cascaded stages of smart pixel array cellular logic (SPARCL) processors interconnected with free-space digital optic channels. The SPARCL processing elements are arranged in a two-dimensional array, and each contains an independent optical input/output port and electrical nearest-neighbor local interconnections. The smart pixels are implemented using GaAs-GaAlAs multiple-quantum-well diode arrays flip-chip bonded onto complementary metal-oxide-semiconductor circuitry through the Bell Labs Lucent Technologies/George Mason University optoelectronic VLSI foundry. This system provides efficient execution of single-instruction multiple-data algorithms on large data fields and images.

Electrical, thermal and optomechanical packaging of large 2D optoelectronic device arrays for free-space optical interconnects

Innovative approaches to the design of a high-performance package module accommodating a array of surface-active devices indium bump bonded to a VLSI chip are presented. Electrical, thermal and optomechanical design considerations are discussed and experimental performance results of a prototype implementation are described. The package module supports 139 impedance-controlled signal connections as well as active temperature stabilization of the optoelectronic VLSI chip. The package module is compact, simple to assemble, alignment-tolerant and can be passively inserted into a free-space optical system with no need for further adjustments.

Design of an opto-electronic VLSI/parallel fibre bus

We present a design for an opto-electronic bus system based on commercial parallel fibre ribbon transmission systems and opto-electronic VLSI smart pixel arrays. We describe the design of the individual components, their integration, the performance limits and potential applications.

Hardware description language for optical processing (hadlop): a simulation environment for parallel optoelectronic architectures

We present a simulation environment for parallel optoelectronic data-processing systems, and we especially consider the fusion of optoelectronic integrated circuits and optical interconnection modules. hadlop, which stands for hardware description language for optical processing, is a simulator that works at the digital design level. So far, hadlop has allowed algorithm and architecture studies for smart-pixel systems. We have just begun to extend the capabilities of hadlop toward an automatic synthesis tool for three-dimensional optoelectronic VLSI circuits. A hadlop architecture will then be the basis for the automatic generation of detailed construction plans that consider the interaction between optical interconnection modules and optoelectronic integrated circuits. The simulation system is freeware and is available through the Internet at http://www2.informatik.uni-jena.de/pope/HADLOP/hadlop.html.

Specification for a reconfigurable optoelectronic VLSI processor suitable for digital signal processing

A concept for a parallel digital signal processor based on opticalinterconnections and optoelectronic VLSI circuits is presented. Itis shown that the proper combination of optical communication, architecture, and algorithms allows a throughput that outperformspurely electronic solutions. The usefulness of low-level algorithmsfrom the add-and-shift class is emphasized. These algorithms leadto fine-grain, massively parallel on-chip processor architectures withhigh demands for optical off-chip interconnections. A comparativeperformance analysis shows the superiority of a bit-serialarchitecture. This architecture is mapped onto an optoelectronicthree-dimensional circuit, and the necessary optical interconnectionscheme is specified.

Optoelectronic-VLSI: photonics integrated with VLSI circuits

Optoelectronic-VLSI (OE-VLSI) technology represents the intimate integration of photonic devices with silicon VLSI electronics. We review the motivations and status of emerging OE-VLSI technologies and examine the performance of OE-VLSI technology versus conventional wire-bonded OE packaging. The results suggest that OE-VLSI integration offers substantial power and speed improvements even when relatively small numbers of photonic devices are driven with commodity complementary metal-oxide-semiconductor logic technologies.

Demultiplexing 2.48-Gb/s optical signals with a CMOS receiver array based on clocked-sense-amplifiers

A repeater array consisting of clocked-sense-amplifier-based optical receivers driving receivers driving 850-nm optical modulators is used to demultiplex a 2.48-Gb/s optical signal into eight 311-Mb/s optical data streams. The synchronous detection provided by the clocked receivers allows 2.48-Gb/s signals to be demultiplexed despite a repeater bandwidth of roughly 350 MHz. The repeater array contains 16 elements, is fully functional, and is realized in a hybrid MQW/CMOS smart pixel optoelectronic VLSI technology. The CMOS circuits are made in a 0.35-μm linewidth process. Total power dissipation for the entire array is 11.5 mW, and 120-fJ optical input signals are used.

Asynchronous transfer mode distribution network by use of an optoelectronic VLSI switching chip

We describe a new optoelectronic switching system demonstration that implements part of the distribution fabric for a large asynchronous transfer mode (ATM) switch. The system uses a single optoelectronic VLSI modulator-based switching chip with more than 4000 optical input-outputs. The optical system images the input fibers from a two-dimensional fiber bundle onto this chip. A new optomechanical design allows the system to be mounted in a standard electronic equipment frame. A large section of the switch was operated as a 208-Mbits/s time-multiplexed space switch, which can serve as part of an ATM switch by use of an appropriate out-of-band controller. A larger section with 896 input light beams and 256 output beams was operated at 160 Mbits/s as a slowly reconfigurable space switch.

Optoelectronic VLSI switching chip with greater than 1 Tbit/s potential optical I/O bandwidth

The authors describe an optoelectronic switching chip with 1024 differential optical inputs and 1024 differential optical outputs with individual channels tested above 600 Mbit/s. The technology for the chip consists of 850 nm GaAs/AlGaAs multiquantum well (MQW) detectors and modulators, flip-chip bonded onto silicon CMOS with substrate removal to allow access to the optical devices.

Optical receivers for optoelectronic VLSI

We describe our work on the design and testing of optical receivers for use in optoelectronic VLSI. The local nature of the optoelectronic VLSI system permits novel receiver designs, incorporating multiple optical beams and/or synchronous operation, while the requirement of realizing large numbers of receivers on a single chip severely constrains area and power consumption. We describe four different receiver designs, and their different operating modes. Results include 1-Gb/s high-impedance, two-beam diode-clamped FET-SEED receivers, single and dual-beam transimpedance receivers realized with a hybrid attachment of multiple-quantum well devices to 0.8-/spl mu/m linewidth CMOS operating to 1 Gb/s, and synchronous sense-amplifier-based optical receivers with low (/spl sim/1 mW) power consumption. Finally, we introduce a measure of receiver performance that includes area and power consumption.

Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap

Technologies now exist for implementing dense surface-normal optical interconnections for silicon CMOS VLSI using hybrid integration techniques. The critical factors in determining the performance of the resulting photonic chip are the yield on the transceiver device arrays, the sensitivity and power dissipation of the receiver and transmitter circuits, and the total optical power budget available. The use of GaAs-AlGaAs multiple-quantum-well p-i-n diodes for on-chip detection and modulation is one effective means of implementing the optoelectronic transceivers. We discuss a potential roadmap for the scaling of this hybrid optoelectronic VLSI technology as CMOS linewidths shrink and the characteristics of the hybrid optoelectronic transceiver technology improve. An important general conclusion is that, unlike electrical interconnects, such dense optical interconnections directly to an electronic circuit will likely be able to scale in capacity to match the improved performance of future CMOS technology.

3-D integration of MQW modulators over active submicron CMOS circuits: 375 Mb/s transimpedance receiver-transmitter circuit

We accomplish the integration of GaAs-AlGaAs multiple quantum well modulators directly on top of active silicon CMOS circuits. This enables optoelectronic VLSI circuits to be achieved and also allows the design and optimization of the CMOS circuits to proceed independently of the placement and the bonding of surface-normal optical modulators to the circuit. Using this technique, we demonstrate operation of a 0.8 micron CMOS transimpedance receiver-transmitter circuit at 375 Mb/s.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>