Abstract
We describe our work on the design and testing of optical receivers for use in optoelectronic VLSI. The local nature of the optoelectronic VLSI system permits novel receiver designs, incorporating multiple optical beams and/or synchronous operation, while the requirement of realizing large numbers of receivers on a single chip severely constrains area and power consumption. We describe four different receiver designs, and their different operating modes. Results include 1-Gb/s high-impedance, two-beam diode-clamped FET-SEED receivers, single and dual-beam transimpedance receivers realized with a hybrid attachment of multiple-quantum well devices to 0.8-/spl mu/m linewidth CMOS operating to 1 Gb/s, and synchronous sense-amplifier-based optical receivers with low (/spl sim/1 mW) power consumption. Finally, we introduce a measure of receiver performance that includes area and power consumption.
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