Optimized Hardware Architecture Research Articles

Connection of H.264/AVC hardware IPs using a specific Networks-on-Chip

Real time and high quality video coding assured by new codec’s as the H.264/AVC is gaining a wide interest in the research and industrial community for different applications. Several new hardware implementations (IPs) have been proposed for the various processing elements of video codec’s. At the same time, several works have been proposed to integrate this IPs in single System-on-Chip (SoC) aiming to provide multi-processor systems (MPSoC) based on shared-bus architecture. Generally these systems present the disadvantages of signal propagation delays and signal integrity and scalability depending on the number of cores used. Network-on-Chip is a newly introduced paradigm to overcome the communication problems of System-on-Chip architectures. In this paper we propose an optimized hardware architecture for the H.264/AVC using a Network-on-Chip. Firstly, we performed a 3×3 mesh Network-on-Chip and then we connect the hardware IPs proposed for the H.264/AVC using a specific Network-Interface. We use only the information available on the H.264/AVC to locate manually the position of IPs on the network. The synthesis results of our implementations are compared with the ordinary shared-bus based network. Finally, we embed the Network-on-Chip based system in a complete System-on-Chip using the MicroBlaze processor and we compare the results.

Fully Binary Neural Network Model and Optimized Hardware Architectures for Associative Memories

Brain processes information through a complex hierarchical associative memory organization that is distributed across a complex neural network. The GBNN associative memory model has recently been proposed as a new class of recurrent clustered neural network that presents higher efficiency than the classical models. In this article, we propose computational simplifications and architectural optimizations of the original GBNN. This work leads to significant complexity and area reduction without affecting neither memorizing nor retrieving performance. The obtained results open new perspectives in the design of neuromorphic hardware to support large-scale general-purpose neural algorithms.

<inline-formula> <tex-math notation="TeX">$(M,p,k)$</tex-math></inline-formula>-Friendly Points: A Table-Based Method to Evaluate Trigonometric Function

Linear (order-1) function evaluation schemes, such as bipartite and multipartite tables, are usually effective for low- precision approximations. For high-output precision, the lookup table size is often too large for practical use. This brief investigates the so-called (M,p,k) scheme that reduces the range of an input argument to a very small interval so that trigonometric functions can be approximated with very small lookup tables and a few additions/subtractions. An optimized hardware architecture is presented and implemented in both a field-programmable gate array device and standard-cell-based technology. Experimental results show that the proposed scheme achieves more than a 50% reduction in total chip area compared with the best linear approach for a 24-bit evaluation.

Area Optimized FPGA-Based Implementation of The Sobel Compass Edge Detector

This paper presents a new FPGA resource optimized hardware architecture for real-time edge detection using the Sobel compass operator. The architecture uses a single processing element to compute the gradient for all directions. This greatly economizes on the FPGA resources' usages (more than 40% reduction) while maintaining real-time video frame rates. The measured performance of the architecture is 50 fps for standard PAL size video and 200 fps for CIF size video. The use of pipelining further improved the performance (185 fps for PAL size video and 740 fps for CIF size video) without significant increase in FPGA resources.

HSS 기반 초고속 LDPC 복호를 위한 구조

본 논문은 위성방송 전송 규격인 DVB-S2의 기반 채널 부호로 사용되는 LDPC를 고속 복호를 위해 HSS(Horizontal Shuffle Scheduling) 방식을 기반으로 고속 복호기 구조를 연구하였다. 첫째로 HSS방식에서 발생하는 메모리 충돌을 극복하는 방식을 제시한다. 둘째로 고속 복호를 위해 LUT(Look Up Table)을 이용하는 Sum-Product 알로리즘 대신 min값에서 scaling factor를 곱하는 Normalized Min-Sum 알고리즘을 사용하였으며, 성능 향상을 위해 check node에서 bit node로 입력되는 값의 부호를 확인하여 신뢰성 없는 값을 삭제하는 Self-Correct 방식을 제시하여 sum-product 방식에서 발생하는 bottle neck 현상을 하였다. 마지막으로 고속화를 위한 효율적인 메모리 구조를 제안한다. This paper proposes the high speed LDPC decoder structure base on the DVB-S2. Firstly, We study the solution to avoid the memory conflict. For the high speed decoding process the decoder adapts the HSS(Horizontal Shuffle Scheduling) scheme. Secondly, for the high speed decoding algorithm normalized Min-Sum algorithm is adapted instead of Sum-Product algorithm. And the self corrected is a variant of the LDPC decoding that sets the reliability of a Mc<TEX>${\rightarrow}$</TEX>v message to 0 if there is an inconsistency between the signs of the current incoming messages Mv'<TEX>${\rightarrow}$</TEX>c and the sign of the previous incoming messages Moldv'<TEX>${\rightarrow}$</TEX>c This self-corrected algorithm avoids the propagation on unreliable information in the Tanner graph and thus, helps the convergence of the decoder.Start after striking space key 2 times. Lastly, and this paper propose the optimal hardware architecture supporting the high speed throughput.

Optimized hardware architecture for object recognition and tracking

The recent research is focused on development of mobile vision systems and algorithms suitable for very large-scale integration implementation. These systems can be used in various applications. We propose a novel field-programmable gate array (FPGA)-based architecture for early vision. The central idea is to take into account the perceptual aspects of visual tasks inspired by biological vision systems: shape and color. For this reason, we propose an original approach based on a system implemented in an FPGA connected to a CMOS imager. The proposed algorithm implementation analysis and optimization methodology under resource constraints enable one to implement the algorithm on only one FPGA chip. To prove the proposed concept the system was implemented and tested on an autonomous mobile platform. The implementation framework enables direct algorithm implementation in application-specific integrated circuit.

Hardware acceleration of an RTP Proxy Server

More and more TVoIP services are emerging on the market using RTP to compensate for the dynamic routing. Interactive applications, however, still suffer from the network's long latency. Offloading to the access network offers a solution. In this paper we present an optimized hardware architecture for a proxy handling RTP packets delivering an acceleration ratio of over 440. The architecture has built-in support for Video-on-Demand, Time-Shifted TV and Fast Channel Change services, and has been successfully tested on a custom FPGA board.

Multiple Word-Length High-Level Synthesis

Digital signal processing (DSP) applications are nowadays widely used and their complexity is ever growing. The design of dedicated hardware accelerators is thus still needed in system-on-chip and embedded systems. Realistic hardware implementation requires first to convert the floating-point data of the initial specification into arbitrary length data (finite-precision) while keeping an acceptable computation accuracy. Next, an optimized hardware architecture has to be designed. Considering uniform bit-width specification allows to use traditional automated design flow. However, it leads to oversized design. On the other hand, considering non uniform bit-width specification allows to get a smaller circuit but requires complex design tasks. In this paper, we propose an approach that inputs a C/C++ specification. The design flow, based on high-level synthesis (HLS) techniques, automatically generates a potentially pipeline RTL architecture described in VHDL. Both bitaccurate integer and fixed-point data types can be used in the input specification. The generated architecture uses components (operator, register, etc.) that have different widths. The design constraints are the clock period and the throughput of the application. The proposed approach considers data word-length information in all the synthesis steps by using dedicated algorithms. We show in this paper the effectiveness of the proposed approach through several design experiments in the DSP domain.

ASIP Approach for Implementation of H.264/AVC

This paper presents an Application Specific Instruction Set Processor (ASIP) for implementation of H.264/AVC, called Video Specific Instruction-set Processor (VSIP). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has coprocessors for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The proposed VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. Moreover, the proposed hardware accelerators have small size, consume low power consumption, and thus, they can support real-time video processing. VSIP has been thoroughly verified using an FPGA board having the Xilinx? Virtex II. VSIP can implement a real-time H.264/AVC decoder. The proposed VSIP is one of promising solutions for video signal processing.

A Real-time Image Processing with a Compact FPGA-based Architecture

This study have presented a filed programmable gate array implementation of a real time video smoothing algorithm. In comparison with smoothing video techniques like deblocking filters in H.264 or smoothing in JPEG2000, the proposed method is implemented in hardware and its computational cost and complexity are reduced where all pixel processing related to uncompressed video is done on the fly. Our proposed architecture tries to optimize the design of a modified version of the Nagao filter in order to make video smoothing with respect to real time constraints. This filter have to smooth video before applying an edge extraction approach for manufacturing process control. The proposed architecture based on the RC1000P-P Virtex prototyping Board is analyzed to gain an understanding of the relationships between algorithmic features and implementation cost. Experimental results indicate that using this prototyping board with optimized hardware architecture; we can deliver real-time performances and an improvement in the video quality. This filter is capable to process a real time video with a high resolution and deliver 30 images per second at 10 MHz clock cycle.

A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000

In this paper, the design and implementation of an optimized hardware architecture in terms of speed and memory requirements for computing the tile-based 2D forward discrete wavelet transform for the JPEG2000 image compression standard, are described. The proposed architecture is based on a well-known architecture template for calculating the 2D forward discrete wavelet transform. This architecture is derived by replacing the filtering units by our previously published throughput-optimized ones and by developing a scheduling algorithm suited to the special features of our filtering units. The architecture exhibits high-performance characteristics due to the throughput-optimized filters. Also, the extra clock cycles required due to the tile-based version of the discrete wavelet transform are partially compensated by the proper scheduling of the filters. The developed scheduling algorithm results in reduced memory requirements compared with existing architectures.

Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks

This paper presents a new approach for detecting defects in analog integrated circuits using the feed-forward neural network trained by the resilient error back-propagation method. A feed-forward neural network has been used for detecting catastrophic faults randomly injected in a simple analog CMOS circuit by classification the differences observed in supply current responses of good and faulty circuit. The experimental classification was performed for time and frequency domain, followed by a comparison of results achieved in both domains. It was shown that neural networks might be very efficient and versatile approach for test of analog circuits since an arbitrary fault class or circuit's parameter can be analyzed. Considered defect types and their successful detection by the neural networks and a possible off-chip hardware implementation of the proposed technique are discussed as well. Moreover, optimized hardware architecture of the selected neural network type was designed using VHDL for FPGA realization.

A novel all-binary motion estimation (ABME) with optimized hardware architectures

We present a fast motion estimation algorithm using only binary representation, which is desirable for both embedded system and hardware implementation with parallel architectures. The key algorithm distinction is that only the high-frequency spectrum is used. Our experimental results show that it provides excellent performance at both low and high bit rates. Because of its binary-only representation, the proposed algorithm offers low computational complexity and low memory bandwidth consumption. For multimedia-embedded system design, we further investigated specific implementation techniques for several well-known hardware platforms including Intel x86 processors, single-instruction multiple-data processors, and systolic array circuit design. The systolic array architecture requires only single memory access for both the reference and current frames from the on-chip memory. Such an implementation provides an optimized solution with great throughput, while the quality is maintained. Finally, we show that our binarization methods are closely coupled to the accuracy of binary motion estimation algorithms. The binarization and coding efficiencies can be improved using various filters and binarization methods.

Hardware Support for Advanced Data Management Systems

This thesis considers the problem of the optimal hardware architecture for advanced data management systems, of which the REL system can be considered a prototype. Exploration of the space of architectures requires a new technique which applies widely varying work loads, performance constraints, and heuristic configuration rules with an analytic queueing network model to develop cost functions which cover a representative range of organizational requirements. The model computes cost functions, which are the ultimate basis for comparison of architectures, from a technology forecast. The discussion shows the application of the modeling technique to thirty trial architectures which reflect the major classifications of data base machine architectures and memory technologies. The results suggest practical design considerations for advanced data management systems.