Optimal Tile Research Articles

An optimized tiling pattern for multiobject spectroscopic surveys: application to the 4MOST survey

ABSTRACT Large multiobject spectroscopic surveys require automated algorithms to optimize their observing strategy. One of the most ambitious upcoming spectroscopic surveys is the 4MOST survey. The 4MOST survey facility is a fibre-fed spectroscopic instrument on the VISTA telescope with a large enough field of view to survey a large fraction of the southern sky within a few years. Several Galactic and extragalactic surveys will be carried out simultaneously, so the combined target density will strongly vary. In this paper, we describe a new tiling algorithm that can naturally deal with the large target density variations on the sky and which automatically handles the different exposure times of targets. The tiling pattern is modelled as a marked point process, which is characterized by a probability density that integrates the requirements imposed by the 4MOST survey. The optimal tilling pattern with respect to the defined model is estimated by the tiles configuration that maximizes the proposed probability density. In order to achieve this maximization a simulated annealing algorithm is implemented. The algorithm automatically finds an optimal tiling pattern and assigns a tentative sky brightness condition and exposure time for each tile, while minimizing the total execution time that is needed to observe the list of targets in the combined input catalogue of all surveys. Hence, the algorithm maximizes the long-term observing efficiency and provides an optimal tiling solution for the survey. While designed for the 4MOST survey, the algorithm is flexible and can with simple modifications be applied to any other multiobject spectroscopic survey.

Algorithms for Efficient Reproducible Floating Point Summation

We define “reproducibility” as getting bitwise identical results from multiple runs of the same program, perhaps with different hardware resources or other changes that should not affect the answer. Many users depend on reproducibility for debugging or correctness. However, dynamic scheduling of parallel computing resources, combined with nonassociative floating point addition, makes reproducibility challenging even for summation, or operations like the BLAS. We describe a “reproducible accumulator” data structure (the “binned number”) and associated algorithms to reproducibly sum binary floating point numbers, independent of summation order. We use a subset of the IEEE Floating Point Standard 754-2008 and bitwise operations on the standard representations in memory. Our approach requires only one read-only pass over the data, and one reduction in parallel, using a 6-word reproducible accumulator (more words can be used for higher accuracy), enabling standard tiling optimization techniques. Summing n words with a 6-word reproducible accumulator requires approximately 9 n floating point operations (arithmetic, comparison, and absolute value) and approximately 3 n bitwise operations. The final error bound with a 6-word reproducible accumulator and our default settings can be up to 2 29 times smaller than the error bound for conventional (recursive) summation on ill-conditioned double-precision inputs.

Numerical Methodology for the Conceptual Design of Conformal Ablative Heat Shields

Conformal ablators are low-density composite materials comprising a flexible fibrous substrate and polymer matrix. Recent advancements have improved the efficiency of conformal ablator fabrication through vacuum infusion processing, which injects resin into a fiber substrate enclosed in a matched mold under vacuum. A conceptual design methodology was developed combining a Darcy’s law simulation of the mold filling process with optimal tile layout and material property estimation. The framework allows rapid evaluation of changes to constituent materials, process parameters, and heat-shield geometry, and their impact on manufacturing and material properties. Results for a 4.5 m, 70 deg sphere-cone aeroshell demonstrate the advantages of the integrated approach. The mold filling simulation is then compared with experimental results.

Visual Attention-Aware Omnidirectional Video Streaming Using Optimal Tiles for Virtual Reality

Owing to its interactive look around nature and very large resolution requirement, providing immersive omnidirectional video (ODV) streaming experiences in virtual reality applications demands cost-effective solutions to meet both the content delivery network and device constraints. In this paper, we introduce an adaptive ODV streaming pipeline that optimizes dynamic adaptive streaming over HTTP representations of ODV content considering their visual attention (VA) maps. The main contribution of this paper is the use of VA maps: 1) to compute a novel objective quality metric that captures the fact that not all of the ODV is actually watched by users: the VA spherical weighted-based objective quality measurement; 2) to define optimal tile representations of the ODV frames, namely, tiling schemes, which are composed of variable-sized and non-overlapping tiles; and 3) to efficiently distribute a given bitrate budget among the set of tiles within a tiling scheme for an ODV. We evaluate the proposed system performance with varying bandwidth conditions and the tracked head orientations from user experiments. Results show that the proposed system significantly outperforms the existing non-tiled and tile-based streaming solutions.

Checkpointing-Aware Loop Tiling for Energy Harvesting Powered Nonvolatile Processors

As power failures often occur in energy harvesting powered nonvolatile processors (NVPs), checkpointing is needed during program execution. It is observed that checkpointing is implemented with high overhead in applications with loops, because a large amount of data needs backup during loop execution. As such, we are motivated to reduce the amount of checkpointing data by analyzing data locality and shortening data lifetime in loops. This paper proposes a checkpointing-aware loop tiling technique which targets to reduce the checkpointing and recovering overheads for loops. Specifically, we first derive the optimal tile size for nested loops considering checkpointing distance and data dependencies. Then, the implementations of checkpointing and recovering for tiled loops are presented. Finally, the experiments are conducted to evaluate the effectiveness of the proposed method. The experimental results show that compared to the no-tiling method, the checkpointing-aware loop tiling method reduces the checkpointing and recovering data by 36.2% on average and reduces the total execution time and dynamic energy for checkpointing and recovering by 27.2% and 22.9% on average, respectively.

An efficient tile size selection model based on machine learning

Tiling is a classic loop optimization to improve data locality and achieve coarse-grained parallelism. Tile size selection (TSS) plays an important role in tiling to determine the performance of tiled codes. Most of the previous TSS approaches involve much highly skilled manpower, but it is still difficult to find the optimal tile sizes. In this article, we propose an efficient TSS model using machine learning technique to predict optimal rectangular tile sizes for a given program on multi-core processors. A set of loop features is extracted on tiled codes to capture the locality of data references and the effect of vectorization in tiled loop dimensions. Using the features and corresponding best tile sizes, the generalized regression neural network is employed to build the TSS model, hiding the complicated interactions between tile sizes and underlying factors. Although the impact of multithreading is not directly considered in training the model, the predicted tile sizes can be well adapted to different numbers of threads. Experimental results show that the predicted tile sizes achieve 90% and 81% of the optimal performance on average for 20 selected benchmarks on an Intel Xeon and an IBM Power6 multi-core platforms, respectively. The optimal performance is delivered by the tile sizes that are obtained through a heuristically exhaustive search. Our TSS model outperforms an artificial neural network (ANN)-based TSS prediction model which depends on the prefetched features by over 9% in average performance for 9 benchmarks. It also outperforms a state-of-the-art analytical TSS model which uses the cache set associativity and interaction with the single instruction multiple data (SIMD) units to estimate the optimal tile sizes by over 7% in average performance for 7 benchmarks.

Parallel Seismic Modeling Based on OpenMP+AVX and Optimization Strategy

This paper describes parallel simulation of the memory/computation-intensive acoustic wave equation with CPU template buffer optimization. Considering the 8-core CPU shared storage platform as an example, we obtain a one-time speed-up ratio of 6.7× compared with the serial program by using a coarse-grained OpenMP parallel scheme. Then, data is vectorized on the template buffer using the single instruction-multiple data (SIMD) technique to further exploit the computing potential of the CPUs. We apply an 8-channel parallel vector to simulate seismic wavefields with the 256-bit advanced vector extensions (AVX) instruction set. This increases the computing bandwidth, thus eliminating a significant volume of the computing instructions and obtaining a secondary speed-up ratio of 3–7×. In addition, we use 32-byte data alignment, shortest data direction vectorization, and loop tiling optimization algorithm to achieve faster program execution. Finally, we analyze the factors affecting the secondary speed-up of AVX through three-dimensional modeling experiments with the salt model. The results indicate that the memory, cache, and register can better cooperate with each other and the speed-up is increased by optimizing the AVX algorithm.

Road map partitioning for routing by using a micro steady state evolutionary algorithm

The constantly increasing number of vehicles and the immense size and complexity of road maps set a tough scenario for real world routing. In spite of the tremendous efforts done up to date to tackle this problem, finding the shortest-path in practice is still a challenge due to memory and time constrains. Moreover, most of the efforts have been focused on algorithmics, setting aside the management of the data. However, memory and time constraints are very important to actually construct real world applications, advising a new global approach. In this study we propose a holistic strategy for finding the shortest-path based on efficiently managing the road map data. Our proposal is based on the tile map partitioning, a logic geographical partition strategy.We have developed a routing system highly scalable based on a micro steady state evolutionary algorithm to find the optimal tile map partitioning. We show the actual efficiency and scalability by using the road maps of Malaga, Spain, and Mexico City, making it clear the significant reductions in the time needed to compute the shortest-path (in a real application), what is a key issue that can be freely exploited in future open software for maps.

GW170817: Swift UV detection of a blue kilonova, and improving the search in O3

AbstractSwift’s rapid slewing, flexible planning, and multi-wavelength instruments make it the most capable space-based follow-up engine for finding poorly localized sources. During O1 and O2 Swift successfully tiled hundreds of square-degrees of sky in the LVC localization regions, searching for, and identifying, possible X-ray and UV/O transients in the field. Swift made important contributions to the discovery and characterization of the kilonova AT 2017gfo, discovering the UV emission and providing the deepest X-ray upper limits in the first 24 hours after the trigger, strongly constraining the dynamics and geometry of the counterpart. Swift tiled 92% of the galaxy convolved error region down to average X-ray flux sensitivities of 10−12 erg cm−2 s−1, significantly increasing our confidence that AT 2017gfo is indeed the counterpart to GW 170817 and sGRB 170817. However, there remains significant room for improvement of Swift’s follow-up in preparation for O3. This will take the form of both revised observation strategy based on detailed analysis of the results from O2, and significant changes to Swift’s operational capabilities. These improvements are necessary both for maximizing the likelihood that Swift finds a counterpart, and minimizing the impact that follow-up activities have on other Swift science priorities. We outline areas of improvement to the observing strategy itself for optimal tiling of the LVC localization regions. We also discuss ongoing work on operational upgrades that will decrease latency in our response time, and minimize impact on pre-planned observations, while maintaining spacecraft health and safety.

Irregular Phased Array Tiling by Means of Analytic Schemata-Driven Optimization

The design of subarrayed planar phased arrays characterized by an irregular organization of domino-shaped tiles is addressed. Starting from optimal tiling theorems drawn from mathematical theory, an enumerative approach able to retrieve the optimal clustering providing the maximum aperture coverage and the best radiation performance is proposed to deal with the synthesis of low-/medium-size rectangular arrays. Based on the same optimal theorems and still exploiting the algorithmic procedures at the basis of the enumerative approach, an innovative schemata-based optimization method is introduced for designing large arrays, as well. A set of representative results, concerned with ideal as well as real radiating elements, is reported and discussed to highlight the features and the potentialities of the proposed analytically based design framework.

TOAST: Automatic tiling for iterative stencil computations on GPUs

SummaryThe stencil pattern is important in many scientific and engineering domains, spurring great interest from researchers and industry. In recent years, various optimizations have been proposed for parallel stencil applications running on graphics processing units (GPUs). In particular, tiling is a technique that can significantly enhance application performance by improving data locality and by reducing the volume of communication between host memory and GPU. In addition, tiling enables stencil applications to process inputs that are larger than the physical GPU memory. However, implementing tiling efficiently is complex, time‐consuming, and error‐prone. In this paper, we propose transparently optimized automatic stencil tiling (TOAST), an automatic tiling mechanism for iterative stencil computations running on GPUs; TOAST has 3 main benefits: (1) It incorporates an optimization model that seeks to maximize data reuse within tiles while respecting the amount of dynamically available GPU memory; (2) it offers a virtualized GPU memory for stencil computations, allowing for large input data; and (3) it performs optimal tiling transparently to the developer of the parallel stencil application. The current implementation of TOAST augments the PSkel framework with an internal solver based on genetic algorithms. Our experimental results show that TOAST improves the performance of iterative stencil applications by up to 13 × compared with their multithreaded (central processing unit–based) optimized versions and up to 48 × compared with a naive tiling approach on GPU. The TOAST mechanism is able to automatically achieve a low percentual overhead of data management compared with actual stencil computation.

Curvelet transform with learning-based tiling

Compact signal and image representations are of crucial importance in a variety of application areas. Wavelet and wavelet-like transforms typically divide the frequency plane in a systematic non-adaptive approach. In this paper, we propose a learning-based method for adapting frequency domain tiling using the curvelet transform as the basis algorithm. The optimal tiling that better represents a single image or a given class of images is computed using denoising performance as the cost function. Simulated additive white Gaussian noise is removed from a given image using a thresholding algorithm. The curvelet tiling that generates maximal denoising performance as measured by PSNR or the logarithm of mean squared error (MSE) is considered optimal. The major adaptations considered are the number of scale decompositions, angular decompositions per scale/quadrant, and scale locations. A global optimization algorithm combining the three adaptations is proposed. Signal representations by adaptive curvelets are shown to outperform default curvelets in partial reconstruction error. Furthermore, adaptive curvelets are used in compressed sensing recovery of incomplete seismic datasets and face images. Visual and numerical improvements across a variety of images and different subsampling ratios are reported. Finally, adaptive curvelets denoising performance is tested on seismic datasets. Our results establish clear numerical and visual performance advantages over the default curvelet transform and the non-local means algorithm (NLM).

Simple, Accurate, Analytical Time Modeling and Optimal Tile Size Selection for GPGPU Stencils

Stencil computations are an important class of compute and data intensive programs that occur widely in scientific and engineeringapplications. A number of tools use sophisticated tiling, parallelization, and memory mapping strategies, and generate code that relies on vendor-supplied compilers. This code has a number of parameters, such as tile sizes, that are then tuned via empirical exploration. We develop a model that guides such a choice. Our model is a simple set of analytical functions that predict the execution time of the generated code. It is deliberately optimistic, since tile sizes and, moreover, the optimistic assumptions are intended to enable we are targeting modeling and parameter selections yielding highly tuned codes. We experimentally validate the model on a number of 2D and 3D stencil codes, and show that the root mean square error in the execution time is less than 10% for the subset of the codes that achieve performance within 20% of the best. Furthermore, based on using our model, we are able to predict tile sizes that achieve a further improvement of 9% on average.

Parallel HEVC decoding with asymmetric mobile multicores

Recently, the necessity of parallel ultra-high definition (UHD) video processing has been emerging, and the usage of the computing systems that have asymmetric processors, such as ARM big.LITTLE, is actively increasing. Thus, a new parallel UHD video processing method optimized for asymmetric multicore systems is essential. This paper proposes a novel High Efficiency Video Coding (HEVC) Tile partitioning method for the parallel processing by analyzing the computational power of asymmetric multicores. (1) The proposed method analyzes the computing power of asymmetric multicores and (2) the regression model of computational complexity per video resolution. Lastly, (3) the model determines the optimal HEVC Tile resolution for each core and partitions and allocates the Tiles to suitable cores. Experimental results with the test sequences of common test condition (CTC) show that the decoding speed improved by 17 % with implemented multi-threading module on ARM asymmetric multicore systems.

Performance Optimization of 3D Lattice Boltzmann Flow Solver on a GPU

Lattice Boltzmann Method (LBM) is a powerful numerical simulation method of the fluid flow. With its data parallel nature, it is a promising candidate for a parallel implementation on a GPU. The LBM, however, is heavily data intensive and memory bound. In particular, moving the data to the adjacent cells in the streaming computation phase incurs a lot of uncoalesced accesses on the GPU which affects the overall performance. Furthermore, the main computation kernels of the LBM use a large number of registers per thread which limits the thread parallelism available at the run time due to the fixed number of registers on the GPU. In this paper, we develop high performance parallelization of the LBM on a GPU by minimizing the overheads associated with the uncoalesced memory accesses while improving the cache locality using the tiling optimization with the data layout change. Furthermore, we aggressively reduce the register uses for the LBM kernels in order to increase the run-time thread parallelism. Experimental results on the Nvidia Tesla K20 GPU show that our approach delivers impressive throughput performance: 1210.63 Million Lattice Updates Per Second (MLUPS).

HARDWARE-AWARE TILING OPTIMIZATION FOR MULTI-CORE SYSTEMS

This paper presents a proposition of the new tool which improves tiling efficiency for given hardware architecture. This article also describes the correlation between changing hardware architecture and methods of software optimization. First chapter includes short description of the change in hardware architecture which has occurred in recent 10 years. The second chapter provides an overview of tools which will be used in further research. The consecutive sections contain description of proposed hardware-aware tool for optimal tiling.

1119 任意形状領域に対するタイル配置最適化の一手法(最適化応用)

1119 任意形状領域に対するタイル配置最適化の一手法(最適化応用)

Tile size selection revisited

Loop tiling is a widely used loop transformation to enhance data locality and allow data reuse. In the tiled code, however, tiles of different sizes can lead to significant variation in performance. Thus, selection of an optimal tile size is critical to performance of tiled codes. In the past, tile size selection has been attempted using both static analytical and dynamic empirical (auto-tuning) models. Past work using static models assumed a direct-mapped cache for the purpose of analysis and thus proved to be less robust. On the other hand, the auto-tuning models involve an exhaustive search in a large space of tiled codes. In this article, we propose a new analytical model for tile size selection that leverages the high set associativity in modern caches to minimize conflict misses. Our tile size selection model targets data reuse in multiple levels of cache. In addition, it considers the interaction of tiling with the SIMD unit in modern processors in estimating the optimal tile size. We find that these factors, not considered in previous models, are critical in developing a robust model for tile size selection. We implement our tile size selection model in a polyhedral compiler and test it on 12 benchmark kernels using two different problem sizes. Our model outperforms the previous analytical models that are based on reusing data in a single level of cache and achieves an average performance improvement of 9.7% and 20.4%, respectively, over the best square (cubic) tiles for the two problem sizes. In addition, the tile size chosen by our tile size selection algorithm is similar to the best performing size obtained through an extensive search, validating the analytical model underlying the algorithm.

Tile size selection revisited

Loop tiling is a widely used loop transformation to enhance data locality and allow data reuse. In the tiled code, however, tiles of different sizes can lead to significant variation in performance. Thus, selection of an optimal tile size is critical to performance of tiled codes.

Self adaptive run time scheduling for the automatic parallelization of loops with the C2μTC/SL compiler

• We solve the hyperplane model at run time by scheduling tasks in parallel. • We improve the solution to be self adaptive and able to load balance. • We show that our method accurately computes the optimal tile size. • We get comparable execution times with compile-time methods. In this paper we suggest a new approach for solving the hyperplane problem, also known as “wavefront” computation. In direct contrast to most approaches that reduce the problem to an integer programming one or use several heuristic approaches, we gather information at compile time and delegate the solution to run time. We present an adaptive technique which intuitively calculates which new threads will be able to be executed in the next computation cycle based on which threads are executed in the current one. Moving the solution to the run time environment provides us with higher versatility alongside a perfect solution of the underlying hyperplane pattern being discovered without the need to perform any prior calculations. The main contribution of this paper is the presentation of the self adaptive algorithm, an algorithm which does not need to know the tile size (which controls the granularity of parallelism) beforehand. Instead, the algorithm itself adapts the tile size while the program is running in order to achieve optimal efficiency. Experimental results show that if we have a sufficient number of parallel processing elements to diffuse the scheduler’s workload, its overhead becomes low enough that it is overshadowed by the net gain in parallelism. For the implementation of the algorithm we suggest, and for our experimentations our parallelizing compiler C2μTC/SL is used, a C parallelizing compiler which maps sequential programs on the SVP processor and model.